Tutorial QAM16

XY DNG H THNG
THU PHT 16-QAM
Mc lc
XY DNG H THNG
THU PHT 16-QAM
Danh sch bng
Danh sch hnh v
1 Quy trnh thit k b x l bng gc trong thng tin s
1.1
Kho st thut ton . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
La chn kin trc thit k . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Thit k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Trin khai trn phn cng(HDL/FPGA) . . . . . . . . . . . . . . . .
1.5
Tng hp v layout ASIC
. . . . . . . . . . . . . . . . . . . . . . . .
2 TRIN KHAI THUT TON 16-QAM TRN MATLAB
2.1
u Nhc im 16-QAM . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Transmitter 16-QAM . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
M Ha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Thit k b m ha v gii m chp s dng thut ton Viterbi
2.2.3
Format into Symbols (QAM mapping) . . . . . . . . . . . . .
10
2.2.4
Zero Padding (Upsampling) . . . . . . . . . . . . . . . . . . .
12
MC LC
2.3
2.4
2.2.5
Raise Cosine Filtering (FIR filter) . . . . . . . . . . . . . . . .
13
2.2.6
Digital Sin/Cos Oscilator (NCO) . . . . . . . . . . . . . . . .
16
2.2.7
Digital Analog Convert(ADC) . . . . . . . . . . . . . . . . . .
16
Receiver 16-QAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
2.3.1
Timing phase recovery . . . . . . . . . . . . . . . . . . . . . .
17
2.3.2
Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . .
19
2.3.3
Searching start symbol . . . . . . . . . . . . . . . . . . . . . .
24
2.3.4
Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
So Snh Kt Qu . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.4.1
Th Mt . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.4.2
M Phng Monte-Carlo . . . . . . . . . . . . . . . . . . . . .
26
2.4.3
La chn thng s cho Raise Cosine Filter . . . . . . . . . . .
27
2.4.4
M Gray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
2.4.5
ng B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
3 THIT K
33
3.1
Tng Quan V Simulink . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.2
M Phng H Thng 16-QAM trn Simulink . . . . . . . . . . . . . .
34
3.2.1
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.2.2
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
4 Specification Design
4.1
54
Xy dng specification design . . . . . . . . . . . . . . . . . . . . . .
54
4.1.1
Cyclic prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.1.2
Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
4.1.3
Zero padder . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
4.1.4
Raised cosin filter . . . . . . . . . . . . . . . . . . . . . . . . .
59
4.1.5
Carrier multiplier . . . . . . . . . . . . . . . . . . . . . . . . .
60
MC LC
4.1.6
Pilot inserter . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
4.1.7
Cut pilot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4.1.8
Sampling
65
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Trin khai phn cng HDL

5.1
5.2
74
Tng quan v verilog . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.1.1
Verilog l g . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.1.2
M hnh m t phn cng . . . . . . . . . . . . . . . . . . . .
75
T chc file verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
Ti liu tham kho
77
Danh sch bng

4.1
Tn hiu vo/ra ca khi cyclic prefix . . . . . . . . . . . . . . . . . .
56
4.2
Tn hiu vo/ra ca khi mapper . . . . . . . . . . . . . . . . . . . .
58
4.3
M ha ca khi mapper . . . . . . . . . . . . . . . . . . . . . . . . .
59
4.4
Tn hiu vo/ra ca khi zero padder . . . . . . . . . . . . . . . . . .
61
4.5
Tn hiu vo/ra ca khi raised cosin filter . . . . . . . . . . . . . . .
62
4.6
gi tr p ng xung ca khi raised cosin filter . . . . . . . . . . . .
66
4.7
Tn hiu vo/ra ca khi carrier multiplier . . . . . . . . . . . . . . .
66
4.8
gi tr ca sng mang sin v cosin . . . . . . . . . . . . . . . . . . . .
69
4.9
Tn hiu vo/ra ca khi pilot inserter . . . . . . . . . . . . . . . . .
71
4.10 Tn hiu vo/ra ca khi cut pilot . . . . . . . . . . . . . . . . . . . .
72
4.11 Tn hiu vo/ra ca khi sampling . . . . . . . . . . . . . . . . . . .
72
Danh sch hnh v

1.1
Quy trnh thit k b x l bng gc . . . . . . . . . . . . . . . . . .
1.2
M hnh m phng HIL cho h thng thng tin s . . . . . . . . . . .
2.1
S khi Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
S khi Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Th Chm Sao 16-QAM . . . . . . . . . . . . . . . . . . . . . . .
12
2.4
Th Chm Sao 16-QAM khi c nhiu . . . . . . . . . . . . . . . .
13
2.5
code thc hin trn Matlab . . . . . . . . . . . . . . . . . . . . . . .
14
2.6
code chuyn i sang Simulink . . . . . . . . . . . . . . . . . . . . . .
15
2.7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.8
Dng ca chui k hiu sau khi thc hin Upsampling . . . . . . . . .
17
2.9
p ng tn s ca Raise Code Filter khi thay i . . . . . . . . .
18
2.10 S khi Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
2.11 S khi Base Band Receiver . . . . . . . . . . . . . . . . . . . . .
20
2.12 Phng php ly mu Early-Later . . . . . . . . . . . . . . . . . . . .
21
2.13 Hin Tng quay k hiu khi lch pha ca sng mang v b to dao
ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.14 S khi Loop Filter(D-PLL bc 2) . . . . . . . . . . . . . . . . . .
23
2.15 S khi b to dao ng NCO . . . . . . . . . . . . . . . . . . . .
23
2.16 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
DANH SCH HNH V
2.17 kt qu m phng tn hiu trn nhiu h thng 16-QAM . . . . . . .
27
2.18 kt qu nh gi SNR ph thuc vo Ns ym . . . . . . . . . . . . . .
28
2.19 BER s dng m Gray v khng s dng Gray
. . . . . . . . . . . .
29
2.20 ng gi data trong 16-QAM . . . . . . . . . . . . . . . . . . . . . .
30
2.21 Tn hiu Thu b xoay . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.22 Tn hiu Thu khi s dng khi synchronization . . . . . . . . . . . .
32
3.1
S khi 16-QAM trn Simulink . . . . . . . . . . . . . . . . . . . .
35
3.2
S khi 16-QAM trn Simulink . . . . . . . . . . . . . . . . . . . .
37
3.3
S khi Graycode . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
3.4
S khi M ode_16QAM . . . . . . . . . . . . . . . . . . . . . . . .
38
3.5
S khi insert_pilot . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.6
S khi receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
3.7
khi vector_receiver . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.8
khi LO_rec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
3.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
3.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
3.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
3.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
3.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
3.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
3.17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
3.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
3.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
DANH SCH HNH V
3.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
4.1
S khi pht . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.2
S khi thu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.3
Khi cyclic prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
4.4
Biu dng sng khi cyclic prefix . . . . . . . . . . . . . . . . . . .
57
4.5
Khi mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
4.6
Chm sao iu ch khi mapper . . . . . . . . . . . . . . . . . . . . .
59
4.7
Biu dng sng khi mapper . . . . . . . . . . . . . . . . . . . . .
60
4.8
Khi zero padder . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.9
M t khi zero padder . . . . . . . . . . . . . . . . . . . . . . . . . .
62
4.10 Biu dng sng khi zero padder . . . . . . . . . . . . . . . . . . .
63
4.11 Khi raised cosin filter . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4.12 M t khi raised cosin filter . . . . . . . . . . . . . . . . . . . . . . .
64
4.13 p ng xung khi raised cosin filter . . . . . . . . . . . . . . . . . .
65
4.14 Biu dng sng khi raised cosin filter . . . . . . . . . . . . . . . .
67
4.15 Khi carrier multiplier . . . . . . . . . . . . . . . . . . . . . . . . . .
67
4.16 M t khi carrier multiplier . . . . . . . . . . . . . . . . . . . . . . .
68
4.17 Sng mang sin ca khi carrier multiplier . . . . . . . . . . . . . . . .
68
4.18 Sng mang cos ca khi carrier multiplier
. . . . . . . . . . . . . . .
69
4.19 Biu dng sng khi carrier multiplier . . . . . . . . . . . . . . . .
70
4.20 Khi cyclic prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
4.21 Biu dng sng khi pilot inserter . . . . . . . . . . . . . . . . . .
71
4.22 Khi cut pilot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
4.23 Biu dng sng khi cut pilot
. . . . . . . . . . . . . . . . . . . .
73
4.24 Khi sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
Chng 1
Quy trnh thit k b x l bng
gc trong thng tin s
thit k bt k mt h thng thng tin s no ta u cn thc hin 5 giai on
(Hnh 1.1) gm: Kho st thut ton, la chn kin trc thit k, thit k, trin khai
trn phn cng(HDL/FPGA), tng hp v layout ASIC. Sau y ta s tm hiu v
nhim v v cch thc thc hin ca tng giai on.
1.1
Kho st thut ton
T nhng yu cu ban u, chng ta s dng cc m hnh v cng thc l thuyt

tm ra cch ph hp gii quyt vn . Sau , cc bc trin khai c a ra mt
cch r rng, chi tit theo trnh t h thng. Cc la chn cng ngh, thit b, k
thut m ha, iu ch cng c cp ti xem xt tnh kh thi ca vic thc
hin thut ton. Cui cng ta tin hnh thit lp cc iu kin( V d nh s bit m
ha cho u vo v u ra ca h thng) v nh gi c nh hng cc tham s
n cc thng s x l tn hiu( v d nh yu cu SNR ti thiu l bao nhiu).
thc hin cng vic nh gi thut ton chng ta c th dng cc cng c ph bin
1
CHNG 1. QUY TRNH THIT K B X L BNG GC TRONG THNG TIN S2
Algorithm
Architecture synthesis
Architecture retiming
and optimization
HDL/FPGA
Implementation
Asic Implementation
Hnh 1.1: Quy trnh thit k b x l bng gc
hin nay l Matlab hoc C. Phng php c dng l Monte-Carlo. y l cch

thc m phng s dng cc tp bin u vo ngu nhin phng theo cc iu kin
thc t nh gi cht lng ca thut ton. Trng hp ph bin l s dng m
phng Monte-Carlo c lng t s li bit BER. chnh xc ca cc c lng
thu c t m phng Monte-Carlo s ph thuc vo kch thc mu N , kh nng
ti to li mu u vo, v chnh xc cc gi thit m hnh ha. Cui cng, chng
ta phi a ra gii php ti u mm : bit m ha, php ton lm trn, tr ca
mch (latency), cc b nhn, b cng, . . .
1.2
La chn kin trc thit k
thit k ra mt h thng m bo yu cu ca thut ton c rt nhiu m hnh.

C th k ra nh: pipeline, parallel, in-space, ... Mi m hnh li c mt u nhc
im ring. Cc thng s nh gi cht lng ca cc m hnh l: Area, Throughput,
Power. V vy vic chn ra mt thit k l rt quan trng, n ty thuc vo yu cu
thit k ca d n. Ngoi ra mi mt m hnh thit k u c nhng kh khn ring
cn gii quyt nn vic la chn kin trc ph hp cn ph thuc vo thi gian thit
k v c con ngi na v vy cn phi xem xt k lng.
Kinh nghim cho phn ny l tham kho cng nhiu bi bo v project cng tt.
Sau chng ta phi tng hp ra cc gii php cng vi phc tp, im mnh v
iu yu ca chng. T xy dng h thng ca chng ta mt cch ph hp nht.
1.3
Thit k
Sau khi la chn kin trc, ta phi thit k c th mch. Chng ta cn chia nh
cc thit k cng su cng tt v t cc tn hiu iu khin cho ph hp. Thc t
to ra m hnh tht rt tn km v tin ca cng nh thi gian, v th vic m
hnh ha kt hp m phng c ngha ht sc quan trng. M hnh trn Simulink

cho php quan st c qu trnh hot ng, nh gi cc yu cu p ng ca h
thng trc khi trin khai thc nghim.
Khi trin khai trn Simulink, cc chc nng khc nhau ca h thng c phn
ra r rng thnh cc khi ring r. Da trn c s nh gi hiu qu lm vic ca
cc khi ny, ta s ti u n gin ha cng nh nng cao chnh xc. y s
chnh l m hnh chun mc cho vic trin khai thc t h thng trn phn cng
HDL/FPGA.
Kt qu: Sau khi thit k xong, ta c th vit c 1 design specification. N bao
gm ton b data flow trong mch, cc chc nng ca cc tn hiu.
1.4
Trin khai trn phn cng(HDL/FPGA)
y l bc to tin cho vic hin thc ha thit k ngoi thc t. Cc board

FPGA s c dng chy th thit k, nh gi hiu nng, nng lng... Nu vic
nh gi ny thnh cng, ta s tip tc chuyn sang bc ch to; ngc li, ta s
tip tc ti u, m phng h thng p ng c cc yu cu mong mun.
Chng ta trin khai bc ny da trn m hnh Hardware in the Loop (HIL)(Hnh
1.2). HIL l phng php m phng kt hp gia ngn ng phn cng HDL vi
Simulink. u tin, cc khi x l s bng gc trn Simulink c trin khai bng
code HDL. Sau , ta dng cng c Sysgen ca Xilinx thay th cc khi c sn
trong thit k trn Simulink bng cc khi s dng code HDL. H thng s hot ng
bng u vo ngu nhin trn Simulink, cc khi x l chy trn board FPGA v u
ra c a ngc v Simulink so snh v nh gi.
Khi trin khai code HDL chng ta nn tham s ha d liu cho tn hiu u vo,
u ra thit k tr nn mm do trong vic thay i kch thc cc tn hiu ny.
Mt im ng lu trong phn ny l Coding Style. i vi mi hng (Altera,
Hnh 1.2: M hnh m phng HIL cho h thng thng tin s

Xilinx, ...) pht trin board FPGA u c mt coding style khc nhau, iu ny nhm
m bo code HDL c synthesis hiu qu nht. V vy cn xc nh board FPGA
lm vic v tm hiu cch vit code ca hng .
1.5
Tng hp v layout ASIC
Chng ta s dng b cng c Synopsys thc hin tng hp v layout ASIC. Sau
khi c bn thit k ASIC v qua nhiu bc kim duyt, ta hon ton c th mang
i ch to v thu v mt vi mch hon chnh vi cng ngh mong mun.
Chng 2
TRIN KHAI THUT TON
16-QAM TRN MATLAB
2.1
u Nhc im 16-QAM
M-QAM l phng php iu ch phase v iu ch bin da trn s kt hp ca

ASK v PSK. Trong M l s im trn chm sao m ha. M cng tng t l li tn
hiu cng t, v tc bit cng nh. Trong bi ny ta xy dng h thng thu pht
16-QAM.
Cc phng php iu ch PSK, FSK khi tng M (M>8) th khong cch hnh
hc gia cc im trn chm sao s gn li, iu ny tng ng vi vic xc sut
xy ra li tng ln, dn n phi tng cng sut pht m bo cht lng ca tn
hiu thu. Mt khc QAM c hiu sut ph tn cao nn ph hp vi vic truyn dn
tc bit cao trn cc bng tn hn ch.
Nhc im ln nht ca QAM l do bin ca cc tn hiu khc nhau nn dng
QAM s gp kh khn khi phi truyn vi cng sut ln (v t s gia cng sut cu
tn hiu ln nht v tn hiu nh nht trong b tn hiu truyn i > 1). Kh khn ny
c th nh sau: khuch i cc tn hiu nh t th khi tn hiu i qua b khuch
6
CHNG 2. TRIN KHAI THUT TON 16-QAM TRN MATLAB
i s lm cho b khuch i lm vic vng bo ha cho nn tn hiu u ra ca

b khuch i s b mo dn n li pha thu. Ngc li nu mun khuch i tn
hiu ln m khng b mo th im lm vic ca b khuch i li li gn gc ta
cho nn hiu sut ca b khuch i s gim xung ng k.
ph hp vi vic test th nghim trn cc thit b tht ca phng lab EDABK
chn tn s pht 2.4Ghz (bng tn t do), cc thng s trung tn v base band s
c tnh ton v la chn ph hp.
Transmitter 16-QAM
Tn s ct fc =
20Mhz
tn s u ra f =
5Mhz
Fcenter = 144Mhz
BW = 10
Mixes up
DAC
X
LO1 = 144Mhz
f1= fIF
Di thng 0-10Mhz
~
Fcenter = 2.442Ghz
BW = 50
Gain = 50dB
NF ~ 4dB
Fcenter = 2.442Ghz
BW = 50 Mixes up
Fcenter = 144Mhz
BW = 30
Gain = 50dB
NF ~ 4dB
BPF2
f2= fRF
~
LO2 = 2.298Ghz
Hnh 2.1: S khi Transmitter
IF Amp
Power
Amp
2.2
2.2.1
M Ha
c c dng bit u vo cho 16-QAM t cc ngun tin ban u l file text, file
m thanh hoc mt dng tn hiu tng t khc. Vic u tin cn thc hin l M
Ngun (Source Coding) mc ch l bin i ngun tin tin cho vic lu tr bo
mt: m nn, m bo mt.
M Knh (Channel Coding) bin i tp d liu ngun bng mt thut ton cho
php pht hin v sa li, lm chc tin cy ca thng tin, gim t s li bit BER.
M knh chia lm hai loi chnh bao gm
1. m c th t pht hin v sa li (FEC-forward error correction): c s dng
vi cc h thng thi gian thc nh thoai, truyn hnh.
(a) m khi tuyn tnh-m khng nh: ph bin hay s dng l m Reed
Solomon code.
(b) m chp, vng-m c nh: ph bin s dng m chp, gii m Viterbi.
(c) Reed Solomon code v convolution code c th kt hp vi nhau s dng
trong m knh.
2. m c th pht hin li v yu cu truyn li: thng dng trong cc h thng
khng phi thi gian thc, nh trong internet, fax,
2.2.2
Thit k b m ha v gii m chp s dng thut ton

Viterbi
M Chp
Trong mt h thng thng tin v tuyn y khng th thiu phn m knh, trong
loi m c s dng ph bin nht l m chp v gii m Viterbi. Vic s dng
m chp v gii m Viterbi c tng ng k t l SNR nhng b li cng lm tng

thm s bit khng mang thng tin.
S dng a thc sinh vi convolution encoder v Viterbi decoder c thc hin
trong matlab command bng lnh:
poly2trellis(ConstraintLength,GeneratorPolynomials)
Trong ConstraintLength l mt vector m chiu di ca n l s symbol u

vo trong encoder digram. Mi phn t ca n th hin s lng bit ca thanh ghi
dch. GeneratorPolynomials l ma trn [n by k].
n
k
l t l m ca convolution code.
N l s symbol ra. K l s symbol vo. Gi tr ca n v k c tnh nh hnh 2.2.
Hnh 2.2: S khi Transmitter

Theo hnh ta c s lng thanh ghi dch l 5 (tnh l trng hp tr 0 7 4 ) do
ConstraintLength = 5. GeneratorPolynomials: trn First Output ta c [1 1 1 1 1]
= 3710 (tr 0 l MSB). Trn Second Output c [1 1 0 1 1] = 3310
poly2trellis(5,[37 33]);
10
Gii m Viterbi
gii m chp ta s dng gii m Viterbi thc hin 1 trong hai trng hp:
Quyt nh cng (Hard Decision): code sau minh ha cho vic m ha v gii
m chp s dng Viterbi hard decision.
t = poly2trellis([4 3],[4 5 17;7 4 2]); % Define trellis.
tb = 2; % Traceback length for decoding
% Create a ConvolutionalEncoder System object
hConvEnc = comm.ConvolutionalEncoder(t);
% Create a ViterbiDecoder System object
hVitDec = comm.ViterbiDecoder(t, InputFormat, hard, ...
TracebackDepth, tb, TerminationMethod, Truncated);
code = step(hConvEnc, ones(100,1)); % Encode a string of ones.
decoded = step(hVitDec, code); % Decode.
Quyt nh mm (soft decision): l vic s dng nsdec bit cho vic quyt nh
mm. Khi gi tr u vo s c a v cc s nguyn nm gia 0 7
2nsdec 1. u vo l 0 s l quyt nh chc chn 0, u vo l 2nsdec 1 s
quyt nh chc chn 1, cc s cn li ng mi mc tin tng gim dn.
2.2.3
Format into Symbols (QAM mapping)
Bin i dng bit u vo thnh dng cc k hiu(symbol), u ra gm 2 dng I

(Inphase) v Q (Quandrature). i vi h thng 16-QAM, mi k hiu tng ng vi
4bit u vo, vi cc dng I v Q nhn cc gi tr +1, -1, +3, -3. Cc bit c m
ha thnh k thiu theo th chm sao:
Khi cc chm sao ny c pht i qua knh truyn s xy ra hin tng li tn
hiu, v vy chm sao thu c s khng cn chnh xc l 16 im nh trn hnh
2.3. v vy ta cn phi c b quyt nh da vo ngng ca cc im thu c. vic
quyt nh ngng ny s n n vic quyt nh sai khi c nhiu ln.
11
N = 100; %number of bit for simulation

x = randn(N,1)>0; % Random data
t = poly2trellis(7,[171 133]); % Define trellis.
% Create a ConvolutionalEncoder System object
hConvEnc = comm.ConvolutionalEncoder(t);
% Create a ViterbiDecoder System object
hVitDec = comm.ViterbiDecoder(t, InputFormat, Soft, ...
SoftInputWordLength, 3, TracebackDepth, 2, ...
TerminationMethod, Continuous);
code = step(hConvEnc,x); % Encode the data.
% Quantize to prepare for soft-decision decoding.
%compare and quantization input to 07 2nsdec 1
qcode = quantiz(code,[0.001,.1,.3,.5,.7,.9,.999]);
decoded = step(hVitDec,qcode); % Decode.
m bo vic quyt nh sai ny t nh hng ti t l SNR ca h thng ngi

ta m ha cc im trn chm sao theo phng php GRAY cc im sao gn nhau
s ch khc nhau 1 bit. Khi nu quyt nh sai im sao cng s ch gy ra li 1
bit. Trong cc trng hp khc s gy ra li >1bit.
Trong Matlab ta s dng lnh y = qammod(x,M) v lnh z = qamdemod(y,M)
m ha v gii m c s dng Gray. Hoc c th thc hin khng dng lnh c
sn vi tng chm sao nh sau:
0011 = 00 7 0(xor(0, 0)) = 00, 11 7 1(xor(1, 1)) = 10
0110 = 01 7 0(xor(0, 1)) = 01, 10 7 1(xor(1, 0)) = 11
Code hon chnh thc hin trn matlab nh hnh 2.5 t chuyn i sang code
c th xy dng trn s Simulink nh hnh 2.6
Kt qu thc hin ta c hnh di. sau khi tn hiu qua hai ln b lc raised
cosine filter(pht v thu) ta c tn hiu ng mu xanh pha trn. Sau thc
hin ly mu ti cui mi chu k ca tn hiu ny ta c c ng mu en l bit
12
Hnh 2.3: Th Chm Sao 16-QAM

b = log2(16) s bit trn 1 symbol khi s dng m ha 16-QAM.
Tb l thi gian 1 bit u vo ca khi modulation 16-QAM.
Ts = b*Tb thi gian ca 1 symbol u ra khi modulation.
Nb l s sample trn 1 bit.
Ns = b*Nb l s sample trn 1 symbol.
T = Ts/Ns l sample time.
Fs = 1/T l tn s ly mu.
thu c khi thu. Hnh di l bit truyn i khi pht, sau khi c lm tr
Nsym-1 mu. Ta nht thy kt qu thu c chnh xc. hnh ??
2.2.4
Zero Padding (Upsampling)
Thc hin chn thm 0 (zero padding) c tc ly mu ph hp. Thc hin trn
phn cng ngi ta chn h s upsampling bng 4 hoc 8. Gi s tc iu ch l
B, tn s FDAC = 4B add thm 3 phn t 0 tc u ra sau b DAC l B. Ngoi
ra vic add thm 0 vo cng m bo b lc sa dng hot ng ng. FDAC = 8B
13
Hnh 2.4: Th Chm Sao 16-QAM khi c nhiu

sqrtRcosTxFlt = comm.RaisedCosineTransmitFilter(...
Shape, Square root, ...
RolloffFactor, beta, ...
FilterSpanInSymbols, Nsym, ...
OutputSamplesPerSymbol, sampsPerSym);
add thm 7 phn t 0 tc u ra sau DAC l 2B. Trong bi ny ta chn add thm
3 phn t 0, u ra B = 5Mhz.
Trong Matlab vic ny thc hin: y = zeros(1,length(x)*4); y(1:4:end) = x;
2.2.5
Raise Cosine Filtering (FIR filter)
Thng tin trc khi truyn i c a qua b Raised Cosine Filter nhm mc ch
gii hn di thng truyn, trnh nhiu ISI. Kt hp vi b raised cosine filter bn
pha thu to ra match filter tng BER ca tn hiu thu c. Raised Cosine Filter l
mt loi ca Nyquite filter. Lun lun phn chia b lc ny thnh hai phn s dng
trn pha pht v pha thu. Root Nyquite Filter c s dng trong mi phn. t
14
Hnh 2.5: code thc hin trn Matlab

hp 2 phn ta thu c y Nyquite Filter. B lc ny gim nh hng ca nhiu
bng rng. gii hn di thng truyn trnh gy dnh hng ti cc hn thng khc,
v cng trnh nh hng t cc h thng khc. Thng s chnh ca 1 b lc raised
cosine l roll-off factor . ( = 0 trong trng hp l tng, = 1 l trng hp xu
nht. thng thng c chn 0.2-0.35). hnh 2.9
Thit lp b lc square-root raised cosine
(http : //www.mathworks.com/help/comm/examples/raisedcosinef iltering.html)
cc thng s cn thit xy dng b lc:
15
Hnh 2.6: code chuyn i sang Simulink

Roll off Factor thng c chn trong khong 0.2 7 0.5.
Filter Span In Symbols Nsym: s cc k hiu c mt cng lc trong b lc. l
mt s chn 6,8,10. . . thng mc nh l 10.
Oput Samples Per Symbol samspersym: tng ng vi h s upsample.
to ra b lc square-root raised cosine s dng 1 trong 2 cch.
S dng cng c filterbuilder hoc fdatool.
S dng lnh comm.RaisedCosineT ransmitF ilter trong command matlab.
16
Hnh 2.7:
2.2.6
Digital Sin/Cos Oscilator (NCO)
To dao ng dng sin hoc cos di dng cc mu ri rc.
2.2.7
Digital Analog Convert(ADC)
Thc hin chuyn i t tng t sang s. Vic ny cn thit trong cc h thng thc
t v ch c tn hiu tng t mi c th truyn i, nhng trong m phng phn ny
c b i v thc hin ghp sng mang trc tip.
Cc khi cn li trong s khi Transmitter hnh 2.4 ch thc hin trn thc t,
cn trong m phng c b i.
17
Hnh 2.8: Dng ca chui k hiu sau khi thc hin Upsampling
2.3
Receiver 16-QAM
S khi tng qut ca my thu Receiver 16-QAM. Trong m phng s dng

Matched Filter ch xt n khi Base band.
2.3.1
Timing phase recovery
: xc nh thi im tt nht ly mu tn hiu thu c. v d i vi iu ch

PSK ti nh ca dng xung. Vic ny ci thin cht lng BER, gim nh hng
ca nhiu. c rt nhiu phng php timing phase recovery, mi phng php c th
ph hp cho mt hoc nhiu h thng khc nhau. Khi Timing phase recovery c
t sau b lc thu(match filter) v trc khi gii m. Cc phng php sau c th
c s dng cho Timing phase recovery
Squaring Timing Recovery Block
Assumptions Common to All Feedback Method Blocks
18
Hnh 2.9: p ng tn s ca Raise Code Filter khi thay i

Early-Late Gate Timing Recovery Block
Gardner Timing Recovery Block
MSK-Type Signal Timing Recovery Block
Mueller-Muller Timing Recovery Block
Phng php Early-Late Gate Timing Recovery c bit ph hp vi h thng MQAM c s dng raised cosine filter. K thut ny i hi ly 3 samples trn 1 symbol.
hnh 2.12 Nu ly mu ti im ti u, ln trung bnh cng ca late v early
s bng vi late v early. Ngoi ra thi gian ly mu trung bnh, c feed back
loop.
e[k] = eI [k] + eQ [k]
eI [k] = yI [kT + dk ] (yI [kT +
T
T
+ dk ] yI [kT + dk1 ])
2
2
eI [k] = yQ [kT + dk ] (yQ [kT +
T
T
+ dk ] yQ [kT + dk1 ])
2
2
Code of Early-Late algorithm on Matlab
19
f2= fRF
KDTT
~
LNA
LO2
DAC
X
Amp
BB
f1= fIF
~
LO1
Hnh 2.10: S khi Receiver
2.3.2
Carrier Recovery
Khi Carrier Recovery (phc hi sng mang) c nhim v to ra dao ng ni ng

b vi sng mang pha pht c v tn s v pha. Nu tn s v pha ca b to dao
ng pha thu khng ng b vi pha pht s dn n hin tng quay chm sao k
hiu v dn ti phc hi sai thng tin.
Nguyn l lm vic da trn b vng kha pha s (D-PLL), trong ATAN l
khi tnh ton sai lch pha gia sng mang v b to dao ng ni, t thng
qua Loop Filter v NCO b to dao ng ni iu chnh tn s v pha ng b
vi sng mang ti sau khi ADC ca my thu.
20
Hnh 2.11: S khi Base Band Receiver

D-PLL c chia lm 3 phn chnh: Phase Detector, Loop Filter v NCO.
1. Phase Detector: Tnh ton sai pha gia tn hiu nhn c v tn hiu c
lng. Nu sng mang ti c pha l 0 v b to dao ng ni c pha l th
nhim v ca phase Detector l to ra tn hiu bng hoc t l vi sai pha:
= 0
c nhiu cch tnh ton , trong phng php ph bin v n gin nht
l dng hm Actan:
= atan(I) atan(Iest )
2. Loop Filter: Lc tn hiu sai pha to ra tn hiu in e dng hiu
21
Hnh 2.12: Phng php ly mu Early-Later

dTN = Ns/2 %Ns is number of sample in symbol
tsN = 2Ns; %index symbol initial
delta=0.01;
drif=abs(ys(tsN-dTN))-abs(ys(tsN+dTN));
if dif>delta, tsN=tsN-1; elseif dif<-delta, tsN=tsN+1; end
chnh b NCO.
Hm truyn t ca Loop Filter l:
L(z) = K.
(z 1) + K1
(z 1)
3. NCO: cn gi l b tn hp tn s Digital Synthesizer: S dng tn hiu iu

chnh e cp nht l pha ca b to dao ng ni.
Hm truyn t ca NCO l:
H(z) =
1
Z 1
22
Hnh 2.13: Hin Tng quay k hiu khi lch pha ca sng mang v b to dao
ng
Hot ng ca b D-PLL trong min Z:
Tn hiu sai pha trong min thi gian v trong min tn s:
e(k) = (k) (k)
E(z) = (z) (z)
trong (k) l pha sng ti, (k) l pha ca b to dao ng (cng chnh l u
ra ca NCO). Ta c phng trnh
(z 1).(z) = L(z).E(z) = L(z).[(z) (z)]
Suy ra hm truyn t ca c h thng D-PLL l:
H(z) =
L(z)
L(z) + z 1
Hnh 2.14: S khi Loop Filter(D-PLL bc 2)
Hnh 2.15: S khi b to dao ng NCO

Trong Matlab PLL c thc hin bng lnh
phierr (i) = atan2(I, Q) atan2(Iest , Qest );
e(i) = e(i 1) + K.phierr (i) K.phierr (i 1) + K1 .K.phierr (i);
phiHat(i) = phiHat(i 1) e(i);
23
2.3.3
24
Searching start symbol
Truyn thng tin t do thng gp phi cc hin tng mt d liu, khng thu c
u gi. Khi s khng th gii m d liu thu c v vy cn phi xc nh
c u gi k tip ca thng tin Vic tm u gi c xc nh bng cch nhn
preamble vi cc on ca d liu thu c.
%select point start packed
ii = 0;
ok = 0;
preambI = [3 -3 3 3 -3 -3 3 -3 3 3];
preambQ = [3 -3 3 3 -3 -3 3 -3 3 -3];
while(ok = 1&&ii<length(rI)-11)
ii=ii+1;
cI = abs(rI(ii:ii+9)*preambI);
cQ = abs(rQ(ii:ii+9)*preambQ);
if(cQ==90 || cI == 90)
ok = 1;
break
end
end
ii
rII = rI(ii:end);
rQQ = rQ(ii:end);
2.3.4
Rotation
Sau khi Timing recovery v khi Carrier Phase recovery tn hiu c a v ng

v tr chm sao. V khi Carrier Phase recovery ch c th khi phc c phase vi
gc lch < nn khi b dch bi mt gc bt k chm sao thu c ny c th

2
b dch i 1 gc k vi k = 0, 1 , 2, 3. Khi cn phi sa dng symbol Arlam

2
a chm sao v v tr ng ca n trc khi c th gii m tn hiu. Vic xoay
chm sao v v tr chnh xc c th xc nh c bng cch xc nh gc lnh m
25
symbol Arlam dch bng cch nhn vi exp(k ).

2
for k = 1:length(rII)
if(rII(1+9)>=0 & rQQ(1+9) <= 0)
rIr(k) = real((rII(k)+1i*rQQ(k))*exp(1i*1*pi/2));
rQr(k) = imag((rII(k)+1i*rQQ(k))*exp(1i*1*pi/2));
elseif(rII(1+9)>=0&rQQ(1+9) >= 0)
rIr(k) = real((rII(k)+1i*rQQ(k))*exp(-1i*0*pi/2));
rQr(k) = imag((rII(k)+1i*rQQ(k))*exp(-1i*0*pi/2));
elseif(rII(1+9)<=0&rQQ(1+9) >=0)
rIr(k) = real((rII(k)+1i*rQQ(k))*exp(-1i*1*pi/2));
rQr(k) = imag((rII(k)+1i*rQQ(k))*exp(-1i*1*pi/2));
elseif(rII(1+9)<= 0 &rQQ(1+9) <= 0)
rIr(k) = real((rII(k)+1i*rQQ(k))*exp(1i*2*pi/2));
rQr(k) = imag((rII(k)+1i*rQQ(k))*exp(1i*2*pi/2));
end
end
2.4
2.4.1
So Snh Kt Qu
Th Mt
Ly mu tn hiu trong cc chu k lin tip thu c(pha thu) v v ln cng 1

th, m ca th mt cho bit cht lng tn hiu thu c.
f ori = 1 : 16 : length(y_Ire)
plot(yI re(i : 15 + i));
holdon
grid; title(0 EyeDiagram0 );
end
26
Hnh 2.16: Eye Diagram
2.4.2
M Phng Monte-Carlo
L vic thc hin m phng lp li nhiu ln vi 1 mu data c nh, m bo xc

sut li tin gn n li thc t, hn ch li ngu nhin. Trong Matlab thc hin m
phng Monte-carlo bng 2 vng lp for lng nhau:
SN R_ranger = 10 : 5 : 50;
f orSN R = SN R_ranger
f ork = 1 : 1000
x = zeros(1, N _symbol);
...
BER_16QAM (k) = Ber_langth/N _symbol;
end
27
BER_ranger = [BER_rangersum(BER_16QAM )/1000]

end
trong k = 1000 l s ln lp li cho 1 mu data, thay i nhiu knh truyn tha
mn SNR trong khong -10:5:50. BER_ranger s c tnh cho mi ln thay i
SNR. S dng hm c sn semilogy() v ng BER.
Hnh 2.17: kt qu m phng tn hiu trn nhiu h thng 16-QAM
2.4.3
La chn thng s cho Raise Cosine Filter
Filter Span In Symbols Nsym: s cc k hiu c mt cng lc trong b lc. l mt s

chn 6,8,10. Nsym cng tng cht lng lc tn hiu cng tt, nhng i li p ng
xung s tng length (h) = Nsym*Ns Ns s symbol trong mt samble Xy dng code
matlab s dng convolution code c Nsym thay i trong khong 2, 6, 10 chn la
thng s ph hp cho ng dng. ta nhn thy khi Nsym thay i 2, 10 th chiu di
28
p ng xung ca b lc raise cosin tng ln 5 ln. nhng i li BER tng khng

ng k. hnh 2.18
Hnh 2.18: kt qu nh gi SNR ph thuc vo Ns ym
2.4.4
M Gray
Thc hin m ha Gray cho chm sao l vic m ha cc im trn chm sao sao cho
cc im gn nhau nht ch khc nhau 1 bit (00-01-11-10), iu ny m bo nu
bn pha thu gii m nhm ch dn n sai 1 bit tn hiu cho mi im sao.
Ngoi vic m ha Gray ta c th s dng M knh (vng, Viterbi...) tng

thm tin cy cho h thng.
29
Thc hin trong Matlab nh sau:
x1 = rand(1, N _symbol) > 0.5;

x = zeros(1, N _symbol);
x(1 : 2 : end) = x1(1 : 2 : end);
x(2 : 2 : end) = xor(x1(1 : 2 : end), x1(2 : 2 : end));
M phng chng minh vic s dng Gray cho ng BER tt hn so vi trng
hp khng s dng m Gray.
Hnh 2.19: BER s dng m Gray v khng s dng Gray
2.4.5
ng B
Trn thc t b to dao ng ca My Thu v My Pht lun c s khc nhau c

v tn s v pha,hn na vic truyn tn hiu trong thi gian thc s lm dch pha
tn thiu ti my thu. Dn n vic gii m 1 cch thng thng s khng th thc
hin c. m bo gii m ng ta phi s dng vng kha pha s Digital-Phase
30
Lock Loop (D-PLL) ng b tn s v ng b pha ca My thu ng vi tn s

v pha ca my thu.
Preamble l phn d liu bit trc cho c my pht v my thu, Preamble c
chn vo u mi gi d liu bn pha pht. vic bit trc Preamble s m bo
vic gii m v tm im bt u khung d liu mt cch chnh xc.
preamble = [3 3 3 + 3 3 + 3 3 + 3 3 + 3]; Cc bc thc hin ng b trong
Hnh 2.20: ng gi data trong 16-QAM

trong vng kha pha ca my thu 16-QAM:
1. ly mu tn hiu downsample()
2. chuyn qua vng kha pha, xoay tn hiu thu c 1 gc = 0 (gc khi to).
3. a v im gn nht trong chm sao bng cch so snh vi ngng.
4. tnh gc b dch i atan(I, Q) atan(I_est, Q_ets).
5. ti to gc (i) theo cng thc hm p ng xung ca Loop Filter v DDS
6. da vo Preamble xoay v chm sao ng.
Hnh 2.21: Tn hiu Thu b xoay
31
Hnh 2.22: Tn hiu Thu khi s dng khi synchronization
32
Chng 3
THIT K
Sau khi la chn c kin trc thit k cho h thng, chng ny s chng ta s
hc cch thit k h thng phn cng sao cho hiu qu, ph hp vi mong mun, tit
kim thi gian thit k, tnh chnh xc cao. Chng ta s thng qua cc bc lm sau
y:
1. Trin khai s Simulink
2. Xy dng mt bn specification design
3. M t thut ton dng trin khai cc khi trong Spec. di dng lu
thut ton
4. Xy dng m FSM, ASMD, FSMD cho nhng b phc tp
3.1
Tng Quan V Simulink
Simulink l mt b cng c trong Matlab dng m hnh, m phng v phn tch

cc h thng ng vi mi trng giao din s dng bng ha. Vic xy dng m
hnh c ng gin ha bng cc hot ng nhp chut v ko th. Simulink bao
33
CHNG 3. THIT K
34
gm mt b th vin khi vi cc hp cng c ton din cho c vic phn tch tuyn
tinhsv phi tuyn. Simulink l mt phn quan trong ca Matlab c th d dng
chuyn i qua li trong qu trnh phn tch, v v vy ngi dng c th tn dng
c u th ca c 2 mi trng.
xy dng c 1 h thng trn Simulink ta cn quyt nh kin trc s thc
hin. Tn hiu u vo u ra, thi gian thc hin...
Vic xy dng m phng trn Simulink s m bo m phng chy c trn thi
gian thc, gn hn vi cc h thng thc. Cc h thng thc c phn chia thnh
cc module thc hin mt chc nng nht nh no , cc module c kt hp bi
cc khi c bn trong th vin ca Simulink. Vic ny lm n gin hn vic thit
k h thng trn HDL, VHDL...
3.2
M Phng H Thng 16-QAM trn Simulink
Thay i SNR trong khong -10:5:30 thc hin chy m phng 30s (n v thi gian
trong m phng), kt qu ng BER thu c tng t nh trong m phng thut
ton trn code Matlab.
Cc khi trong simulink c t tn gn ging vi chc nng ca n, v vy khi
mun s dng 1 khi no ta c th search tn tng ng trong Search hoc trong
help. Ngoi ra cn c help bit tt c cc chc nng c th, kt qu u ra, kiu
d liu u ra v u vo ca khi , trc khi tnh ti vic kt hp khi vi cc
khi c bn khc.
Trong vic m phng cc h thng Vin thng, in t ta lu n cc th
vin Simulink cha cc khi chc nng c bn, Comunications System Toolbox, DSP
System Toolbox. Mt s khi khc ca Xilinx s c cp phn sau.
Vic xy dng 1 m hnh m phng hon chnh trn Simulink ngoi yu cu chy
m phng trn Matlab code, hiu r chc nng, tnh cht tng Module. Cn rt cn
CHNG 3. THIT K
35
c thi gian tm hiu cc khi c bn, v kt ni cc khi c bn to thnh cc

Module c chc nng nht nh t to iu kin xy dng cc Module ln trong
cc h thng thc t.
Hnh 3.1: S khi 16-QAM trn Simulink
Sound bit: to ra chui bit 0, 1

Transmitter: m ha v ghp sng mang cho chui bit u vo, u ra s l tn
hiu s tn s IF. Trn h thng tht s c ni vi ADC v a ln RF
trc khi pht i.
Channel: s dng knh nhiu trng hoc nhiu Rayleigh
Receiver: nhn tn hiu s IF, ct b sng mang v gii m. u ra l chui bit.
Calculating bit error and Display: u vo l bit pht c lm tr, bit sau
gi m. u ra c hin th scope(dng sng theo thi gian) v Display(dng
s). Chc nng tnh s bit li, t l li.
CHNG 3. THIT K
3.2.1
36
Transmitter
Khi Convolutional Encoder nm trong th vin Comunication System Toolbox

- Error Detection and Correction-convolution. C th tm bng cch search tn
ca khi trong tm kim. Khi ny thng i km vi khi gii m Viterbi
Decoder ( s dng bn khi Receiver). Thng s hot ng c chn nh
trong phn code matlab a ra. Sau khi ny tc bit tng ln gp i,
v vi mi bit vo s c 2 bit ra tng ng.
Raised Cosine Transmit Filter i km vi Raised Cosine Receiver Filter nm
trong th vin Comunication System Toolbox-Comm Filters. Thng s hot
ng chn ging nh code matlab.
LO: b giao ng hnh sin trong th vin Simulink-Sources-sin wave. Hai b to
dao ng lnh pha Ch : v khi to dao ng c tc bng vi tc ca
sample, v nm trong khi pht nn phi chn Sample time cho n. Cc khi
khc nm pha sau s khng phi chn Sample time na. Cc thng s khc
chn nh trong code matlab nh Amplitude, Bias, Frequency, phase, Sample
time.
Khi Multiplex, add, gain trong th vin Simulink/Math Operations. Khi Gain
c dng y kiu sot nng lng pht i ca khi pht.
Khi P reamble_M odulation: u vo dng bit sau m knh, u ra cc symbol
c ng gi (ghp thm preamble bo hiu u gi). c ghp t cc
khi nh, thc hin chc nng tnh m gray, m ha 16_QAM , v chn pilot
and Arlam. hnh 3.2
Graycode: u vo bit sau m knh, u ra dng bit sau m gray, tc khng

thay i. hai bit sau khi m knh c tch lm 2 ng (select_row, thng
CHNG 3. THIT K
37
Hnh 3.2: S khi 16-QAM trn Simulink

s chnh trong khi: ch r la chn Rows or columns, v tr ca cc phn t
ly ra trong Rows or Columns). 3.3 Khi buffer lu li 2 bit lin tip . Khi
Xor tnh gray theo cng thc (Bit1 = bit1, Bit2 = bit1 Xor bit2). Unbuffer c
tun t cc bit trong b m ra ngoi.
Khi M od_16QAM : u vo dng bit sau khi graycode, u ra symbol I v
Q. Khi buffer gi 4 bit [a1 a2 a3 a4] v thc hin modulation 16QAM, I_sym
= 2*(a1*2+a2)-3 , Q_sym = 2*(a3*2+a4)-3. hinh 3.4
khi insert_pilot u vo symbol v Q, u ra dng symbol I v Q c
ng gi, 40 symbolI_sym ghp vi 10symbol preamb_I. nn tc u ra
fout = 5/4 fin . hinh 3.5
khi AWGN channel: trong th vin Communications System Toolbox-Channels.
Ngoi ra cn c cc khi to knh Fading, Multipath Rayleigh. . . thng s s
dng ging nh trong code matlab.
CHNG 3. THIT K
38
Hnh 3.3: S khi Graycode
Hnh 3.4: S khi M ode_16QAM
3.2.2
Receiver
u vo tn hiu s tn s IF = 40MHz, u ra dng bit c gii m. Bao

gm nhiu khi nh, thc hin chc nng h tn, Timming recovery, phase recovery, tracking begin packed, remove preamble, demodulation 16_QAM , gray decode,
Viterbi Deocder. hinh 3.6 ch ra khi thu trn simulink.
CLK trong th vin Simulink-Sources-Counter Free Running: Sample time bng
vi tc sample, Number of bits chn 1 s ln hn s symbol thc hin m
phng.
CHNG 3. THIT K
39
Hnh 3.5: S khi insert_pilot

V ector_receive: 3.7 u vo tn hiu s tn s IF, u ra l vector chiu di
LB(chn ging code matlab). Chc nng thc hin ca khi: khi c u vo
IF _rec cc phn t s c dch 1 n v, IF _rec s c t vo cui ca
mng.
M t chc nng: ti thi im sel = 0. B mux s chn Vector u ra r1 =
zeros(Lb,1). Ti thi im sel != 0 u ra ti thi im t-1 s c a tr li
u vo. u ra sau b MUX s ly cc phn t 27 LB, v ghp vi rec_IF
v tr LB. Khi LO_rec to ra sin v cos c tn s IF, phase = 0, wct= wc*(n1)*T; trong n 1 l phn d ca php chia clk cho Ns, T l symbol time
ca clk, wc l hng s. khi cosin trong th vin Simulink-Locup Tables-Cosin
s tnh cos, sin t phase u vo. hnh ??.
CHNG 3. THIT K
40
Count_sample: m s symbol nhn, thc cht l php chia ly phn nguyn

ca clk cho Ns.
Timming Recovery: u vo tn hiu sau h tn, u ra symbol ly mu.
Khi yr1 v yr2 to ra cc mng kch thc LB lu u vo sau khi nhn sin v
for n=1:Ns % Operation per symbol time
%timing recovery
yrb = [yrb(:,2:end) yr(:,LB)];
bf = filter(bh,1,yr(:,end-Ng+1:end));
yrg = [yrg(:,2:end) bf(:,Ng)];
end
%timing recover searching position
ycsk=yrg(:,Nts); % Correlator output at (k-1)Ts
ycsk1=yrg(:,Nts+Ndt); % Correlator output at (k-1/2)Ts
dif=ycsk*(ycsk1-ycsk0).; %error
if dif>delta, Nts = Nts+1; elseif dif<-delta, Nts=Nts-1; end
ycsk0 = ycsk1;
NNt = [NNt Nts];
yrec=yrg(:,Nts)*Ts;
cos, tip theo a mng qua b lc Square Root, u ra l mng Ng phn t,

nhng ch a ra phn t th Ng bng khi select Rows . RaisecosinFilter
m bo thc hin lc tn hiu ng v thc hin thi gian thc, mng yr1_vec
s c ct Ng (bng vi chiu di p ng xung ca RaiseCosineFilter) a
qua b lc, kt qu ra ch ly phn t cui cng. iu quan trong cn ch
cch chuyn i t thc hin trn matlab thnh thc hin thi gian thc ca
Simulink 3.9.
Phn t cui cng trong mng kt qu ca square root c xp li thnh
mng LB phn t bng khi cal_yrg1, cal_yrg2 sau ly mu bng khi
downsample. Vic tnh ton cc khi s dng vector LB phn t m bo
Timming recovery s dng LB phn t lin tip tnh ton. Khi cal_N ts:
CHNG 3. THIT K
41
u vo N ts_0 c chn bng 3Ns, dif th hin s sai khc c tnh theo
cng thc dif=ycsk*(ycsk1-ycsk0).; sel = count_symbol. u ra l v tr cho
gi tr ly mu cao nht. M t thc hin:N ts_M l b MUX chn la gia
ycsk=yrg(:,Nts); % Correlator output at (k-1)Ts
ycsk1=yrg(:,Nts+Ndt); % Correlator output at (k-1/2)Ts
dif=ycsk*(ycsk1-ycsk0).; %error
if dif>delta, Nts = Nts+1; elseif dif<-delta, Nts=Nts-1; end
ycsk0 = ycsk1;
gi trN ts_0 vi sel=0, N ts_out vi sel != 0. u ra ca b MUX c a

tr li (s dng khi delay 1 a tr li , ging vi vic s dng gi tr u
ra khi MUX ti thi im t-1), dif c tnh ton v a vo khi Subsystem
thc hin chc nng trng ng vi dng code 3.10
Khi cal_yck v cal_yck1 u vo l vector yrg1, yrg2 v Nts u ra ca khi

cal_N ts. Khi ny ch c chc nng a ra phn t th Nts ca yrg1 v yrg2.
hinh 3.11
Khi Phase Recovery: u ra ca khi Timming recovery c nhn vi Ts

khi phc thnh cc symbol. Sau c a qua khi Phase Recovery khi
phc v tr ng ca cc symbol , bng cch dch chng 1 gc phase nht
nh trong khong [07 ] v cc im trn constellation gn nht. 3.12.

2
M t hot ng: u vo s c nhn vi mt gc phi_Hat = 0, sau
so snh xem gn vi im no trn chm sao nht bng function cons_star.
P hi_Err l gc lch gia im trn chm sao gn nht vi im thu c, kt
qu ny c dng tnh e v tnh phi_Hat ti thi im t.
Hnh 3.13 trn show kt qu ca phi_Err, e v P hi_Hat. Do tnh ton ng
nn phi_Hat sau 1 thi gian s bm c ng v tr phase b dch. D
CHNG 3. THIT K
42
liu c gain vi 1/A a v ng chm sao pht i trc khi kim sot nng
lng pht.
Khi Search_beginning: Code Matlab thc hin tng ng: Kh khn gp

ii = 0;
ok = 0;
preambI = [3 -3 3 3 -3 -3 3 -3 3 3];
preambQ = [3 -3 3 3 -3 -3 3 -3 3 -3];
while(ok = 1&&ii<length(rI)-11)
ii=ii+1;
cI = abs(rI(ii:ii+9)*preambI);
cQ = abs(rQ(ii:ii+9)*preambQ);
if(cQ==90 || cI == 90)
ok = 1;
break
end
end
phi y l trong Simulink khng th thc hin Break, v cng khng th

lu li tt c rI v rQ thc hin trong 1 lt, vic xp rI v rQ nhn vi
Preamble s tr ln phc tp. Ngoi ra trn Simulink s thc hin lin tc thay
v thc hin while-end nh trong matlab.
vic thu thng tin v tuyt khng phi lc no cng bt c u gi c th
x l thng tin mt cch chnh xc, v vy ngi ta thng ghp thm phn preamble
vo mi gi bo hiu cho vic bt u 1 gi. Ta c th s dng c im ny
tm ra u mi gi tin. Yu cu chc nng: t 2 u vo l cc symbol I v Q v
preamble I v preamble Q bit ta xc nh khi no cho s xut hin ca u gi.
lm c iu ny rI v rQ s c a vo 1 Quere c kch thc 10 phn t,
c mi 1 phn t c a vo li em Quere ny nhn vi Preamble, kt qu
s ly tng tr tuyt i. nu c 2 kt qu tnh ton trn dng rI v rQ cng bng
CHNG 3. THIT K
43
nhau v cng bng 90 th s a ra xung bo hiu ln mc 1, cn li l mc 0. Hnh

di ch ra kt qu thc hin. bi v ch cn xc nh c ng u gi, s da vo
tnh ton lun m khng cn tnh ton cc u gi tip theo na, nn ta s tao ra
sn xung ln 1 t khi c u gi, v duy tr bng 1 cho n khi kt thc qu trnh
nhn tn hiu. thc hin n gin vi b MUX v 1 b tr 3.14 v kt qu 3.15
Rotation Constelation: V gc dch khi truyn tin l bt k, trong khi Phase
recovery ch c th xoay c cc gc [07 ] do vi cc gc ln hn ta

2
2
s phi xoay thm 1 ln na bng cch s dng gc dch ca u gi symbol
u gi.
M t chc nng: khi ny da vo gc hin ti ca u gi (Arlam) so vi gc
ca Arlam pht i, cc symbol thu c u c xoay 1 gc tng ng vi
lch ca 2 Arlam .
M t hot ng: MUX1 s chn gc ban u bng vi gc (3 -3i) ca Arlam
pht i, t thi im pht hin ra u gi (tng ng vi v tr Arlam thu) b
MUX1 s chuyn sang ly gc lch ca (I_in+1i*Q_in). gc thu c sau b
MUX 1 s c a qua MUX3 duy tr gc cho n ht qu trnh thu
tn hiu. lm c iu , MUX 3 s c u vo 0 l u ra ca MUX1, v
u vo 1 l u ra ti thi im t-1, sel ca MUX3 s l sel ca MUX1 ti thi
im t-1 m m bo MUX 3 lun hot ng sau khi MUX1 hot ng.
u ra ca MUX3 s c tr i gc ban u ca Arlam pht bit c tn
hiu b dch i 1 gc bao nhiu, v gc ny s c nhn vo tn hiu (I_in
+ 1i*Q_in) to ra (I_out+1i*Q_out) 3.16
Khi Position of packed: vi 1 chui symbol thu c tun t theo thi gian
yu cu ct b phn mt gi, v ch ra c v tr mi ca gi. V sau ch
ly cc gi tr mang thng tin, khng ly phn mt gi v phn preamble. Khi
ch c tn hiu sn bo khi c u gi v s th t ca symbol thu c.
CHNG 3. THIT K
44
Phn tch: ta cn c 2 khi buffer c kch thc bng 2 ln chiu di ca gi (c

thng tin v preamble) m bo khi ta bt c bt c v tr no ca chui
thng tin th trong buffer vn lun c 1 gi tin. Khi buffer th 2 s lu gi tr
chui tn sau khi a qua khi delay bng vi chiu di ca gi tin. iu ny
s m bo c rng trong 2 khi buffer 1 v buffer2 lun cha 2 gi tin lin
tip ca chui. khi khi position of packed ch cn ch ra c v tr thng
tin nm v tr t th bao nhiu n th bao nhiu ca 2 buffer(v tr ny l
ging nhau vi c 2 buffer v chng lch nhau bng bng chiu di gi) sau
s dng khi select Rows vi ch s la chn a t ngoi vo ta s thu c
khung thng tin cn thit. kt hp vi khi unbuffer ta s c chui thng tin
ln lt.hnh 3.17 S dng sn bo hiu c u gi to ra tn hiu v tr ca
symbol, khi no c sn ln 1 th v tr ca symbol s c gia nguyn. V tr
ca symbol chia ly phn d cho s lng phn t trong gi ta s tm c v
tr ca u gi trong buffer. Kt hp vi mng 40 phn t(17 40s phn t
mang thng tin trong 1 gi) ta s a ra c v tr ca cc phn t trong
gi tin.
Kt qu c cho nh hnh di tng ng sn xung bo hiu, v tr symbol,
v v tr ca u gi trong buffer. hnh 3.18
Remove Preamble: nhn u vo l ch s ca cc symbol mang thng tin, v
I_pre, Q_pre l cc symbol thu c, cn loi b preamble 3.19
Khi Demodulation_grayDecode gii m 16_QAM v gii m gray code, lm
ngc li so vi bn m. ??
Viterbidecoder: tc gim 1 na, u vo 2 bit, u ra 1 bit.
khi tnh ton s bit li, t l li so vi s bit truyn i bao gm c do cha
ng b v li truyn. hinh ??
CHNG 3. THIT K
45
Hnh 3.6: S khi receiver
CHNG 3. THIT K
46
Hnh 3.7: khi vector_receiver
Hnh 3.8: khi LO_rec
CHNG 3. THIT K
47
Hnh 3.9:
Hnh 3.10:
Hnh 3.11:
CHNG 3. THIT K
48
Hnh 3.12:
CHNG 3. THIT K
49
Hnh 3.13:
Hnh 3.14:
CHNG 3. THIT K
50
Hnh 3.15:
CHNG 3. THIT K
51
CHNG 3. THIT K
52
Hnh 3.17:
Hnh 3.18:
Hnh 3.19:
CHNG 3. THIT K
53
Hnh 3.20:
Hnh 3.21:
Chng 4
Specification Design
4.1
Xy dng specification design
Phn ny chng ta s phn nh h thng ra thnh nhiu khi nh (Block) sau nh

ngha u vo u ra, hm truyn t, constraint timing cho h thng. Constraint
timing l g? N n gin l mt chu k hot ng ca h thng. Chu k ny do chng
ta d kin da trn thut ton v kin trc la chn ban u. p ng cho
mt h thng chy ng yu cu th c rt nhiu thut ton, tuy nhin chng ta phi
la chn thut ton sao cho n cn i gia hiu nng v thi gian thc hin. Mt
thut ton c chnh xc cao nhng thi gian tnh ton cng nh ti nguyn phn
cng qu nhiu th khng phi l s la chn s 1, nhng cng ty theo ca
ngi thit k. Sau y chng ta s tham kho mt specification design cho h thng
QAM-16. Cc khi s c trnh by da theo s khi thu v pht (hnh 4.1 v
hnh 4.2) Ch : Khi carrier multiplier v khi raised cosin filter c s dng
nh nhau trong c khi pht v khi thu
54
CHNG 4. SPECIFICATION DESIGN
Zero pad
Cyclic
Prefix
Data_in
55
Raised
cosin filter
sin
x
Pilot
inserter
adder
Mapper
Zero pad
Raised
cosin filter
cos
x
LO
Hnh 4.1: S khi pht

sin
x
ng b
LPF
Match
filter
Ly mu
Phase
Lock
Loop
Ct pilot
cos
x
LPF
Match
filter
Ly mu
Xoay
chm sao
da vo
cyclic
prefix
Demapper
Data_out
LO
Hnh 4.2: S khi thu
4.1.1
Cyclic prefix
Tn hiu vo/ra
Tn hiu vo ra ca khi Cyclic prefix c biu din hnh 4.3 v bng 4.1
Hot ng
D liu vo sau 90 bit s c chn khong bo v 10 bit 1.
Cn 1 thanh ghi-xbit la chn gia 90 bit u vo v 10 bit bo v 1
Ban u gn tn hiu vo cho 1 dy dn A (wire), cng lc bt Start t 0
ln 1
khi c sn ln ca xung clk, u ra bng vi gi tr dy dn A
56
Cyclic Prefix
clk
data_out
rst_n
ready
data_in
start
Hnh 4.3: Khi cyclic prefix

Port
clk
rst_n
data_in
ce
Data Width
1bit
1bit
1bit
1bit
data_out 1bit
ready
1bit
Direction
Input
Input
Input
Input
Output
Output
Description
Clock(2.5Mhz)
reset mc thp
d liu vo
chip enable: cho php nhn
d liu
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.1: Tn hiu vo/ra ca khi cyclic prefix
Khi c d liu ra, tn hiu Ready s chuyn t 0 ln 1

Dng sng ca khi cyclic prefix
Dng sng ca khi cyclic prefix c biu din hnh 4.4
4.1.2
Mapper
Tn hiu vo/ra
Tn hiu vo ra ca khi Mapper c biu din hnh 4.5 v bng 4.2
57
Cycle Prifix
clk
rst
din
a1
a2
a1
dout
a90 b1
b1
a90
a2
b1
1
b1
b2
b1
start
ready
Hnh 4.4: Biu dng sng khi cyclic prefix

Hot ng
Khi start =1 gn d liu vo cho 1 dy dn x l trn dy dn
M ha theo bng 4.3
Dng sng ca khi mapper

Dng sng ca khi mapper c biu din hnh 4.7
4.1.3
Zero padder
Tn hiu vo/ra
Hot ng
Chn 15 s 0 vo gia cc phn t
58
Mapper
clk
rst_n
data_Q
data_in
data_I
start
ready
Hnh 4.5: Khi mapper

Port
clk
rst_n
start
data_in
data_I
Data Width
1bit
1bit
1bit
1bit
16bit
Direction
Input
Input
Input
Input
Output
data_Q
16bit
Output
ready
1bit
Output
Description
Clock(2.5Mhz)
reset mc thp
bo d liu vo
d liu vo
d liu phn thc (4bit thp
phn trong tng s 16bit)
d liu phn o (4bit thp
phn trong tng s 16bit)
bo c d liu ra ng b
cho khi sau
Bng 4.2: Tn hiu vo/ra ca khi mapper
Khi c tn hiu start, a d liu vo vo khi (dy A)

Sel la chn gia dy A v 16b0
Ti sn dng ca clk, gn tn hiu c chn cho u ra
Tn hiu sel l tn hiu iu khin c 1 bit.
b0b1 I
00
-3
01
-1
11
+1
10
+3
59
b2b3 Q
00
-3
01
-1
11
+1
00
+3
Bng 4.3: M ha ca khi mapper
Hnh 4.6: Chm sao iu ch khi mapper
4.1.4
Raised cosin filter
Tn hiu vo/ra
Tn hiu vo ra ca khi raised cosin filter c biu din hnh 4.11 v bng 4.5
Hot ng
Khi Ce_shift = 1: cho php thanh ghi dch hot ng
Tn hiu c dch vo v c nhn vi 1 bng gm 16 gi tr- l gi tr ca
cc p ng xung (hnh 4.12)
Hnh 4.13 l p ng xung 16 im s m ha
Bng 4.6 biu din gi tr ca p ng xung
60
Mapper (16-QAM)
clk
rst
start
din
16-QAM_in
0110
1011
s0
s1
dout _I
Real_0
Real_1
dout _Q
Imag_0
Imag_1
16-QAM_out
ready
Hnh 4.7: Biu dng sng khi mapper

Dng sng ca khi raised cosin filter
Dng sng ca khi raised cosin filter c biu din hnh 4.14
4.1.5
Carrier multiplier
Tn hiu vo/ra
Tn hiu vo ra ca khi Carrier multiplier c biu din hnh 4.15 v bng 4.7
61
Mapper
clk
rst_n
data_Q
data_in
data_I
start
ready
Hnh 4.8: Khi zero padder

Port
clk
rst_n
start
data_in
sel
Data Width
1bit
1bit
1bit
16bit
1bit
data_out 16bit
ready
1bit
Direction
Input
Input
Input
Input
Input
Output
Output
Description
Clock(10Mhz)
reset mc thp
bo d liu vo
d liu vo
Tn hiu chn gia u vo
v s 0-16bit
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.4: Tn hiu vo/ra ca khi zero padder
Hot ng
tn hiu selc arrier l mt tn hiu c m theo chu k ca xung ng h, c
gi tr t 0-15. N s iu khin tn hiu data_in ra cc u ra ln lt t 0-15
b MUX, sau tn hiu ny s c nhn vi mt hng s x (l cc gi tr
sin, cosin c ly mu sn) v sau a ra ngoi thng qua b DEMUX.
B FlipFlop c tc dng gi tn hiu ra mc n nh (hnh 4.16)
Hnh 4.18 v hnh 4.17 l sng sin v cos c ly mu thnh 16 im.
Sng mang l cosin hoc sin s c ct ra thnh 16 im vi gi tr nh trong
bng 4.8
62
Sel
Data_in
16'b0
SET
CLR
Data_out
clock
Hnh 4.9: M t khi zero padder

Port
clk
rst_n
start
data_in
ce_shift
Data Width
1bit
1bit
1bit
16bit
1bit
data_out 16bit
ready
1bit
Direction
Input
Input
Input
Input
Input
Output
Output
Description
Clock(10Mhz)
reset mc thp
bo d liu vo
d liu vo
Khi ce_shift = 1: Cho php
dch bit
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.5: Tn hiu vo/ra ca khi raised cosin filter
Dng sng ca khi carrier multiplier

Dng sng ca khi carrier multiplier c biu din hnh 4.19
4.1.6
Pilot inserter
Tn hiu vo/ra
Tn hiu vo ra ca khi pilot inserter c biu din hnh 4.20 v bng 4.9
63
Zero Padder
clk
rst
start
Data_in
Data_out
Din0
Din0 0
Din1
0
...
Din1 0
...
sel
ready
Hnh 4.10: Biu dng sng khi zero padder

Hot ng
Sau 25 im chm sao (mi mt chu k sng mang i din cho mt im) phi
chn thm 10 s 7 (mi s 7 c biu din bng 16 bit)
Mi sng mang c chia thnh 16 im nh cc b pha trn
chn 10 s 7 th t l clk c vo v c ra l: 400/410
Ch : phn d liu mu pl trong hnh 4.21 l phn d liu c chn vo
Dng sng ca khi pilot inserter
Dng sng ca khi pilot inserter c biu din hnh 4.21
64
Raised cosin filter
clk
rst_n
data_out
data_in
ready
start
ce_shift
Hnh 4.11: Khi raised cosin filter

Data_in
SET
CLR
SET
CLR
h0
SET
CLR
h1
SET
CLR
h2
SET
CLR
h3
SET
CLR
h4
SET
CLR
...
SET
CLR
h14
h15
Data_out
Hnh 4.12: M t khi raised cosin filter
4.1.7
Cut pilot
Tn hiu vo/ra
Tn hiu vo ra ca khi cut pilot c biu din hnh 4.22 v bng 4.10
Hot ng
Sau 410 mu d liu (tnh t lc c tn hiu start) phi ct i 10 s 7 (mi s
7 c biu din bng 16 bit)
Hnh 4.13: p ng xung khi raised cosin filter

clk c vo v c ra l: 410/400
Qu trnh ngc li so vi khi pilot inserter
Dng sng ca khi cut pilot
Dng sng ca khi cut pilot c biu din hnh 4.23
4.1.8
Sampling
Tn hiu vo/ra
Tn hiu vo ra ca khi sampling c biu din hnh 4.24 v bng 4.11
Hot ng
Ly mu tn hiu vo vi tc : C 16 mu th ly 1 mu
Dng sng ca khi sampling
Dng sng ca khi sampling c biu din hnh ??
65
##
h0
h1
h2
h3
h4
h5
h6
h7
h8
h9
h10
h11
h12
h13
h14
h15
66
gi tr
0.0000
-0.0951
-0.1672
-0.1317
0.0641
0.3928
0.7431
0.9690
0.9690
0.7431
0.3928
0.0641
-0.1317
-0.1672
-0.0951
0.0000
Bng 4.6: gi tr p ng xung ca khi raised cosin filter
Port
clk
rst_n
start
data_in
sel_carrier
data_out
ready
Data Width
1bit
1bit
1bit
16bit
4bit
16bit
1bit
Direction
Input
Input
Input
Input
Input
Output
Output
Description
Clock(10Mhz)
reset mc thp
bo d liu vo
d liu vo
la chn nhn hng s
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.7: Tn hiu vo/ra ca khi carrier multiplier
67
Raise cosin filter
clk
rst
start
Ce_shift
Data_in
...
Din0 0
...
Reg_shift_1
0 Din0 0
...
Reg_shift_2
0 Din0 0
...
Reg_shift_15
...
0 Din0
d0
d1
d2
d3
d4
...
d14 d15
Reg_shift_0
Data_out
Din0 0
Din1 0
...
Din1 0
...
0 Din1 0
...
0 Din1 0
...
...
0 Din1
ready
Hnh 4.14: Biu dng sng khi raised cosin filter
clk
Carrier multiplier
rst_n
data_in
start
data_out
ready
Sel_carrier
Hnh 4.15: Khi carrier multiplier
68
sel
x0
0
0
x1
1
x2
Data_in
2
D
SET
x3
3
15
x15
CLR
15
Hnh 4.16: M t khi carrier multiplier
Hnh 4.17: Sng mang sin ca khi carrier multiplier
Data_out
69
Hnh 4.18: Sng mang cos ca khi carrier multiplier
##
sin0
sin1
sin2
sin3
sin4
sin5
sin6
sin7
sin8
sin9
sin10
sin11
sin12
sin13
sin14
sin15
Gi tr
0.0000
0.3827
0.7071
0.9239
1.0000
0.9239
0.7071
0.3827
0.0000
-0.3827
-0.7071
-0.9239
-1.0000
-0.9239
-0.7071
-0.3827
##
cos0
cos1
cos2
cos3
cos4
cos5
cos6
cos7
cos8
cos9
cos10
cos11
cos12
cos13
cos14
cos15
Gi tr
1.0000
0.9239
0.7071
0.3827
0.0000
-0.3827
-0.7071
-0.9239
-1.0000
-0.9239
-0.7071
-0.3827
0.0000
0.3827
0.7071
0.9239
Bng 4.8: gi tr ca sng mang sin v cosin
70
Carrier Multiplier
clk
rst
start
sel
Data_in
Data_out
0
d0
d1
d2
d3
d4
d5
...
D0
D1
D2
D3
D4
D5
...
15
...
d1
d2
d3
d4
d5
...
d15
... D15 D0
D1
D2
D3
D4
D5
d15 d0
ready
Hnh 4.19: Biu dng sng khi carrier multiplier
Pilot Inserter
clk1
clk2
rst_n
data_out
ready
data_in
start
Hnh 4.20: Khi cyclic prefix
15
... D15
Port
clk1
clk2
rst_n
start
data_in
data_out
ready
Data Width
1bit
1bit
1bit
1bit
16bit
16bit
1bit
Direction
Input
Input
Input
Input
Input
Output
Output
71
Description
Clock(10Mhz)
Clock(10.25Mhz)
reset mc thp
bo d liu vo
d liu vo
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.9: Tn hiu vo/ra ca khi pilot inserter
Pilot inserter
Clk_in
Clk_out
rst
start
Data_in
D[0]0
Data_out
Count_out
D[0]1
D[0]15 D[1]0
pl
pl
pl
10
D[0]0 D[0]1
D[1]1
D[1]15
D[0]15 D[1]0 D[1]1
D[24]0 D[24]1
D[1]15
D[24]0 D[24]1
ready
Hnh 4.21: Biu dng sng khi pilot inserter
D[24]15
D[24]15
409 410
72
Cut Pilot
clk1
data_out
clk2
ready
rst_n
data_in
start
Hnh 4.22: Khi cut pilot
Port
clk1
clk2
rst_n
start
data_in
data_out
ready
Data Width
1bit
1bit
1bit
1bit
16bit
16bit
1bit
Direction
Input
Input
Input
Input
Input
Output
Output
Description
Clock(10.25Mhz)
Clock(10Mhz)
reset mc thp
bo d liu vo
d liu vo
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.10: Tn hiu vo/ra ca khi cut pilot
Port
clk
rst_n
start
data_in
data_out
ready
Data Width
1bit
1bit
1bit
16bit
16bit
1bit
Direction
Input
Input
Input
Input
Output
Output
Description
Clock(0.625Mhz)
reset mc thp
bo d liu vo
d liu vo
d liu ra
bo c d liu ra ng b
cho khi sau
Bng 4.11: Tn hiu vo/ra ca khi sampling
73
Cut pilot
Clk_out
Clk_in
rst
start
Data_in
D[0]0 D[0]1
Data_out
Count_out
D[0]0
D[0]15 D[1]0 D[1]1
D[0]1
D[0]15 D[1]0
D[1]15
D[24]0 D[24]1
D[1]1
D[1]15
D[24]15
pl
pl
D[24]0 D[24]1
10
pl
D[24]15
409 410
ready
Hnh 4.23: Biu dng sng khi cut pilot
clk
rst_n
data_in
start
Samping
data_out
ready
Hnh 4.24: Khi sampling
Chng 5
Trin khai phn cng HDL
Chng ny chng ta s hc cch t chc cc file verilog nh th no cho hiu qu v
ch trong khi vit code. Trong chng ny chng ta s khng bn n cch vit code
verilog. hc cch vit code HDL, chng ta tham kho trang web: http://www.
asic-world.com/ mc Verilog Tutorial v lm cc bi lab ca altera: http://www.
altera.com/education/univ/materials/digital_logic/labs/unv-labs.html
5.1
5.1.1
Tng quan v verilog

Verilog l g
Verilog l mt ngn ng m t phn cng Hardware Description Language (HDL).

Mt ngn ng m t phn cng l mt ngn ng s dng m t mt h thng s:
v d nh mt b chuyn mch s, mt vi x l, mt b nh memory hay n gin
ch l mt flip-flop. C ngha l bng cch s dng ngn ng m t phn cng HDL,
chng ta c th m t bt c phn cng s no ti bt k mc no.
74
CHNG 5. TRIN KHAI PHN CNG HDL
5.1.2
1
75
M hnh m t phn cng
C 3 m hnh c s dng trong cc thit k verilog: M hnh cu trc, m hnh
RTL, m hnh hnh vi.

M hnh cu trc
c s dng ch yu kt ni cc phn t c bn v cc module con. Chng ta
m t m hnh cu trc qua cc bc sau:
Bc 1: Khai bo module
+ Tn module
+ Tn cng, kiu v kch thc cng
Bc 2: Khai bo cc dy dn bn trong mch
+ S dng wire cho vic m t dy dn.
Bc 3: To module con hoc primitive (cc cng logic c bn c nh
ngha sn). Sau kt ni a tn dy dn vo v tr u vo, ra tng ng
ca cng.
M hnh RTL
c s dng m t cc hm Bool v ng d liu.
Dng cu lnh gn lin tc assign
Gn biu thc bool cho bin wire
Cc php gn assign hot ng song song vi nhau
M hnh chnh xc, nhng vn d c hiu
1
Tham kho bi ging IC s ca Thy Minh
CHNG 5. TRIN KHAI PHN CNG HDL
76
M hnh hnh vi
Dng m t mch t hp v mch dy. Cc khi always v initial l cc thnh
phn chnh.
5.2
T chc file verilog
Mc ny ni v vic tham s ha cc tn hiu u vo v u ra. Chng ta thng

s dng parameter truyn tham s t cc modul lp trn xung cc modul lp
di
Ti liu tham kho

[1] Book Reference
1. Digital Communication by Satellite
2. Digital Communications, John G. Proakis
3. Digital Filters with MATLAB
4. ALTERA tutorial
5. XILINX tutorial
[2] FPGA Implementation of Carrier Synchronization for QAM Receivers
[3] Tri Budi Santoso, Lecture Note Developing on Simulation Programming of
16QAM in the AWGN Channel
[4] Hamid GHaravi, Pilot Asssited 16- Level QAM for Wireless Level, IEEE Transactions on circuits and systems for video technology, Vol. 12, No. 2, February
2002.
77

Tutorial QAM16

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Tutorial QAM16

Uploaded by

Copyright:

Available Formats

XY DNG H THNG

THU PHT 16-QAM

Danh sch bng

Danh sch hnh v

1 Quy trnh thit k b x l bng gc trong thng tin s

Kho st thut ton . . . . . . . . . . . . . . . . . . . . . . . . . . .

La chn kin trc thit k . . . . . . . . . . . . . . . . . . . . . . . .

Trin khai trn phn cng(HDL/FPGA) . . . . . . . . . . . . . . . .

Tng hp v layout ASIC

2 TRIN KHAI THUT TON 16-QAM TRN MATLAB

Thit k b m ha v gii m chp s dng thut ton Viterbi

Format into Symbols (QAM mapping) . . . . . . . . . . . . .

Zero Padding (Upsampling) . . . . . . . . . . . . . . . . . . .

Raise Cosine Filtering (FIR filter) . . . . . . . . . . . . . . . .

Digital Sin/Cos Oscilator (NCO) . . . . . . . . . . . . . . . .

Digital Analog Convert(ADC) . . . . . . . . . . . . . . . . . .

Timing phase recovery . . . . . . . . . . . . . . . . . . . . . .

Searching start symbol . . . . . . . . . . . . . . . . . . . . . .

La chn thng s cho Raise Cosine Filter . . . . . . . . . . .

Tng Quan V Simulink . . . . . . . . . . . . . . . . . . . . . . . . .

M Phng H Thng 16-QAM trn Simulink . . . . . . . . . . . . . .

Xy dng specification design . . . . . . . . . . . . . . . . . . . . . .

Raised cosin filter . . . . . . . . . . . . . . . . . . . . . . . . .

5 Trin khai phn cng HDL

Tng quan v verilog . . . . . . . . . . . . . . . . . . . . . . . . . . .

M hnh m t phn cng . . . . . . . . . . . . . . . . . . . .

T chc file verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ti liu tham kho

Danh sch bng

Tn hiu vo/ra ca khi cyclic prefix . . . . . . . . . . . . . . . . . .

Tn hiu vo/ra ca khi mapper . . . . . . . . . . . . . . . . . . . .

Tn hiu vo/ra ca khi zero padder . . . . . . . . . . . . . . . . . .

Tn hiu vo/ra ca khi raised cosin filter . . . . . . . . . . . . . . .

gi tr p ng xung ca khi raised cosin filter . . . . . . . . . . . .

Tn hiu vo/ra ca khi carrier multiplier . . . . . . . . . . . . . . .

gi tr ca sng mang sin v cosin . . . . . . . . . . . . . . . . . . . .

Tn hiu vo/ra ca khi pilot inserter . . . . . . . . . . . . . . . . .

4.10 Tn hiu vo/ra ca khi cut pilot . . . . . . . . . . . . . . . . . . . .

4.11 Tn hiu vo/ra ca khi sampling . . . . . . . . . . . . . . . . . . .

Danh sch hnh v

Quy trnh thit k b x l bng gc . . . . . . . . . . . . . . . . . .

M hnh m phng HIL cho h thng thng tin s . . . . . . . . . . .

Th Chm Sao 16-QAM . . . . . . . . . . . . . . . . . . . . . . .

Th Chm Sao 16-QAM khi c nhiu . . . . . . . . . . . . . . . .

code thc hin trn Matlab . . . . . . . . . . . . . . . . . . . . . . .

code chuyn i sang Simulink . . . . . . . . . . . . . . . . . . . . . .

Dng ca chui k hiu sau khi thc hin Upsampling . . . . . . . . .

p ng tn s ca Raise Code Filter khi thay i . . . . . . . . .

2.10 S khi Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 S khi Base Band Receiver . . . . . . . . . . . . . . . . . . . . .

2.12 Phng php ly mu Early-Later . . . . . . . . . . . . . . . . . . . .

2.14 S khi Loop Filter(D-PLL bc 2) . . . . . . . . . . . . . . . . . .

2.15 S khi b to dao ng NCO . . . . . . . . . . . . . . . . . . . .

2.16 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DANH SCH HNH V

2.17 kt qu m phng tn hiu trn nhiu h thng 16-QAM . . . . . . .

2.18 kt qu nh gi SNR ph thuc vo Ns ym . . . . . . . . . . . . . .

2.19 BER s dng m Gray v khng s dng Gray

2.20 ng gi data trong 16-QAM . . . . . . . . . . . . . . . . . . . . . .

2.21 Tn hiu Thu b xoay . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.22 Tn hiu Thu khi s dng khi synchronization . . . . . . . . . . . .

S khi 16-QAM trn Simulink . . . . . . . . . . . . . . . . . . . .

S khi 16-QAM trn Simulink . . . . . . . . . . . . . . . . . . . .

DANH SCH HNH V