2007



MULTISIM 7.0

1. Multisim 7.
O Multisim 7
.
,
.

,
. ,
,
.

(projects).
:
1. Multisim.
, .
. TTL.
- , .
TTL CMOS.
(basic),
(power source) (measurement
components).

.1 Multisim 7. TTL.

. 2 LED
2.
1. .
.
,
.
LED.
2.

Karnaugh.

Multisim
.

3.
:
,
, (on off)
.
) .
)
.
) Multisim
.

U3A

74LS11D
U3B
J1
Key = A

U2A
J2
Key = B

J3
Key = C

2.5 V

U4C
74LS11D
U3C

V1
5 V

X1
U4A

74LS04D

U2B
74LS04D

U2C
74LS04D

74LS11D

74LS32D
U4B

74LS32D

74LS32D

U1A

74LS11D

. 3

4.
:
: , , ,
, , , .
1, . ,
(=1)
(=1)
( = 0).

Multisim.
5. :

.

 - 2
-

Multisim. ,
Multisim,
.
1.
.
.

. 1

(Full Adder)

.

. 3.
bits
2.

. 2 bits

1. bits
block :
U2A

IO1

7486N

IO2

U1A

7408N

U2B

IO4

7486N
U1B

7408N

U3B

IO5

7432N

IO3

. 3 bits

. (add_sub.ms7) .
,
:

menu: Place, Create Hierarchical Block.

(. adder2b) . ,
bits ( bit
) (
).
. block . block
Edit Subcircuit. ,
,
. Vcc
. (Save as: adder2b) ,
.

. (copypaste) . , . 4
bits
(Fulladder 9 , 5 )
bits . block
(. 5).
block Place,
Hierarchical block. E block .

.X1

A1

IO1
IO2
IO3

IO4
IO5

S1

A2
adder2b1
A3

S2
S3
S4

X2

A4
IO1
IO2
IO3

IO4
IO5

Cout
adder2b1
B1
X3
B2

IO1
IO2
IO3

IO4
IO5

B3

adder2b1
X4

B4

IO1
IO2
IO3

IO4
IO5

adder2b1

Cin

. 4 bits

add_sub.ms7
:

J1
Key = A

J2

J5

X3

J6
X2

Key = B

X4
2.5 V

Key = C

X5
2.5 V

X6
2.5 V

2.5 V

Key = D

X1
A1
A2
A3
A4
B1
B2
B3
B4
Cin
G1

V1
5 V

J3

J4

J7

J8

S1
S2
S3
S4
I011

fulladder
Key = E

Key = F

Key = G

Key = H

. 5

5.
:

C0

14

15

2.5

Cout

6.
:

. 6 2
4-bit, XOR
,
2. Multisim
4 .

4
5
12
4
11
7
13
10

5
4
10
15
4
1
0
0

Cin

Cout

0
1
1
0
1
1
0
1

10

J1
Key = A

J2

J5

X3

J6

Key = B

X2
Key = C

X4

X5

2.5 V 2.5 V

Key = D

X6
2.5 V

2.5 V
2.5 V

X1
V1
5 V

U1A

U2A
J3

J4

J7

J8
7486N
U3A

Key = E

Key = F

Key = G

A1
A2
A3
A4
B1
B2
B3
B4
Cin
G1

S1
S2
S3
S4
I011

fulladder

Key = H
7486N
U4A

7486N
J9

7486N

Key = L

. 4 .

: 1)
.
2) Internet 74LS283

11

 - 3

, .

, .
bits. To bits
OR NOR.
bits , . 2.

bits.
,
.
TTL 74LS85 CMOS 4585.
4-bits 3 2 1 0 3 2 1 0 O_AGTB (out A
Geater Than B), O_ALTB (Out A Less Than B) O_AEQB (ut A Equal to B).
.

. 1. 74LS85

12

, 85 (AGTB, AEQB, ALTB),

bits. 500
12 bits 74LS85.
1
74LS85, .

1. 4-bits CMOS
4585, TTL 74LS85.
.

VCC
5V
J1

Key = A
VCC

J2
Key = B

J3
Key = C

J4
Key = D

X1

X2

5V
U1
15
14
2
1
7
9
10
11
4
6
5

2.5 V

X3
2.5 V

2.5 V

A3 OAGTB 13
B3 OAEQB 3
A2 OALTB 12
B2
A1
B1
A0
B0
AGTB
AEQB
ALTB
4585BD_5V

J6
Key = E

J7
Key = F

J8
Key = G

J9
Key = H

. 2 MSI CMOS 4585 ( TTL 74LS85)

2. MultiSim 7.0 (a, b)

bit,
bits. O
bits a b go eo. go 1 a>b, eo=1
a=b. gi ei

13

 bits .
(.. comp1.ms7).
gi

gi

Key = D
ei
Key = A
X2
2.5 V
V1
5 V

U2A

74LS08N

b
U1A

Key = B

U3A

74LS04D

74LS86N

U2B

74LS08N

U4A
g0

greater_out

74LS32N
X1
2.5 V

U2C
eo
74LS08N

equal_out

. 3 bits

3.
bits bits
1. block 2-bits.
, 2.
Multisim
.
, Multisim . 5.
(bus1 bus2) .

. 4 4-bits

14

X5

VCC
5V
X1
gi
ei
a
b

GND

X2

g_out
eq_out

gi
ei
a
b

full_comp1

X3

g_out
eq_out

full_comp1

gi
ei
a
b

g_out
eq_out

full_comp1

X4
gi
ei
a
b

g_out
eq_out

full_comp1

Bus1

Bus2

J2
Key = A

J3
Key = C

J4
Key = D

J1

Key = B

J6
Key = E

J5
Key = F

X6
2.5 V

J7

J8
Key = H

Key = G

. 5 4-bits Multisim 7.0

Y : 1.
.
2. 8-bits,
4585

15

2.5 V

 4
-

n m , m2n.
, m
1, . 3 8
1. ,
(minterms) n
. , x,y,z 000,
xyz, D0. . 2.

. 1 3 8.
.

16

. 2 3 8.

,
.
.
, 2n n ,
.

. 3 2--1 () , () .

3 bit Y,
S.
4 4--1.
0 3 AND. S1 S2
, AND. AND

17

 OR,
.

. 4 4--1 .

.
1.
,
, 5.
3.

. 5

18


1.
74LS151
.
. Multisim 7.0 74LS151.
X1

VCC
5V

2.5 V

U1
4
3
2
1
15
14
13
12
11
10
9
7

Key = A
J1

D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
~G

Y
~W

5
6

74151N

J2
Key = B

J3
Key = C

GND

. 6. 74LS151 ,

. ,
,,C.
C
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

19

. 74LS151

C
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

Y
1
1
0
0
0
1
1
0

2. .

(tri-state buffers)
2-bits (ND, OR, XOR, NAND).
bits bits.
bus -bits
. bus Place Bus.
.
(probes).

.
1-bit .
74LS139.
enable
(tri-state). H
.
2-bits.

BCD-to-seven-segment. 74LS47,
BCD ().

20

INPUT

5V

2-BIT LOGICAL OPERATIONS

J1

J2

WITH BINARY DECODER

VCC

X5

X1
Key = C

Key = D

2.5 V
Bus1

74LS125N

U2A

U6A

X2

INPUT DATA BUS

2.5 V

TRI-STATE BUFFERS

74LS08D
2.5 V

U3A

GND

74LS125N
U6B

X3

74LS32N

2.5 V

U4A

74LS125N
U6C

X4

74LS86D

2.5 V

U5A

74LS125N

VCC

U6D

74LS00D

5V
J4

U1A
2
3
1

Key = A
J3
Key = B

1A
1B
~1G

1Y0
1Y1
1Y2
1Y3

4
5
6
7

74LS139D
GND

DECODER

GND
SELECTION LINES

. 7 74LS139

21

VDD
5V

CA
U3
AB CDEFG
U1

J1
Key = A
J2

7
1
2
6
3
5
4

A
OA
B
OB
C
OC
D
OD
OE
~LT
OF
~RBI OG
~BI/RBO

13
12
11
10
9
15
14

74LS47N
Key = B
VCC
J3

Key = C

5V

GND

J4

V1
5 V

Key = D

. 8 74LS47 (BCD-to-7-segment)

:
1. .
2. CD4051. N
-
.
3. 16:1
74LS151. N 5.7.2 .
.
4. ,
:
F(x,y,z)=(1,2,6,7)

22

 5
FLIP-FLOP, ,

1. Flip-Flops
To flip=flop ,
.
(clock pulses) flip-flop,
(CP). flip-flops
:
R-S flip-flop, D flip-flop, J-K flip-flop, T flip-flop.
1.1 D Flip-Flop
H D Flip-Flop :
. CP=0, flip-flop ,
D.
. CP=1, D .
, .
.

. 1. D Flip-Flop .

. 2. 7474.

23

1.2 J-K Flip-Flop

J-K flip-flop 2.
:
. J=0 K=0, .
. J=0 K=1, Q=0.
. J=1 K=0, Q=1.
. . J=1 K=1, flip-flop (toggle).
J-K flip-flop .

Q(n)
0
0
0
0
1
1
1
1

J
0
0
1
1
0
0
1
1

K
0
1
0
1
0
1
0
1

Q(n+1)
0
0
1
1
1
0
1
0

3. JK FF

. 4 74LS112

24

2.
2.1 JK Flip-Flops.
Multisim 7.0
, J-K flip-flop 74LS112.
(CLOCK).

V1
5 V

4
3
1
2
CLOCK
J1

U1A

10

~1PR
1J
1Q 5
1CLK
1K
~1Q 6
~1CLR
74LS112D
15

U1B

~2PR
11 2J
2Q 9
13 2CLK
12 2K
~2Q 7
~2CLR
74LS112D
14

X1

Key = Space

3
1
2

U2A

10

~1PR
1J
1Q 5
1CLK
1K
~1Q 6
~1CLR
74LS112D
15

X2
2.5 V

U2B

~2PR
11 2J
2Q 9
13 2CLK
12 2K
~2Q 7
~2CLR
74LS112D
14

X4

X3
2.5 V

2.5 V

2.5 V

CLEAR
J2

Key = A

. 5 J-K flip-flops

flip-flops

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Q4
0

Q3
0

Q2
0

Q1
0

25

2.2 ( 74LS293)
Multisim7.0
.
X1

X2
2.5 V

X3
2.5 V

X4
2.5 V

2.5 V

U1
10
11
12
13

V2
5 V
V1

J1

10 Hz
5 V

INA
INB
R01
R02

QA
QB
QC
QD

9
5
4
8

74293N

Key = A

. 6 74LS293

2.3 modulo .

, . NAND,
000 111. NAND 111,
Q FF 101 ( NAND),
NAND CLEAR
FF. 101 ( 5)
. modulo 5.

. 7 modulo (up-counter) 8 5.

26

 . 5 ( 2.1),
modulo 16 12.
2.4 74LS194
T 74LS194 4-bits,
, ,
S0 S1, :

. 8 74LS194

Multisim 7.0
.

J1

J2

Key = A

Key = B

J3

J4

V1
5 V
Key = C

Key = D
X1

X2

X3

X4

Bus1
2.5 V
J8
Key = G

J7
Key = H

2.5 V

2.5 V

U1
3
4
5
6
7
2
9
10
1
11

J9
Key = S

A
B
C
D
SL
SR
S0
S1
~CLR
CLK

QA
QB
QC
QD

15
14
13
12

74LS194N
Key = E
J5
CLOCK
V2
5 V
Key = F
CLEAR

J6

. 9 74LS194

27

2.5 V

 :
:
. 24 .
. 12 24 , 1.
0.

28

 - 6

2.5 D-FF
N 74LS75 D-FF
Read/Write Chip_Select.

X12

VCC

X9

5V

X10
2.5 V

Bus1

J1

2.5 V

2.5 V
X5

X8
Key = A
J2
Key = B

2.5 V

X11

2.5 V

X6
2.5 V

X4

X7
2.5 V

X2
2.5 V

2.5 V
U1A
2

1D1 1Q1
~1Q1
3 1D2 1Q2
13 1EN1~1Q2

J3
Key = C

X1
2.5 V

74LS125D
16
1
15
14

74LS125D

U4A

U5A

74LS75N*
U6A
74LS125D

U2B
J4
Key = D

6
7
4

2D1 2Q1
~2Q1
2D2 2Q2
2EN2~2Q2

10
11
9
8

U7A
74LS125D

74LS75N*
74LS04D*
U9A
J5
CHIP_SELECT
U10A
Key = S

GND
U8A

74LS08D*

J6
Key = W

WR/RD_LINE

74LS32D*

GND

10 4-bits Read/Write Chip_Select

2.6 RAM 4x1.

M 4.4 block
bits.
.
74LS244,
. 4.5
.

29

X3
2.5 V

2.5 V

IO1
U1A
IO2

1Q1
~1Q1
3 1D2 1Q2
13 1EN1~1Q2

IO3
IO4

1D1

16
1
15
14
2
4
6
8
1

74LS75N*
U3B
6
7
4

2D1

2Q1
~2Q1
2D2 2Q2
2EN2~2Q2

U4A

10
11
9
8

1A1
1A2
1A3
1A4
~1G

1Y1
1Y2
1Y3
1Y4

IO8
18
16
14
12

IO9
IO10
IO11

74LS244N

74LS75N
U5A

74LS04D

U6A

EN_A
U2A

74LS08D

R_W
74LS32D

VCC 5V
GND

4.4

J1
X2

Key = A

X3
2.5 V

J2
Key = C

X4
2.5 V

X5
2.5 V

2.5 V

X1
IO1
IO2
IO3
IO4
EN_A
R_W

IO8
IO9
IO10
IO11

MEMORY4BX1

J3
Key = C

J5
Key = E
J4
Key = D
J6
Key = F

GND

4.5 block 4bx1.

30

RAM 4bx4
RAM
bits.
. 74LS139.
IO1

INPUT_BUS

U2A
IO2
IO3
IO4

2
4
6
8
1

1A1
1A2
1A3
1A4
~1G

DATA_BUS

1Y1
1Y2
1Y3
1Y4

IO9

18
16
14
12

X1
IO1
IO2
IO3
IO4
EN_A
R_W

74LS244N

IO8
IO9
IO10
IO11

IO10
IO11
IO12

MEMORY4BX1

BUS TRANSEIVER

X2
ADDR DECODER
A0
U1A
A1

2
3
1

1A
1B
~1G

1Y0
1Y1
1Y2
1Y3

4
5
6
7

74LS139D*
R_W
GND

IO1
IO2
IO3
IO4
EN_A
R_W

IO8
IO9
IO10
IO11

MEMORY4BX1
X3
IO1
IO2
IO3
IO4
EN_A
R_W

IO8
IO9
IO10
IO11

MEMORY4BX1
G_EN

X4
IO1
IO2
IO3
IO4
EN_A
R_W

IO8
IO9
IO10
IO11

MEMORY4BX1

4.6 block 4bx4.

4.
block RAM 4bx4.
probes .
,
ENABLE Read/Write. (Write)
1010, 0101, 1100 1111.
(Read) .

31

32


QUARTUS II
1. (downloading) Quartus II:
https://www.altera.com/support/software/download/sof-download_center.html

.
2. Quartus II.
http://www.altera.com/support/licensing/lic-choose.html
. NICID . command promt:>
ipconfig /all
o ipconfig slash. To
(.. 00-3E-12-5F-00-72).
e-mail. .dat.
mylicense.dat. (.. c:\altera\license\mylicense.dat).
2. Quartus
(Tools/license setup).

33

 - 7

1.

(CAD tools). O
,
. ,
, CPLDs FPGAs.
, .
CAD .
(blocks)
, Multisim.
(Hardware
Discription LanguageHDL), VHDL.
VHDL .
.

HDL

1.

34

 CAD . 1.
.
, ,
(synthesis), (place and route).
,

. ,
CPLD FPGA.

. CPLD
(Logic Arrays), AND OR,
FPGA (Look-up Tables).
Multisim,
. ,
,
. ,
.
, waveform vectors .
, .
. 1.
, ,
(place and route fitting).
.
(interconnection matrix),
.
,
,
.

3.

QUARTUS II

QUARTUS II CAD.
ALTERA,
CPLDs FPGAs.
.
(fitting),

() .
QUARTUS II
ALTERA CPLDs FPGAs
.
QUARTUS II, .
,
. QUARTUS II 2.

35

2. QUARTUS II

3.1
, .
,
. ,

(HDL).
, ,

,
.
.
.

,
. .
,
(blocks). ,
.
. 3.3
. F=AB + AB,
.
.

36

AB

3.

,
.
( ).
VHDL. ( Verilog),
()
. VHDL .

, .
, ,
.

HDL ,
.
,
Quartus.
, Quartus II
Editors: ) Waveform Editor. Editor
. ) Block Editor.
(.. ).
. ) Text Editor
.
(harware description languages) .

2.2

. QUARTUS II Analysis & Synthesis.

,
. , ,
CPLD.
,
(Logic Arrays). AND-OR

37

 CPLDs. FPGA,
,
(look-up tables). T,
,
, ,
, -.
,
, .
, .
, .

2.3 (FITTING)
(fitting) (place and route).
,
-. ,
. ,
(logic elements-LEs)
(chip) .
(programmable interconnect),
LEs .

2.4
(timing analysis), .
,
. ,
.
.
,

.
, (timing assignments)
.
(assembling) (.hex) (.sof)
. K ,
.
, , ,
Assembler, (Compilation).
(FPGA CPLD)
(Simulation),
(device programming) .

2.5

(Simulation)
.

38

.
.

. .


.
.

, .

.
(functional)
(timing).
( )
.
,
. .

2.6

. CPLDs FPGAs
.
,
assembler, (compilation) ,
.
ltera .
JTAG Active Serial (AS) mode.
board
( USB) board CPLD FPGA.
(driver) USB-Blaster BYTE-BLASTER.
JTAG ,
.
. (
FPGA) .
.
CPLDs, , , flash
EEPROM.
(AS) flash,
FPGA, .
Quartus II Flash chip FPGA.
.
RUN/PROG
board. (default) JTAG,
Active Serial (AS).

0 1
board. ,
.

39

3.
3.1 ,

Quartus II, Altera.
( )
FPGA,
. F=X1X2+X2X3+X1X3.
1 (Project)
Quartus II project.
project (
),
. , project
. project
FILE MENU| New Project Wizard.
, Project,
( 4). ,
. (projects).
. 4.

4. Project

40

FPGA

NEXT ,
FPGA . , Project
askhsh1 FPGA FLEX10KA
EPF 10K10TC144-4 ( . 5).

B 2
Project
. New
MENU FILE.
. Block
Diagram / Schematic File,
: Verilog HDL File VHDL File.
, Quartus II
, / flip-flop
. Menu Edit| Insert
symbol. , Symbol Tool,
. Primitives/logic, /
Primitives/Pins. 6 .

.
,
Project, askhsh1.

41

 6 . F=X1X2+X2X3+X1X3

.
Multisim, 7.

U1A

X1
X2
U3A

74LS08D
U1B

U4A

U5A
Y

X3
7404N
U3B

74LS08D

7427N

7404N

U2C
7404N
U3C

7408N
XLC1

7404N

AB

7. Multisim

42

 8. (Compilation).

3 Compilation (, , )
,
(Compilation). ,
, , Fitter, Assembler Timing Analyzer.
Menu Processing| Compiler Tool
Start . 8 ,
.
, ,
(LEs), bits , .

B 4
, .
Waveform Editor,
(waveform vectors) .
Waveform Editor , Menu File| New| Other Files|
Vector Waveform File. Quartus
9. Name, Insert Node or Bus.
Node Finder List
( Filter: Pins All).
, .

43

 9.

,
.
, Menu Processing Generate Functional
Simulation Netlist .
Menu|Assignments|Settings|Simulator Settings
Timing Functional ( ). Functional.
1s. (End Simulation at 1s).
, Editor (. 10),
, 1 0,
. . 11 .
(Waveform vector file) askisi1.wvf.

10. Waveform Editor.

,
1 0 .

44

 11.

, Menu Processing/start Simulation .

,
.
5 (pin assignments)
To
.
FPGA FLEX10K ALTERA
EPF10K10TC144-4 ( Menu Assignments/Device).

:
Menu Assignments/Pins. . 12.

. 12 FLEX10K.
.

45

 Node Name
. Location
. , . 12.

.
5 . ()
(compilation) (*.sof),
FPGA.
Programmer, Menu Tools|Programmer.
.

13. Programmer

(Hardware Setup)
. BYTE-BLASTER
USB-BLASTER
USB.
(.sof)
. , Program/Configure.
Start , .
.

46

 8
VHDL
8.1 - LED

8.1.1
,
,
(CAD).
,
. ,
VHDL,
QUARTUS II ALTERA.
VHDL

LEDs. - 8
8 LEDs . sw, 8 bits.
led, 8 bits.
8.1. sw[70],
, sw 8 bits, sw[7], sw[6],
. , sw[0]. led[70].

SW[7..0]

LED[7..0]

8.1 7 7 LED

8.1.2
VHDL,
. , .
.
.
(ENTITY).
. .
(ARCHITECTURE).
:

47

--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--
ENTITY vhdl1 IS
PORT ( sw: IN STD LOGIC VECTOR(7 DOWNTO 0);
led : OUT STD LOGIC VECTOR(7 DOWNTO 0));
END vhdl1;
--
ARCHITECTURE Behaviour OF vhdl1 IS
BEGIN
led <= sw;
END Behaviour ;

, .
, ieee.std logic 1164.all,
STD LOGIC VECTOR.
.
part1
() sw7 sw0 led7 led0.
.
.
Behaviour part1 (ARCHITECTURE Behaviour OF part1 IS).
LED (led <= sw;).
VHDL Quartus II,
project, (File/New Project
Wizard). project , vhdl1. project
(vhdl1).
VHDL Menu File/New
VHDL File.
, ,
.
Menu Processing/Start/Analysis and Synthesis.
.

, ,
.
(Waveform Vector File- *.wvf).
(waveform Editor).
(Assignments/ Settings/Simulation),
.

Menu
Processing/Start/Simulation.

. <=.
8.2 . sw[0] sw[7]
led[0] led[7] .
, 1,
. sw[2]=1
led[2]=1.

48

 8.2

8.2 2:1
8.2.1

2 1.
x , ( x=2),
. H n
2n=x. ,
21=2.

AND2

inst
OR2

NOTinst2

inst3
AND2

S
B
inst1

S
0
1

F
A
B

8.3

) )
)

49

 ,
.
. ,
.
S ( )
.

8.2.2

H VHDL.
2
1. .
ieee.std_logic_1164.all. mux2_1
x, y s f. bit. s
. WITH ( - VHDL)
. WHEN
f x s=0 y
( s=1). OTHERS VHDL
WHEN . s
std_logic, 0 , 1 ,
OTHERS s.
.

library ieee;
use ieee.std_logic_1164.all;
ntity mux2_1 is
port (x,y,s : in std_logic;
f : out std_logic);
end mux2_1;
rchitecture behavior of mux2_1 is
begin
with s select
f<= x when '0',
y when others;
end behavior;

8.4
. s,
.
s=1 f y 1.

50

 8.4

8.3

2:1 / 8 bits

8.3.1
2 1,
1 bit 5.2 8 bits.
.
, .
2= x.
.
8 bits
8 bits. 8.1.
x x [70]. y [70]
f [70]. s bit.
2 1 8 bits.

y[7..0]
x[7..0]

f~[7..0]
SEL
DATAA
DATAB

OUT0

f[7..0]

MUX21

8.5 2 1 8 bits

8.3.2
, 8 bits
.
STD LOGIC VECTOR
8 bits (ieee.std_logic_1164.all).
- (f : out std_logic_vector (7

51

downto 0)).
bits
. .

library ieee;
use ieee.std_logic_1164.all;
entity part2 is
port (x,y : in std_logic_vector (7 downto 0);
s : in std_logic;
f : out std_logic_vector (7 downto 0));
end part2;
architecture behavior of part2 is
begin
with s select
f<= x when '0',
y when others;
end behavior;

.
, bit
s.

8.6 8 bits

52

 9 -

2 4,
BCD 7segment ,
0 7 0,0,0,1,2,3,4,5 .

9.1 2 4
9.1.1

.
2 .
2 4 .

AND2
OUTPUT

Y0

OUTPUT

Y1

OUTPUT

Y2

OUTPUT

Y3

inst
NOT

X0

INPUT
VCC

AND2

inst6
inst3

AND2
NOT

X1

INPUT
VCC

inst7

inst4
AND2

inst5

1
0
0
1
1

0
0
1
0
1

0
1
0
0
0

1
0
1
0
0

2
0
0
1
0

3
0
0
0
1

9.1

2 4

53

9.1.2
2 4
.
.
2 bits,
bit .
.

.

. 00 0001, 01 0010,
10 0100 11 1000.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER_2TO4 IS
PORT(X :IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Y :OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END DECODER_2TO4;
ARCHITECTURE BEHAVIOR OF DECODER_2TO4 IS
BEGIN
WITH X SELECT
Y<= "0001" WHEN "00",
"0010" WHEN "01",
"0100" WHEN "10",
"1000" WHEN OTHERS;
END BEHAVIOR;
2 4.

9.1.

9.2 2 4

54

9.3 BCD 7-segment

9.3.1
BCD 7-segment
BCD, .
. BCD
(LEDs) .
a g.
.
LEDs .
9.3 .

3
0
0
0
0
0
0
0
0
1
1

2
0
0
0
0
1
1
1
1
0
0

1
0
0
1
1
0
0
1
1
0
0

0
0
1
0
1
0
1
0
1
0
1

a
1
0
1
1
0
1
1
1
1
1

b
1
1
1
1
1
0
0
1
1
1

9.3

c
1
1
0
1
1
1
1
1
1
1

d
1
0
1
1
0
1
1
0
1
1

e
1
0
1
0
0
0
1
0
1
0

f
1
0
0
0
1
1
1
0
1
1

g
0
0
1
1
1
1
1
0
1
1
)

9.3.2

BCD 7-segment
,
2 4.


. VHDL,
,
.
BCD 7-segment.
library ieee;
use ieee.std_logic_1164.all;
entity seg_7 is

55

port(c : in std_logic_vector (3 downto 0);

ex1: out std_logic_vector(6 downto 0));
end seg_7;
architecture behavior of seg_7 is
begin
with c select
ex1<= "1111110" when "0000",
"0000110" when "0001",
"1101101" when "0010",
"1111010" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1111011" when "1001",
"0000001" when others;
end behavior;

.
.
.

9.4

BCD 7-segment

56

9.4
1. N bits Quartus
VHDL.
. VHDL .

. 9.5 bits VHDL

2. Quartus II bits,
VHDL.
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY compare IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
AeqB, AgtB, AltB: OUT STD_LOGIC);
END compare;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB<='1' WHEN A=B ELSE '0';
AgtB<='1' WHEN A>B ELSE '0';
AltB<='1' WHEN A<B ELSE '0';
END Behavior;
;

57

2. ,
:

. 9.6

A
. Node finder
Numeric Value.

9.5
IF-THEN-ELSE
VHDL, , .
,
, , - PROCESS. PROCESS
VHDL .
(sensitivity list). ,
.

.
, ,
. 9.7, IF-THEN-ELSE
. w0,
w1 ( ) s.
.
, (PROCESS)
. , .
,
.

58

. 9.7 2:1 IF-THEN-ELSE

(PROCESS).

9.6 VHDL
9.6.1 D (latch)

59

9.6.2 (attributes) D Flip-Flop

D-FF .
(PROCESS),
, Q.
If-THEN-ELSE , EVENT. ,
EVENT Clock ClockEVENT.
Clock.
ClockEVENT Clock=1 Clock
1. , . , ,
Q ,
D Flip-Flop (positive edge triggering).

9.6.3 bits

60

9.6.4 bits

61

: VHDL
.1

VHDL ,
,
. VHDL
VHSIC Hardware Description Language, VHSIC Very High
Speed Integrated Circuit. 1980
1987 IEEE IEEE 1076. 1993
, IEEE 1164.
VHDL,
(Computer Aided Design CAD),
(standard) ASIC (Application
Specific Integrated Circuits). ,
.

.
.2 VHDL
VHDL
. ,
(, ), .
.2.1

VHDL
. ,
, ( )
.
.
. VHDL
_ ( -, a-z, _ , 0-9).
:

_ (ono__ma).

_
(_name name_).

(1name).


VHDL (entity).
VHDL .
.
.
1 bit
(.. 1), bits
(.. 0101).

62

.2.1.1

. .
,
. :
SIGNAL :

. :

BIT 0 1

BIT_VECTOR
0 1. .. signal z : bit_vector (0 to 3) ;

STD_LOGIC 0,
1, , -, L, H, U, X, W.

STD_LOGIC_VECTOR
STD_LOGIC, VECTOR
.

STD_ULOGIC
STD_LOGIC,

.

SIGNED/UNSIGNED

- .
STD_LOGIC.

INTEGER
, 32 bits (231-1) (231-1).
RANGE .. signal z : integer range -120
to 120

BOOLEAN TRUE
FALSE.

ENUMERATION O
.
.
.
STD_LOGIC STD_LOGIC_VECTOR
( ) :
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
std_logic ieee 1164

. SIGNED UNSIGNED
std_logic_signed std_logic_unsigned std_logic_arith

63

 .
STD_LOGIC.
.2.1.2
(Constants),
, .
.
.
, .
:
CONSTANT : := ;

.2.1.3
(VARIABLE)

. :
VARIABLE : ;

.2.1.4

VHDL
.

. :
_1 <= CONV___1 (_2, bits _1) ;
,
BIT_VECTOR 3 bits 4 bits STD_LOGIC_VECTOR,

:
<= CONV_ BIT_VECTOR (,3)

.2.2

VHDL ,
.

.2.2.1 (LOGICAL OPERATIONS)

VHDL .
.
.

64


Not
And
Nand
Or
Nor
Xor
Xnor
.1

, , Not
.
,
.

.2.2.2

(RELATIONAL OPERATORS)

,
.
.
Boolean, TRUE FALSE.

=
/=
<
<=
>
>=

.2

.2.2.3

VHDL , .

,
. x1*x2+x3*x4 x1 AND x2 OR x3 AND x4.
VHDL
(x1 AND x2) OR (x3 AND x4).
.

65

.2.3

VHDL .
- . ,
.

.3

VHDL

VHDL
. VHDL
(entities) (architectures).
.
VHDL (..
nand), .
. ,
. ,
, (component) .

.3.1

vhdl
/
. / ,
.
:
entity is
Port ( : mode ;
: mode ;

: mode );
end ;
.3

mode . , , .
:

in:
out:
buffer:
inout:

, ,
.
:

66



bit / bit_vector
std_logic / std_logic_vector
std_ulogic / std_ulogic_vector
Boolean / integer / real / character
time

VHDL.

.
.

.3.2

,
.
.
. (Declarative Region),
, , , .
BEGIN. H
(Architecture Body), BEGIN.
,
. .
ARCHITECTURE OF IS
Signal;
Constant ;
Type ;
Component ;
Attribute ;
BEGIN
;
END ;
.4

(Structural Style of Modeling ),
. B (Behavioral Style of
Modeling ), ,
(Dataflow Style of Modeling), .
.

67

.3.2.1

(components)
.
.
.

.
.
.
.

,
example_1.
Architecture STRUCT of example_1 is
signal M0, M1: BIT;
component
port ( x : in BIT ;
y: out BIT);
end component;
component NAND3
port (DO, Dl, D2: in BIT;
DZ: out BIT);
end component;
begin
Stage_0: port map (A, M0);
Stage_1: port map (, M1);
Stage_2: NAND3 port map (ENABLE, M0, M1, Z(0));
Stage_3 NAND3 port map (M0, B, ENABLE, Z(l));
Stage_4: NAND3 port map (A, M1, ENABLE, Z(2));
Stage_5: NAND3 port map (A, B, ENABLE, Z(3));
end STRUCT;

.5

(0 1),
.
.
.
( ) (components).
nand 3- (NAND3) not ().

68

 .
VHDL.
( )

.
. :
: PORT MAP ( ) ;
:


: ( Stage_0)


:
()


:
(A, M0 x, y ) .

2-4
enable, 1
0 0 (
). .6
.

ENABLE
1
1
1
1
.6

.3.2.2

A
0
0
1
1

B
0
1
0
1

Z0
1
0
0
0

Z1
0
1
0
0

Z2
0
0
1
0

Z3
0
0
0
1

2-4

.

.
.
Sequential Assignment Statements
,
. :
IF, CASE (FOR WHILE).

.
(PROCESS).
.

69

 PROCESS
2-4
example_2.
rchitecture Behavior of example_2 is
Begin
Process (A, B, ENABLE)
Variable M0, M1: BIT;
Begin
M0:= not A;
M1:= not ;
if ENABLE = 1 then
Z(3) <=A and ;
Z(2) <= A and M1;
Z(l) <= M0 and B;
Z(0) <= M0 and M1;
else
<= 0000;
end if;
end process;
end Behavior;

.7

,
.
(PROCESS) 0 1.

.
:= <= .
.
PROCESS
.
.

' ( ),
.
, ENABLE
(M0:= not A; M1:= not ;)
.
ENABLE. 1
else. 0
0.
.

70

.3.2.3

,
.
.
.

.
2-4.
rchitecture Dataflow of example_3 is
signal MO, M1: BIT;
begin
Z(3) <= A and and ENABLE;
Z(0) <= M0 and M1 and ENABLE;
Z(2) <= A and M1 and ENABLE;
Z(l) <= M0 and and ENABLE;
M0 <= not A;
M1 <= not ;
end Dataflow ;
.8

.
. 0
1 (4) (0) .

.

.3.2.4

, .
.

components ( ), (
) processes ( ).
.

.4

VHDL.
. -

71

 .

. ,
, .
,
.
:
library ;
use , .all ;
:
PACKAGE IS
[ ]
[ ]
END ;
.9

.5

VHDL ,
, .
(COMPONENT).
.
.
.
COMPONENT
[ GENERIC ( : integer := { ;
: integer := }) ; ]
PORT ( : mode ;
: mode ) ;
END COMPONENT;
.10

.
VHDL, .
( 3.5)
( )
, .
.
:
: PORT MAP ( ) ;

72

73