LP TRNH H THNG

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BI QUC BO

What is ARM?
ARM l t vit tt ca: Advanced RISC
Machine.

Cu trc da trn cu trc RISC
(Reduced Instruction Set Computer)

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RISC Architecture
Cu trc RISC c a ra nhm mc ch:
t tc x l cao bng cch:
Gim s lung lnh
C tp thanh ghi ln
X l theo dng load-store
Cc m lnh c di bng nhau
S dng cu trc pipelines
Cu trc n gin, cho php d dng thay i
c tn s hot ng cao hn
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The ARM Processor

c thit k cho cc ng dng nhng,
l CPU cho cc h thng system-on-chip

H tr tp lnh 16 bit v 32 bit

Cu trc khng thun ty l RISC.

Vi x l ARM c bn di dng 1 li
IP (intellectual property core)

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Main features of ARM Processor

-

Tc thp, khong vi trm

Mhz. Tuy nhin 1 s dng ARM
mi c th chy vi tc
khong 2Ghz
Tp lnh 32 bit, h tr tp lnh
Thumb v Thumb2 (16 bit).
Ch c 1 khng gian b nh
Cng sut thp
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ARM Processor families

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ARM-cortex M3
L vi iu khin 32 bit.

Cu trc Havard

Cng sut thp.

Chuyn dng cho cc ng dng nhng.

Gi r

p ng interrupt nhanh (low interrupt
latency).

Ch h tr tp lnh Thumb-2

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Cu trc Von Neumann

Code v data cha trong cng khng gian a ch.
Ch c 1 bus giao tip b nh.
Tn dng c khng gian nh.
Chng trnh c th thit k mm do hn.
Data c th b chp ln chng trnh.
B bottle neck trong qu trnh truyn data v d liu

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Cu trc Harvard
Dng 2 bus ring truy cp code v data
Code v data c th nm chung trong 1 khng gian nh
Truy cp code v data cng lc
Cho php di code v data khc nhau
Code khng b ghi bi data
Phn cng CPU phc tp hn

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Pipeline

Cu trc pipeline cho php mt lnh c

thc thi trong lc np v gii m cc lnh
khc.
Vi cu trc ny, mt lnh c th c
thc thi trong 1 chu k clock
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ARM Cortex M3 block diagram

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Memory endian
ARMv7-M cho php chn endian mode
cho cc tc v truy cp data.

Cc m lnh lun dng little endian

Cc lnh load v store vo khng gian
iu khin h thng (system control
space) lun dng little endian

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Processor operating mode

Handle mode: Khi CPU chy 1 chng trnh x

l exception (v d: trnh phc v ngt).
Thread mode: Khi chy mt chng trnh bnh
thng.
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Privileged access level

Trong ch truy cp u tin (Privileged
access level), CPU c truy cp ton
b ti nguyn h thng.

Sau khi reset, CPU s i vo trng thi
ny.

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User access level

Trong trng thi ny, CPU khng c
truy cp vo 1 s ti nguyn h thng
(VD: thanh ghi cu hnh).

S dng chy 1 chng trnh di s
iu khin ca 1 h iu hnh.

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Mode transition

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Chng trnh vi h iu hnh

H iu hnh chy ch thread
mode vi privileged access level.

Khi mt exception (VD: ngt timer) xy
ra, h iu hnh i vo ch handle
mode.

Cc tc v c thc thi thread mode
vi user access level.

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Stack Pointer Register

Thanh ghi R13 c s dng nh l thanh ghi

stack pointer cho tc v ang tch cc.
Bit [1:0] lun lun bng 00
SP_main:

L thanh ghi SP mc nh, s dng trong handle

mode hoc trong thread mode khi chng trnh
hoc OS chy ch Privileged level.

SP_Process:

c s dng trong thread mode

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PUSH {R0} ; R13=R13-4, then Memory[R13] = R0

POP {R0} ; R0 = Memory[R13], then R13 = R13 + 4
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Link Register
Thanh ghi R14 cha a ch quay v khi
lnh BL (Branch and Link) hay BLX
(Branch and Link with Exchange) c
thc thi.

C th c s dng trong cc lnh
quay v t trnh phc v ngoi l.

Bit thp nht lun lun bng 0.

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main ; Main program

BL function1 ; Call function1 using Branch with Link

; instruction.
; PC = function1 and
; LR = the next instruction in main

function1

; Program code for function 1

BX LR
; Return

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Program Counter Register

Thanh ghi R15 c dng nh Program
Counter.

Bit thp nht phi c set ln 1 khi 1
lnh r nhnh c thc thi ch ra
mode ang chy l Thumb mode

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Program Status Registers

ESPR v ISPR l thanh ghi ch c. Ta truy cp PSR bng lnh MSR:

MRS
MRS
MRS
MSR

r0, APSR ; Read Flag state into R0

r0, IPSR ; Read Exception/Interrupt state
r0, EPSR ; Read Execution state
APSR, r0 ; Write Flag state
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12

Combined Program Status Registers

MRS
MSR

r0, PSR
PSR, r0

; Read the combined program status word

; Write combined program state word

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Mask register
Dng cm cc exception:

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MRS
MRS
MRS
MSR
MSR
MSR

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r0, BASEPRI ; Read BASEPRI register into R0

r0, PRIMASK ; Read PRIMASK register into R0
r0, FAULTMASK ; Read FAULTMASK register
;into R0
BASEPRI, r0 ; Write R0 into BASEPRI register
PRIMASK, r0 ; Write R0 into PRIMASK register
FAULTMASK, r0 ; Write R0 into FAULTMASK
;register

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Thanh ghi iu khin (CONTROL)

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Bit CONTROL[1]
Lun bng 0 handle mode

Trong thread mode, n c th bng 0
hay 1

Ch c th ghi khi CPU Thread mode
v privileged state

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Bit CONTROL[0]

Ch c th ghi khi CPU privileged state

MRS
MSR

r0, CONTROL ; Read CONTROL

;register into R0
CONTROL, r0 ; Write R0 into
;CONTROL register

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Exception

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Exception

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Exception

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Vector table

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Vector table

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Vector table
EXPORT __Vectors
__Vectors
DCD StackMem + Stack
; Top of Stack
DCD Reset_Handler
; Reset Handler
DCD NmiSR
; NMI Handler
DCD
FaultISR
; Hard Fault Handler
DCD IntDefaultHandler
; MPU Fault Handler
DCD IntDefaultHandler
; Bus Fault Handler
DCD IntDefaultHandler
; Usage Fault Handler
DCD
0
; Reserved
DCD
0
; Reserved
DCD
0
; Reserved
DCD
0
; Reserved
DCD IntDefaultHandler
; SVCall Handler
DCD IntDefaultHandler
; Debug Monitor Handler
DCD
0
; Reserved
DCD IntDefaultHandler
; PendSV Handler
DCD SysTickHandler
; SysTick Handler
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Vector table
IntDefaultHandler
B
IntDefaultHandler

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Exception with CONTROL[1]=0

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Exception with CONTROL[1]=1

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Reset sequence

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Reset sequence

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