Written test

Q 1. Question on pass transistor logic. Output voltage was asked for

various combinations of gate and source voltages.
Q2. A logic expression was given. Its CMOS implementation was asked.
Q3. Simple question on Setup/hold time/clock frequency
Q4. 1 question that combined the concepts of a pass transistor and an opamp
Q5. Question on an RLC network. Voltage values at t(0) and t (infinity) was
asked
Q6. One more question on STA ( much tougher than the previous one)
Q7. Question on Fault analysis
Q8. Question on FIFO buffer
Q9. Question on memory mapping and pipelining
Q10. Question on process efficiency.

Note: Some questions may have been missed or reported incorrectly. This
is only a rough idea.