2012 1.

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39. ................................................................................................................ 49
40. ................................................................................................................ 50
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42. ................................................................................................................ 53

1 48

2 48

1.
.
(IV ) 0 256 .
64KB, , 16
, . PER1, PER2 PER3
5678h, 3456h 1234h, . 5, 3 1 IV PER1, PER2
PER3, , ,
.
) 0 5 IV ,
.
)
PC .
) ) .
) .

:
) .
IV
5 for PER1
11
10
4
9
8
3 for PER2
7
6
2
5
4
1 for PER3
3
2
0
1
0
.1
1
0

78h
56h

56h
34h

34h
12h

.1.
) .



. (PC, PSW ) .
:
inta (interrupt acknowledge) ,
IV ,
IV ( IVTP
)
IV PC.
. :
I ( ) PSW ,
T ( ) PSW
L ( ) PSW
.
) ) . ,

. PSW
.
. , . PSW
. , . PSW
. .
) RTI (return from interrupt).
:

3 48

,
PSW
PC .
PSW RTI,
RTI.

2.
4G (gig) 16 . 16 , 32
16 . , , . (IV)
. , PER1, PER2
PER3 3, 5 7 ,
12345678h, 23456789h 3456789h, . 16 0h,
4h 8h, .
) .
) 8 , .
) 5 .
) PER2 ?
) PER2
PER3.
) IV ?

LOAD
OUT
LOAD
OUT
LOAD
OUT

#3
0h
#5
4h
#7
8h

LOAD
STORE
LOAD
STORE

#2345h
11
#6789h
10

)
7

PER3

6
5

PER2

4
3

PER1

2
1
0

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

) 5

LOAD
STORE
LOAD
STORE
ili:
LOAD
OUT

#3456h
11
#789Ah
10

)64K

#7
4h

3456h
789Ah

2345h
6789h

1234h
5678h

3.
16GB (giga ). 32 ,
. , , . IV (Interrupt Vector)
4 0. , IRQ0 IRQ1,
IRQ1 , PER0 PER1, . PSW I
(Interrupt Enable) 1 L 0
. .
. INTE RTI . PC PSW
. PER0 PER1 02h 04h, .
0 1. PER0 2,
PER1 3. : INC
100h PER0 . 00h
1. () ,

4 48

. 2. PER1, 6. PER0.
. 101h AND #1
, 0. , SP
.

1
2
3




0
000A
4
000A
A00A INTE
0A0A POP
1
000A
5
00A0
A00B INC
0A0B OR #1
2
0A0A
6
000A
A00C RTI
0A0C PUSH
3
A00A
7
000A
0A0D RTI
) PER1 IV ?
) )?
) PER0 IVT.
) .
, , ,
, .
) 5. .
PSW . .

) IVT.
) 2
) LOAD #3; OUT 2
)

0100

INC

1
2

A00A
A00B

INTE
INC

3
4
5
6
7
8

0A0A
0A0B
0A0C
0A0D
A00C
0101

POP
OR #1
PUSH
RTI
RTI
AND #1

9
10
11
12

A00A
A00B
A00C
0102

INTE
INC
RTI

ACC
1
1
1
2
2
XX10b
XX11b
XX11b
XX11b
XX11b
1
1
1
2
2

1
1
1
2
3
3
4
1
5
5
5
-

I
1
0
1
1
0
0
0
0
1
1
1
0
1
1
1

L
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0

PRIRR1
1
-

PRIRR0
1
1
1
1
-

4
0101
I=1, L=0

0101
I=1, L=0
A00C
I=1, L=1

2
0101
I=1, L=0
A00C
I=1, L=0

5
0102
I=1, L=0

3
0101
I=1, L=0
A00C
)
101h
XX10b

5 48

A00Ch
XX11b
->

4.
64 KB. , 16
.
/ , / ,
. 8 0 .
4 IRQ0 IRQ3 , IRQ0
. 4 7 , .
, 0 3 . PSW I
(Interrupt Enable) , INTE (Interrupt
Enable, I 1) INTD (Interrupt Disable, I), L20
. 4 IMR (Interrupt Mask Register) i
IRQi. . IRQ1 IRQ3
PER1 PER3, , .
.
PER1 PER3.
100h 300h, .
) IRQ30 ?
) PER1 .
) PER1 .
INTH1: IN
FF00h
STORE (Dest)+

RTI
STORE ,
? .
) PER1 .
) PER3
PER1, ?

) IRQ0

) .

) INTH1:

LOAD
STORE
LOAD
STORE
INTE
IN
STORE

RTI

#01
0Ah
#00
0Bh
FF00h
(Dest)+

) I 1, IMR bb01 (, b ).

5.
16GB, 32 , 64
. , .
(IV) 4 2h. IRQM
IRQN .
0 1 IV , . . 2 IV
(TRAP), 3 . PSW
I (Interrupt Enable) . PSW PC
. . 32 . INTE, INTD, RTI, TRPE
TRPD . 1, 2,
0 3. INTE 0100h 1. ()
, .

6 48

2. IRQN, 5. IQM.
PSW- 0.
Slika 1
0100h
0101h
0102h
0103h
0104h
0105h

INTE
LOAD #1h
INC
STORE #1h
DEC
INTD

2
1000h INC
1001h PUSH
1002h POP
1003h RTI
1004h LOAD 1h
1005h OR #FFh

1006h
1007h
1008h
1009h
100Ah
100Bh

STORE 1h
RTI
POP
INC
PUSH
RTI

3
0000h 1001h
0001h 100Ah
0002h 1000h
0003h 1004h
0004h 1006h
0005h 1008h

) IRQM IRQN, ?
) , 0100h.
, , ,
, .
) 7. .
PSW I. .
) 1h )?

) IRQM 1000h, IRQN 1004h

) 0100h, 0101h, 1004h, 1005h, 1006h, 1007h, 0102h, 1000h, 1001h, 1002h, 1003h, 0103h, 1008h, 1009h, 100Ah, 100Bh,
0104h, 0105h

0
1
2

0100
0101

INTE
LOAD #1

3
4
5
6
7

1004
1005
1006
1007
0102

LOAD 1
OR #FFh
STORE 1
RTI
INC

8
9
10
11
12
13
14
15
16
17
18

1000
1001
1002
1003
0103
1008
1009
100A
100B
0104
0105

INC
PUSH
POP
RTI
STORE #1
POP
INC
PUSH
RTI
DEC
INTD

ACC
?
?
1
1
100A
10FF
10FF
10FF
1100
1100
1101
1101
1101
1101
1101
0103
0104
0104
0104
0103
0103

1
1
1
1
2
2
3
2
4
5
5
6
4

I=1, T=0
0102

I
0
1
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
0

T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

PRIRRN
1
-

PRIRRM
1
1
1
-

I=1, T=0
0103

I=1, T=0
I=1, T=0
0103

6
I=1, T=0
0104

I=1, T=0
0103
1101

7 48

)
I=1, T=0
0103h
) MEM[1] = 10FFh

6.
16GB, 32 , 64
. , .
(IV) 4 2h. IRQM1
IRQM2 , IRQM2 , IRQN
. 0, 1 2 IV , .
. 3 . PSW- I (Interrupt
Enable) T (Trap) , L .
PSW PC . . 32 . INTE, INTD,
RTI, TRPE TRPD . .
IMR. 1, 2, 0
3. TRPE 0100h 1. () ,
. 2.
IRQM1, 5. IRQN, 9. IRQM2. PSW-
0.
1
0100h
0101h
0102h
0103h
0104h
0105h

TRPE
INTE
LOAD #1h
INTD
STORE 1h
TRPD

2
1000h INC
1001h RTI
1002h POP
1003h PUSH
1004h DEC
1005h RTI

1006h
1007h
1008h
1009h
100Ah
100Bh

INC
RTI
LOAD 1h
INC
INC
RTI

3
0000h 1002h
0001h 1008h
0002h 1009h
0003h 1006h
0004h 1004h
0005h 1000h

) IRQM1, IRQM2 IRQN, ?

) , 0100h.
, , ,
, .
) 6. .
PSW I, T L. .
) 1h )?
) .
INTRQ ,
PSW IRQM1 IRQM2.

) IRQM1 1009h, IRQM2 1006h, IRQN 1004h

) 0100h, 0101h, 0102h, 1009h, 100Ah, 1004h, 1005h, 100Bh, 0103h, 0104h, 1000h, 1001h, 0105h
ACC I L PRIRRN PRIRRM2
0
?
0 0 00 1
100
TRPE
?
0 1 00 2
101
INTE
?
1 1 00 3
102
LOAD #1
1
1 1 00 1
1
0 0 10 4
1009
INC
2
1
0 0 10 5
100A
INC
3
1
0 0 10 1
3
2
0 0 10 6
1004
DEC
2
2
0 0 10 7
1005
RTI
2
1
0 0 10 8
100B
RTI
2
1 1 00 9
103
INTD
2
0 1 00 1
10 104
STORE 1h
2
0 1 00 1
2
3
0 0 00 1
11 1000
INC
3
3
0 0 00 1
12 1001
RTI
3
0 1 00 1
13 105
TRPD
3
0 0 00 1

PRIRRM1
1
1
-

8 48

3
I=1, T=1, L=00
0103

I=0, T=1, L=00

0105

2
I=1, T=1, L=00
0103
I=0, T=0, L=10
100B

T=1, I=1, L=00

0103h
T=0, I=0, L=10
100Bh

) MEM[1] = 2h
)

7.
64 KB, , 16
. . IV (Interrupt Vector)
IVTP. Trap 2 IVT.
PSW PC . . (Ri) 8 .
TRPE (Trap Enable) TRPD (Trap Disable) , trap-.
TRPE TRPD ( trap). 1, trap
2, 0 3. ,
trap-.
1
FF00h
FF01h
FF03h
FF04h
FF05h
FF08h

TRPD
MOV R0, #2
TRPE
DEC R0
JNZ FF03h
TRPD

2
00A0h POP
R1
00A1h PUSH R1
00A2h RTI

3
0000h
0001h
0002h
0003h
0004h
0005h
0006h

00h
A0h
00h
0Ah
00h
A0h
00h

4
00A0h POP R1
00A1h PUSH #2
00A3h RTI

) FF07h?
) IVTP ( 0, 7)?
) , FF00h, FF08h.
, , ,
, .
) R1 RTI 00A2h?
) , FF00h, ,
trap 2 4.
adresa instrukcija

:
) FF07h FFh.
) IVTP 1.
)

0
1
2
3
4

FF00
FF01
FF03
FF04

TRPD
MOV R0, #2
TRPE
DEC R0

00A0

POP R1

R0
?
?
2
2
1
1
1

R1
?
?
?
?
?
?
5

1
2

0
0
0
1
1
0
0

9 48


6
7
8

00A1
00A2
FF05

PUSH R1
RTI
JNZ FF03h

9
10
11
12
13

00A0
00A1
00A2
FF03
FF04

POP R1
PUSH R1
RTI
TRPE
DEC R0

14
15
16
17

00A0
00A1
00A2
FF05

POP R1
PUSH R1
RTI
JNZ FF03h

18
19
20
21

00A0
00A1
00A2
FF08

POP R1
PUSH R1
RTI
TRPD

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0

5
5
5
5
3
3
3
3
3
3
5
5
5
5
5
8
8
8
8

1
3
4
3
5
6
5
7
8
7
-

0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
0

5
T=1
FF
05

T=1
FF
05
6

T=1
FF
3

T=1
FF
7

T=1
FF
03
4

T=1
FF
08
8

T=1
FF

T=1
FF

) R1 5.
) : FF00, FF01, FF03, FF04, 00A0, 00A1, 00A3, FF02, .

0
1
2
3
4

FF00
FF01
FF03
FF04

TRPD
MOV R0, #2
TRPE
DEC R0

5
6
7
8

00A0
00A1
00A3
FF02

POP R1
PUSH #2
RTI
???

R0
?
?
2
2
1
1
1
1
1

R1
?
?
?
?
?
?
5
5
5

1
2
3
-

0
0
0
1
1
0
0
0
1

1
T=1
FF
05
2
T=1
FF
3
T=1

10 48

FF
02

8.
128KB, 16 ,
.
/ , . IV (Interrupt Vector)
IVTP (Interrupt Vector Table Pointer), IVTP 2.
IRQ0, IRQ1 IRQ2 , IRQ0 , IRQ2
, PER0, PER1 PER2, . 2, 3
4 IV , . . 16
10h, 20h 30h, . PSW- I (Interrupt Enable)
, L . PSW PC .
. 16 . INTE, INTD, RTI INT .
INT . 1, 2,
0 3. 0100h 1. ()
, .
2. IRQ2, 5. IRQ0.
PSW- 0. IMR .
3
0000h 0000h
0001h 0001h
0002h 1000h
0003h 1008h
0004h 1000h
0005h 100Ch
0006h 1009h
) IRQ0, IRQ1 IRQ2, ?
) 3 .
) .
) .
, , ,
, .
) 6. .
PSW I L. .
Slika 1
0100h
0102h
0103h
0104h
0106h
0108h

LOAD #2h
INTE
INC
ADD #2h
INT #3h
INTD

2
1000h PUSH
1001h INTE
1002h LOAD 1h
1004h INC
1005h STORE 1h
1007h POP

1008h
1009h
100Ah
100Bh
100Ch
100Dh

RTI
INTE
INC
RTI
INC
RTI

:
IRQ0 1000h, IRQ1 100Ch, IRQ2 1009h
LOAD #100Ch
STORE 5h
)
LOAD #2h
OUT 10h
LOAD #3h
OUT 20h
LOAD #4h
OUT 30h
)
100h, 102h, 103h, 1009h, 100Ah, 1000h, 1001h, 1002h, 1004h, 1005h, 1007h, 1008h, 100Bh, 104h, 106h, 100Ch,
100Dh, 108h, 109h
)
)

0
1
2
3

0100
0102
0103

LOAD #2
INTE
INC

4
5

1009
100A

INTE
INC

ACC
?
2
2
3
3
3
4
4

1
1
1
2

I
0
0
1
1
0
1
1
0

L
00
00
00
00
01
01
01
11

PRIRR0
1
-

PRIRR1
-

PRIRR2
1
1
-

11 48


6
7
8
9
10
11
12
13
14
15
16
17
18

1000
1001
1002
1004
1005
1007
1008
100B
0104
0106
100C
100D
0108

PUSH
INTE
LOAD 1h
INC
STORE 1h
POP
RTI
RTI
ADD #2
INT #3
INC
RTI
INTD

4
4
1
2
2
4
4
4
6
6
7
7
7

3
3
3
3
3
2
1
4
4
-

0
1
1
1
1
1
1
1
1
0
0
1
0

11
11
11
11
11
11
01
00
00
00
00
00
00

3
I=1, L=00
0104

I=1, L=00
0104
I=1, L=01
100B
0004

2
I=1, L=00
0104
I=1, L=01
100B

4
I=1, L=00
0108

I=1, L=00
0104h
I=1, L=01
100Bh
0004h

9.
16
IRQ IVT.
INTA .
, , 4 .
, .
, 0FF0h (I/O) 4
.
) .
) IRQ1 IRQ2 , .
) 16 , .

12 48


IMR

IRR
IRQ0

IRQ1

IRQ2

IRQ3

IRQ
INTA

clIRR0
clIRR1
clIRR2
clIRR3

INTA0
INTA1
INTA2
INTA3

LOAD #1001b
OUT 0FF0h

10.
8GB, 16 ,
. I/O
, . IV (Interrupt Vector)
IVTP (Interrupt Vector Table Pointer), IVTP 8. IRQ
IV . INTA
. , ,
4 , IRQ0 IRQ3
, IRQ0 , IRQ3 , PER0
PER3, , 2, 3, 1 4 ,
1007h, 1000h, 1010h 1003h . 8 10h,
20h, 30h 40h . ,
. , 00ABh I/O
, 4 .
Fh. PSW- I (Interrupt Enable) .
ACC, PSW PC . . 16 .
1, 2. 0100h 1. ()
, . 3.
IRQ0, 5. IRQ2, 7. IRQ1.
PSW- 0. INTE INTD . 1h
0.

13 48

1
2
1006h RTI
1010h LOAD 1h
0100h INTE
1000h INTE
1007h INTE
1013h XOR #1h
0101h LOAD 1h
1001h INC
1008h LOAD 1h
1016h STORE 1h
100Bh INC
1019h RTI
0104h DEC
1002h RTI
0105h STORE 1h
1003h INTE
100Ch STORE 1h
0108h INC
1004h DEC
100Fh RTI
0109h INTD
1005h INTE
) .
) , 0100h.
, , ,
, .
) 8. .
PSW I. .
) .
) IRQ0 IRQ3 , .

LOAD #02h
OUTB 0010h
LOAD #03h
OUTB 0020h
LOAD #01h
OUTB 0030h
LOAD #04h
OUTB0040h
) 0100h, 0101h, 0104h, 1007h, 1008h, 1010h, 1013h, 1016h, 1019h, 1000h, 1001h, 1002h, 100Bh, 100Ch, 100Fh, 0105h,
0108h, 0109h
)

0
1
2
3

0100
0101
0104

INTE
LOAD 1h
DEC

4
5

1007
1008

INTE
LOAD 1h

6
7
8
9

1010
1013
1016
1019

LAOD 1h
XOR #1
STORE 1h
RTI

10
11
12
13
14
15
16
17
18

1000
1001
1002
100B
100C
100F
0105
0108
0109

INTE
INC
RTI
INC
STORE 1h
RTI
STORE 1h
INC
INTD

ACC
?
?
0
-1
-1
-1
0
0
0
1
1
0
0
0
1
0
1
1
-1
-1
0
0

1
1
1
2
2
2
2
1
3
3
3
1
1
1
-

PRIRR
1
1
1
1
1
-

IRR0
1
-

IRR1
1
1
1
-

IRR2
1
-

IRR3
-

3
FFFF
I=1
0000
0105

2
FFFF
I=1
0000

I
0
1
1
1
0
1
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0

FFFF
I=1
0000
0105
FFFF
I=1
0000
100B

14 48

0105
FFFF
I=1
0000
100B
FFFFh
I=1
0000h
0105h
0000h
I=1
0000h
100Bh

)
IMR

IRR
IRQ0

IRQ1

IRQ2

IRQ3

IRQ
INTA

clIRR0
clIRR1
clIRR2
clIRR3

INTA0
INTA1
INTA2
INTA3

LOAD #0110b
OUTB 0000 00ABh

11.
16
IRQ0 IVT.
INTA0 .
IRQ0 3 .
) .
) , ?

) Daisy chainig

) IRQ0 IRQ3 , ; INTA0

( READ ).

12.
8GB, 16 ,
. U/I

15 48

, . IV (Interrupt Vector)
IVTP (Interrupt Vector Table Pointer), IVTP 16h. IRQM
IRQN ,
IV . INTA
. , ,
Daisy chainig. IRQM , PER1, PER2 PER3,
PER1 , IRQN PERN, 3, 5, 1 7
, 1007h, 1000h, 1003h 1010h, . 8
10h, 20h, 30h 40h . PSW- I (Interrupt Enable)
, L . ACC, PSW PC
. . 16 . 1,
2. 0100h 1. () ,
. 2.
PER1, 5. PER2, 7. PERN.
PSW- 0. INTE INTD . 1h 0.
1
2
1006h RTI
1013h XOR #1h
0100h INTE
1000h INC
1007h INTE
1016h STORE 1h
0101h LOAD 1h
1001h INC
1008h LOAD 1h
1019h RTI
0104h DEC
1002h RTI
100Bh INC
0105h STORE 1h
1003h INTE
100Ch STORE 1h
0108h INC
1004h DEC
100Fh RTI
0109h INTD
1005h INTE
1010h LOAD 1h
) .
) 8 , .
) .
) , 0100h.
, , ,
, .
) 8. .
PSW I. .

LOAD #03h
OUTB 10h
LOAD #05h
OUTB 20h
LOAD #01h
OUTB 30h
LOAD #07h
OUTB 40h

)
IV
25h
7 PERN
24h
23h
6
22h
21h
5 PER2
20h
1Fh
4
1Eh
1Dh
3 PER1
1Ch
1Bh
2
1Ah
19h
1 PER3
18h
17h
0
16h

1010h
0000h

1000h
0000h

1007h
0000h

1003h
0000h

16 48

IRQM
INTAM

INTA

PER1

IRQ
INTA
INTA
PER2

CPU
READ

IRQN

READY
INTA

ENABLE

IRQ
INTA
PER3

PERN

INTAN
) 0100h, 0101h, 1007h, 1008h, 100Bh, 1000h, 1001h, 1010h, 1013h, 1016h, 1019h, 1002h, 100Ch, 100Fh, 0104h, 0105h,
0108h, 0109h

0
1
2

0100
0101

INTE
LOAD 1

3
4
5

1007
1008
100B

INTE
LOAD 1
INC

6
7

1000
1001

INC
INC

8
9
10
11
12
13
14
15
16
17
18

1010
1013
1016
1019
1002
100C
100F
0104
0105
0108
0109

LOAD 1
XOR #1
STORE 1
RTI
RTI
STORE 1
RTI
DEC
STORE 1
INC
INTD

ACC
?
?
0
0
0
0
1
1
2
3
3
0
1
1
3
1
1
0
-1
-1
0
0

1
1
1
1
2
2
2
3
3
3
3
2
1
1
-

PRIRRN
1
-

PRIRRM
1
1
-

IRQM1
1
-

IRQM2
1
-

IRQM3
-

3
0000
I=1
0104
0000

2
0000
I=1
0104
0000
0001
I=1
100C
0000

I
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0

0000
I=1
0104
0000
0001
I=1
100C
0000
0003
I=0
1002
0000

17 48

0000h
I=1
0104h
0000h
0001h
I=1
100Ch
0000h
0003h
I=0
1002h
0000h

13.

IRQ , . 16, 8
. IRQ 4 PER1PER4.
READY 1.
PER1 PER4 FF01h, FF02h, FF03h FF04h, READY
7, 3, 5 1. 100h, 200h, 300h 400h,
RTI. PER4 , PER1 . ACC,
PSW PC .
) , IRQ.
) ) RTS
( )?

INTH: LOAD FF04h; PER4

AND #02h
JNZ 400h
LOAD FF03h; PER3
AND #20h
JNZ 300h
LOAD FF02h; PER2
AND #08h
JNZ 200h
LOAD FF01h; PER1
AND #80h
JNZ 100h
RTI;
ELSE
) JUMP- JSR (Jump to Subroutine), RTI

18 48

14.
(,
) :
) ,
)
) .
.

:
) ABUS, DBUS, RDBUS FCBUS ,
, .
L
L
L
L

ABUS
DBUS
RDBUS
FCBUS

L
L
L

) ABUS, DBUS, WRBUS FCBUS ,

, .
L
L
L
L

ABUS
DBUS
WRBUS
FCBUS

L
L
L

) DBUS FCBUS , ,
inta, /
, .

DBUS
inta
FCBUS

L
L
L
L
L

15.
(,
) :
) ,
)
) .
.

a) ABUS, DBUS RDBUS ,

, .

19 48

tcitanje

i i+1

MCLK
ABUS
DBUS
RDBUS

j j+1
L
L
L
L
L
L
L

) ABUS, DBUS WRBUS ,
, .
tupis

i i+1

MCLK
ABUS
DBUS
WRBUS

j j+1
L
L
L
L
L
L
L

) DBUS
inta, , /
, .
tulaz

i i+1

MCLK
ABUS
DBUS
inta

j j+1
L
L
L
L
L
L

16.
64B. .
/ . 32B ROM ,
32KB RAM . RAM 8KB RAM
, ROM 8B ROM .
256x4- RM ( R, W CS) 1024x4- ROM ( R CS).
) ,
RAM, ROM , RAM , ROM .
.
) RAM ROM ?
.

)
?

RAM
ROM
a RAM a
a ROM a

0000h
0000h
8000h
0000h
8000h

FFFFh
7FFFh
FFFFh
1FFFh
9FFFh

) RAM .
numRam =

RAMSize
8Kx8
8Kx8
64 128x8
=
=
=
= 64
RAMChipSiz e 256x 4 2 128x 4
128x8

20 48

RM .
numRom =

ROMSize
8Kx8
8Kx8
16 512x8
=
=
=
= 16
ROMChipSiz e 1024x 4 2 512x 4
512x8

17.
1MB, . 16-
. MAR 8- MDR.
/ . MEM
PER . 256KB
.
)
.

21 48

) 128x4 (
R, W CS).

) .

) .
RAMSize
256Kx8
256Kx8
256Kx8 4 64x8
numRam =
=
=
=
=
=4
RAMChipSiz e 128Kx 4 2 64Kx 4
64Kx8
64x8

18.
/ .
16- (W). , .
8GB, 2GB ROM .
/ 1GW 0h.
a)
.
) , - ,
RAM ROM .
.
) RAM 4GB
RAM , SRAM 512x8 ( R, W
CS).

22 48

) ROM 1GB
ROM , ROM 256x8 ( R
CS).
)
STORE C000 0000h, R1 (.). . , .

) .

)
?

-
RAM
ROM

0000 0000h
0000 0000h
0000 0000h
C000 0000h

FFFF FFFFh
3FFF FFFFh
BFFF FFFFh
FFFF FFFFh

) RAM .
numRam =

RAMSize
2Gx16
2Gx16
2Gx16
8 256Mx16
=
=
=
=
=8
RAMChipSiz e 512Mx8 2 256Mx8 256Mx16
256Mx16

23 48

) RM .
numRom =

ROMSize
512Mx16 512Mx16
4 128Mx16
=
=
=
=4
ROMChipSiz e
256Mx8 2 128Mx8
128Mx16

24 48

) STORE . , C000 0000

ROM . ROM
FC , .
ROM ( I ,
W ROM )
FC. ,
ROM .

19.

. W 1 16 .
STOREB MDRL MAR.
STOREW MDRH ( ) MDRL ( )
MAR. 16 .
.
) ? ML MH?
) ML, MH?
) : (i) STOREW 8h, (ii) STOREW 5h.

25 48


MAR

MARinc

INC

MDRL

MDRH

MARout

rd

22

wr

m/io

Hout2

D 15 - 8

A
D 15 - 8
D 7-0
RD

Hout1

Lout2

D 7-0

D 15 - 8

D 7-0

Lout1

22
8
8

WR
M/IO
W
3
A 20
A 21

E
0
1

DC 0
DC 1
DC 2
DC 3

0
1
2
3

DC

RD
WR
A0

DC

A 19 - 1

D 7-0
A

D 15 - 8

A 19 - 1
A

RD

WR

CS

CS

ML

MH
DC 0
A0
W
DC 0
A0
W

) 4MB, 512KB, 512KB

) ML: 0h, 2h, ... ( ), MH: 1h, 3h,... ( ).
) 1; 2.

20.
16- little-endian ( ).
. 16 16 .
- .
(HMODULE) (LMODULE) :
16-
16-
:
R:
W:
BEH(Byte Enable High): D15..8
BEL (Byte Enable Low): D7..0
) . .
?
) 16- ABCDh. 1234h,
1. ?
2. () .
3. () ?
4. ?
) 1235h, 1. 4.
D15..8 D7..0
.

)
BEH BEL,
. BH HMODULE, BEL
LMODULE. HMODULE,
1h, 3h, 5h, 7h, 9h (0=1). LMODULE,

26 48

0h, 2h, 4h, 6h, 8h (0=0).

.

) , .
1234h,
8 , 8 .
W . LMODULE HMODULE
BEL BEH . ,
.

.
1234h

D0-7
CDh

D15-8
ABh

R
0

W
1

BEH
1

BEL
1

) ,
. HMODULE , LMODULE
. ,
.

1
2

.
1234h
1236h

D0-7
XX
ABh

D15-8
CDh
XX

R
0
0

W
1
1

BEH
1
0

BEL
0
1

21.
16- 8192 .
SRAM 64x4 ( R, W CS). little-endian.
. 8- 16- .
- . .

BE1 D15..8, BE0

D7..0. (BEx - Byte Enable x).
RAM .

numRam =

RAMSize
8192 1024x8 1024x8
=
=
=
= 32
RAMChipSiz e 64x 4 2 32x 4
32x8

27 48


BE0
E

9 7

6 1

6 1

6 1

6 1

R
W
0
1

CSL0
CSL1

CSL0
A

DC ...

5 0

W 64x4

W 64x4

CS

CS

...
7

50

CSL7

D 3 0

D 3 0

D 3 0

7 .. 4

...

R
W
CSL7
A

50

W 64x4

W 64x4
CS

9 7

D 3 0
D 3 0

7 .. 4

R
W
0
1

5 0

CS

D 3 0

BE1

CSH0
CSH1

CSH0

DC ...

5 0

50

W 64x4

W 64x4

CS

CS

...
7

D 3 0

D 3 0
CSH7

D 15..12

D11 8
...

R
W
CSH7
R

5 0

50

W 64x4

W 64x4

CS

CS

D 3 0

D 3 0

D 15..12

D11 8

8- 16-
BE0 BE1.
,
.

28 48

29 48

22.
32- big-endian ( ) ( 32-
32- ). .
ROM RAM . ROM , RAM
ROM . ROM 1MB 16 , 4Kx4
. RAM 8MB 32-, 16Kx2 .
. - .

ROM
RAM

00000000h
00100000h

000FFFFFh
008FFFFFh

ROM 512Kx8 4Kx4 .

.

numRm =

ROMSize
512Kx8 512Kx8
=
=
= 256
ROMChipSiz e
4Kx 4
2Kx8

512Kx8 .

ROM .
20 31 ROM
ROMENABLE. BE1

30 48

D15..8, BE0 D7..0.

ROM0 (1h, 3h, 5h, 7h, 9h,..), a ROM1 (0h, 2h, 4h, 6h, 8h,..).

ROMENABLE = A 31...A 20
CS0 = ROMENABLE BE1
CS1 = ROMENABLE BE0

RAM 2Mx8 16Kx2 .

numRm =

RAMSize
2Mx8 2Mx8
=
=
= 512
RAMChipSiz e 16Kx 2 4Kx8

2Mx8 RAM .

RAM .

31 48

RMENABLE =

A 31 ...A 24 (A 23 A 22 + A 23 A 21 + A 23 A 20 + A 23 A 22 A 21 A 20 )

CS0 = RMENABLE BE3

CS1 = RMENABLE BE2
CS2 = RMENABLE BE1
CS3 = RMENABLE BE0

23.
big-endian 24- 16-
. .
a) 2 MB 1024x4 SRAM .
R, W CS0 CS1.
) a) 4MB .

:
a) RAM 2Mx8 1024x4 .

numRm =

RAMSize
2Mx8
2Mx8
=
=
= 2048
RAMChipSiz e 1024x 4 512x8

32 48

A9..0

CS0

W
E

CSL0
CSL1

0
1

A15..10

CSL0
CSH0

...

DC

A9..0

R A9..0

1024x4
CS0

1024x4
CS0

CS1

CS1

D3..0

D3..0

62

CSL63

63

D3..0

D7..4
...

A9..0

CS1

R
W

CSH0
CSH1

0
1

A20..16

...

DC

30
31

CSH31

CSL63
CSH61

R A9..0

1024x4
CS0

1024x4
CS0

CS1

CS1

D3..0

D3..0

A9..0

D3..0

D3..0

2Mx8 .

) 2Mx8 ) 4Mx8
.

CS0 = BE1
CS1 = BE0

RAM0 (0h, 2h, 4h, 6h, 8h, )

RAM1 (1h, 3h, 5h, 7h, 9h, )

33 48

24.
, 16- 8-
. .

0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000h

14h

0h

05h

00h

32h

15h

31h

FFh

0Ah

00h

16h

000Bh 000Ch 000Dh 000Eh

01h

F0h

00h

10h

16- e PC ( ), SP (
), A (), AR ( ).
PC. , .
JSR .
SP = DEE0h AR = 9, 16- .

0000h
0003h
0005h
0007h

LOADW PC(05h)
ADDB(AR)+
JSR(AR)
HALT

;potporogram
X
OUTB F000h
X+4
RTS

; relativno adresiranje sa 8-bitnim pomerajem

; autoinkrement adresiranje
; skok u potprogram, registarsko indirektno
; zaustavljanje procesora

; memorijsko direktno
; povratak iz potprograma

) X?
) ,
.

:
a) AR JSR.
, AR 9. ,
X = 10 = 000Ah.
) .

34 48

M/ IO

0000h

14h

LOADW PC(5),

0001h

0Ah

LOADW PC(5),

0002h

05h

LOADW PC(5),

0008h

0Ah

LOADW PC(5) ,

0009h

00h

LOADW PC(5),
ACC=0A00h

0003h

00h

ADDB(AR)+,

0004h

32h

ADDB(AR)+,

0009h

00h

ADDB(AR)+

0005h

15h

JSR(AR),

10

0006h

31h

JSR(AR),

11

DEE0h

07h

JSR(AR), PC

12

DEDFh

00h

JSR(AR),
PC

13

000Ah

16h

OUTB F000h,

14

000Bh

01h

OUTB F000h,

15

000Ch

F0h

OUTB F000h,

16

000Dh

00h

OUTB F000h,

17

F000h

00h

OUTB F000h

18

000Eh

10h

RTS

19

DEDFh

00h

RTS, PC

20

DEE0h

07h

RTS, PC

21

0007h

FFh

HALT

35 48

25.
/
. 32MB, 16- (W). /
. .

0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000h

A000h 0000h 0000h E004h F000h E028h 0000h 0009h 0500h 0050h 0000h

,
. 16 .

0000h
0003h
0005h

LOAD R1,0
OUT PC(F000h),R1
STORE (9h),R1

; memorijsko direktno adresiranje

; relativno adresiranje sa 16-bitnim pomerajem
; memorijsko indirektno adresiranje.

M/ IO

00 0000h

A000h

LOAD R1,0, a

00 0001h

0000h

LOAD R1,0,

00 0002h

0000h

LOAD R1,0,

00 0000h

A000h

LOAD R1,0

00 0003h

E004h

OUT PC(F000h),R1,

00 0004h

F000h

OUT PC(F000h),R1,

FF F005h

A000h

OUT PC(F000h),R1

00 0005h

E028h

STORE (9h),R1,

00 0006h

0000h

STORE (9h),R1,

10

00 0007h

0009h

STORE (9h),R1,

11

00 0009h

0050h

STORE (9h),R1,

12

00 000Ah

0000h

STORE (9h),R1,

13

50 0000h

A000h

STORE (9h),R1

36 48

26.
4 16- (R0-R3)
16 , 8 .
. .

0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h

00h

30h

0Eh

0Eh

30h

30h

00h

3000h 3001h 3002h 3003h 3004h 3005h 3006h 3007h 3008h 3009h

05h

30h

11h

0Ah

30h

05h

22h

0Ch

44h

02h

FFh

300Ah 300Bh 300Ch 300Dh 300Eh 300Fh 3010h 3011h 3012h 3013h

00h

00h

05h

30h

00h

02h

04h

F0h

12h

C0h

PC.
SP .
, SP=4000h, IVTP=0h, PC=3000h. ,
.

3000h
3004h
3007h
3009h
...
300h
3011h
3013h

LOAD R1, (300Ah)

LOAD R2, (R1)0Ch
INT #2
HALT

;
;
;
;

ADD R2, #4
PUSH R2
RTI

; neposredno adresiranje
; registarski direktno adresiranje
; povratak iz prekidne rutine

memorijski indirektno adresiranje

registarski indirektno sa 8-bitnim pomerajem
softverski prekid
zaustavljanje procesora

M/ IO

3000h

05h

LOAD R1, (300Ah),

3001h

11h

LOAD R1, (300Ah),

3002h

0Ah

LOAD R1, (300Ah),

3003h

30h

LOAD R1, (300Ah),

300Ah

00h

LOAD R1, (300Ah),

300Bh

00h

LOAD R1, (300Ah),

0000h

00h

LOAD R1, (300Ah),

0001h

30h

LOAD R1, (300Ah),
R1=3000h

37 48

3004h

05h

LOAD R2, (R1)0Ch,

10

3005h

22h

LOAD R2, (R1)0Ch,

11

3006h

0Ch

LOAD R2, (R1)0Ch,

12

300Ch

05h

LOAD R2, (R1)0Ch,

13

300Dh

30h

LOAD R2, (R1)0Ch,
R2=3005h

14

3007h

44h

INT #2,

15

3008h

02h

INT #2,

16

4000h

09h

,
PC-a

17

4001h

30h

,
PC-a

18

0004h

0Eh

19

0005h

30h

20

300Eh

00h

ADD R2,#4,

21

300Fh

02h

ADD R2,#4,

22

3010h

04h

ADD R2,#4,
R2=3009h

23

3011h

F0h

PUSH R2,

24

3012h

12h

PUSH R2,

25

4002h

09h

PUSH R2, R2

26

4003h

30h

PUSH R2, R2

27

3013h

C0h

RTI

28

4003h

30h

RTI, PC

29

4002h

09h

RTI, PC

30

3009h

FFh

HALT

38 48

27.
32- big-endian ( ), 32-
29- . . . STORE AABBCCDDh
12345676h.
a) ,
D31..0.
) ,
D15..0.

MEM[12345676] = AAh
MEM[12345677] = BBh
MEM[12345678] = CCh
MEM[12345679] = DDh
)

1
2

.
12345674h
12345678h

D0..7
BBh
XX

D15..8
AAh
XX

D23..16
XX
DDh

D31..24
XX
CCh

R
0
0

W
1
1

M/ IO
1
1

BE3
0
1

BE2
0
1

BE1
1
0

BE0
1
0

1
2

.
12345676h
12345678h

D0-7
BBh
DDh

D15-8
AAh
CCh

D23-16
XX
XX

D31-24
XX
XX

R
0
0

W
1
1

M/ IO
1
1

BE3
0
0

BE2
0
0

BE1
1
1

BE0
1
1

28.
little-endian 32- 64 . . LOAD,
16- 1234567Ah. BBh
,
.

D0..7

D15..8

D23..16

D31..24

D39..32

D47..40

D55..48

D63..56

12345676h

XX

XX

XX

AAh

BBh

XX

XX

XX

RD, BE2, BE3

0 15 23 63 .

29.
:
a) .
) .
) .
,
?

39 48

BUSYBUS
BCLK

modul
0

modul
1

BG_OUT
BG_IN

BR

BG_OUT
BG_IN

BR

CD
...
...
...

0
0

BG_OUT
BG_IN

BR

...
...

modul
(n-1)

...

n-1

m-1
m-1

DC
0

...
...

ARBITRATOR

)
BUSYBUS
BCLK

modul
0
BR
BG_IN

modul
1
BR
BG_IN

BG_OUT
BG_OUT
1
) BUSYBUS .

...

...

modul
(n-1)
BR
BG_IN

BG_OUT

30.
1MB, . 16-
. MAR 8- MDR.
/ . MEM
PER .
. CR 10h, SR
11h, DR 12h, IE
13h. IE intack.

40 48

A
20
D
8
RD
WR
M/IO

RD intack
D2

RD
D1
WR
D0
M/IO
A19..5 15
A4

LD

A3..2
2
A1
A0

CR

E
0
1

DC

SR

0
1
2
3

WR
D2

LD

DR

WR
D3

LD

IE

D0
D1
D2
D3

31.
/ .
16- (W). , .
8GB. / 1GW
0h. DMA .
; ,
10 . : DMA
.

(Source)

32

ARSH, ARSL

0h, 1h

(Destination)

32

ARDH, ARDL

2h, 3h

32

CNTH, CNTL

4h, 5h

16

DR

6h

16

SR

7h

16

CR

8h

IVT

16

IE

9h

41 48

/
32.
16 .
16 . .
PER0 PER1 , : FF00h, FF01h,
FF02h (PER0) FF10h, FF11h, FF12h (PER1). Enable Interrupt
, Start , 1 (0
, 1). Ready.
200h PER0, F000h, Obrada,
PER1. . Obrada
. ,
CALL Obrada.

:
LOAD
STORE
LOAD
STORE
LOAD
OUT
LOOP1:IN
AND
JZ
IN
STORE
LOAD
INC
STORE
LOAD
DEC
STORE
JNZ
LOAD
OUT
CALL
LOAD
STORE
LOAD
STORE
LOAD
OUT
LOOP2:IN
AND
JZ
LOAD
OUT
LOAD
INC
STORE
LOAD
DEC
STORE
JNZ
LOAD
OUT

#200h
MemCnt
#F000h
MemDst
#8000h
FF00h
FF01h
#1
LOOP1
FF02h
(MemDst)
MemDst

;broja u MemCnt

;ako nije spreman, ekaj

;ulaz podatka
;i smetanje u memoriju
;auriranje pokazivaa

MemDst
MemCnt

;i brojaa

;adresa u MemDst
;Start=1, Enable=0, Direction=0
;pokreni kontroler
;ispitivanje bita spremnosti

MemCnt
LOOP1
#0
FF00h
Obrada
#200h
MemCnt
#F000h
MemSrc
#8002h
FF10h
FF11h
#1
LOOP2
(MemSrc)
FF12h
MemSrc

;auriranje pokazivaa

MemSrc
MemCnt

;i brojaa

MemCnt
LOOP2
#0
FF10h

;ako nije poslednji, ponovi

;zaustavi kontroler
;Stop PER1

;ako nije poslednji, ponovi

;zaustavi kontroler
;Stop PER0
;obrada
;broja u MemCnt
;pokaziva u MemSrc
;Start=1, Enable=0, Direction=1
;pokretanje kontrolera
;ispitivanje bita spremnosti
;ako nije spreman, ekaj
;podatak na izlaz

42 48

33.
16 8
/ . PER0, PER1 PER2 ,
: FF10h, FF11h, FF12h (PER0), FF20h, FF21h, FF22h (PER1) FF30h, FF31h,
FF32h (PER2). Start ,
Enable , 3 (1, 0).
Ready. :
PER0 PER1 100h
1000h (PER0) 1100h (PER1), Obrada
(CALL Obrada) 200h , 1000h PER2.
, Ready.

LOAD #1000h;pokretanje obe ulazne operacije

STORE MemB0
LOAD #1100h
STORE MemB1
LOAD #100h
STORE MemCnt0
STORE MemCnt1
LOAD #0
STORE MemSem0
STORE MemSem1
LOADB #89h
STOREB
FF10h
STOREB
FF20h
Wait0: LOAD MemSem0;ekanje na zavretak sa PER0
AND #1
JZ
Wait0
Wait1: LOAD MemSem1;ekanje na zavretak sa PER1
AND #1
JZ
Wait1
CALL Obrada ;obrada
LOAD #1000h ;izlazna operacija
STORE MemB
LOAD #200h
STORE MemCnt
LOADB #80h
STOREB
FF30h
Loop: LOADB FF31h
AND #80h
JZ
Loop
LOADB (MemB)
STOREB
FF32h

INC
MemB
DEC
MemCnt
JNZ
Loop
LOAD #0
STOREB
FF30h
:
Per0: PUSH
LOADB FF12h
STOREB
(MemB0)
INC
MemB0
DEC
MemCnt0
JNZ
Back0
LOAD #0
STOREB
FF10h
INC
STORE MemSem0
Back0: POP
RTI
Per1:

PUSH
LOADB FF22h
STOREB
(MemB1)
INC
MemB1
DEC
MemCnt1
JNZ
Back1
LOAD #0
STOREB
FF20h
INC
STORE MemSem1
Back1: POP
RTI

34.
, , PER0 PER1
16 16 . 16 .
IV (0 PER0, 1 PER1).
:
PER0_CONTROL
FF00h PER1_CONTROL
FF10h
PER0_STATUS
FF01h PER1_STATUS
FF11h
PER0_DATA
FF02h PER1_DATA
FF12h
0 Start , 1 (0-,
1-), 4 Enable , 0 Ready
. :
A(i) (i=0FF) PER0 1000h, B(i) (i=0,..FF) PER1
1100h, (B(i) = A(i) + B(i))
PER0. PER0 , PER1

43 48

, PER0 . PER0
.

Crdy:

Wait:

Loop:

LOAD #100h
STORE MemCnt0
STORE MemCnt1
LOAD #1000h
STORE MemAdr0
LOAD #1100h
STORE MemAdr1
LOAD #0
STORE MemSem0
LOAD #0 ; smer: ulaz
STORE MemDir0
LOAD #11h
OUT FF00h
LOAD #01h
OUT FF10h
IN FF11h
AND #01h
JZ Crdy
IN FF12h
STORE (MemAdr1)
INC MemAdr1
DEC MemCnt1
JNZ Crdy
LOAD #0
OUT FF10h
LOAD MemSem0
CMP #1
JNZ Wait
LOAD #100h
STORE MemCnt
LOAD #1000h
STORE MemA
LOAD #1100h
STORE MemB
LOAD (MemA)
ADD (MemB)
STORE (MemB)
INC MemA
INC MemB

DEC MemCnt
JNZ Loop
LOAD #100h
STORE MemCnt0
LOAD #1100h
STORE MemAdr0
LOAD #0
STORE MemSem0
LOAD #1
; smer: izlaz
STORE MemDir0
LOAD #13h
OUT FF00h

Wait1:LOAD MemSem0
CMP #1
JNZ Wait1
HALT
:
PUSH
LOAD MemDir0 ; koji smer?
CMP #1
JZ Out
; input
IN FF02h
STORE (MemAdr0)
Inc:
INC MemAdr0
DEC MemCnt0
JNZ Back
LOAD #1
STORE MemSem0
LOAD #0
OUT FF00h
JMP Back
;output
Out:
LOAD (MemAdr0)
OUT FF02h
JMP Inc
Back: POP
RTI

35.
, PER0 PER1,
16 16 . 16 .
.
PER0_CONTROL
FF00h PER1_CONTROL
FF10h
PER0_STATUS
FF01h PER1_STATUS
FF11h
PER0_DATA
FF02h PER1_DATA
FF12h
0 Start , 1 (0, 1), 2 Enable
. 4 Ready .
: (i), i = 0, , 999 PER0 2000h
(A(i)*A(i)) PER1. PER0 PER1 , .
PER1 . ,
.

44 48

:
LOAD #2000h
;poetna adresa ulaznog bafera
STORE MemWP
;pokaziva koji prati uitavanje sa PER0
STORE MemRP
;pokaziva koji prati slanje na PER1
LOAD #1000
;broj elemenata niza
STORE CntW
STORE CntR
LOAD #5
OUT
FF00h
;start PER0
LOAD #3
OUT
FF10h
;start PER1
Chck: IN
FF11h
AND #10h
JZ
Chck
;
LOAD MemWP
SUB
MemRP
JLE
Chck
;skok ako je rezultat oduzimanja =< 0
LOAD (MemRP)
MUL (MemRP)
;kvadriranje elementa niza
OUT
FF12h
;slanje rezultujueg elementa na PER1
INC
MemRP
DEC
CntR
JNZ
Chck
LOAD #0
OUT
FF10h
;Stop PER1
HALT
PER0:
Per1: PUSH
IN
FF02h
STORE (MemWP)
INC
MemWP
DEC
CntW
JNZ
Back
LOAD #0
OUT
FF00h
;Stop PER0
Back: POP
RTI

36.
16 /
. , , PER0, PER1 PER2 16
16 . 16 .
.
PER0_CONTROL
FF00h PER1_CONTROL
FF10h PER2_CONTROL
FF20h
PER0_STATUS
FF01h PER1_STATUS
FF11h PER2_STATUS
FF21h
PER0_DATA
FF02h PER1_DATA
FF12h PER2_DATA
FF22h
15 Start , 0 (0
, 1), 7 Enable , 0 Ready
. :
A(i) (i = 0, , 99) PER0 1000, B(i) (i = 0, , 99)
PER1 2000, C(i) (C(i) = A(i) + B(i), i = 0, , 99)
3000, C PER2.
C , . i- A(B) i- C
i- B(A). , C PER2 C
, . C PER2. PER0 PER1
, PER2 .

45 48

Wait:

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
AND
JZ
MOV
CMP
BLE
INC
MOV
CMP
JNZ
MOV
HALT

R0,
#-1
mcA, R0
mcB, R0
mwcC, R0
R1,
R0
;R1 is read pointer
FF00h, #8080h ;start PER0
FF10h, #8080h ;start PER1
FF20h, #8001h ;start PER2
R0,
FF21h ;read status
R0,
#1
Wait
R2,
mwcC
R2,
R1
Wait
R1
FF22h, (R1)3000
R1,
#99
Wait
FF20h, #0

PER0:
INTD
PUSH R0
PUSH R1
PUSH R2
MOV R0,
FF02h
MOV R1,
mcA
INC
R1
MOV mcA, R1
MOV (R1)1000,
R0
CMP
R1,
mcB
JG
SkipA
ADD R0,
(R1) 2000
MOV R2,
mwcC

INC
R2
MOV mwcC, R2
MOV
(R2) 3000,
R0
SkipA: CMP
R1,
#99
JNZ
BackA
MOV FF00h, #0
BackA: POP
R2
POP
R1
POP
R0
RTI
PER1:
INTD
PUSH R0
PUSH R1
PUSH R2
MOV R0,
FF12h
MOV R1,
mcB
INC
R1
MOV mcB, R1
MOV
(R1) 2000,
R0
CMP
R1,
mcA
JG
SkipB
ADD R0,
(R1) 1000
MOV R2,
mwcC
INC
R2
MOV mwcC, R2
MOV
(R2) 3000,
R0
SkipB: CMP
R1,
#99
JNZ
BackB
MOV FF10h, #0
BackB: POP
R2
POP
R1
POP
R0
RTI

46 48

37.
I/O 16 8
. ,
: Data (0026h, 0028h), Control (0030h, 0032h) Status (0020h, 0022h). 8 ,
. 2 Ready, 0 Start.
, Ready, ,
SUM1 SUM2. 0.
, .

LOOP:

TSTP2:

PER2:

PER1:

END:

MOV SUM1, #0
MOV SUM2, #0
OUT 30h, #1
OUT 32h, #1
IN R0, 20h
AND R0, #4
JNZ PER1
IN R0, 22h
AND R0, #4
JZ LOOP
IN R0, 28h
OR R0, R0
JZ END
ADD SUM2, R0
JMP LOOP
IN R0, 26h
OR R0, R0
JZ END
ADD SUM1, R0
JMP TSTP2
OUT 30h, #0;
OUT 32h, #0;

; Start PER1
; Start PER2
; Test PER1

; Test PER2

;Input from PER2

;Input from PER1

Stop PER1
Stop PER2

47 48

38.
/ , ,
PER0 (adrCR=FF10h, adrSR= FF11h, adrDR=FF12h), PER1 (adrCR=FF20h, adrSR=FF21h,
adrDR=FF22h) DMA1 (adrCR=FF00h, adrSR=FF01h, adrDR=FF02h,
adrCNT=FF03h, adrAs=FF04h, adrAd=FF05h) PER2 (adrCR=FF30h, adrSR=FF31h, adrDR=FF32h)
16 16 . 16
. 0 Start , 1
(0-, 1-), 2 Enable , 4 Ready
. 3 DMA (0-
(burst), 1- (cycle stealing)).
) . PER1
A(i) 80h 1000h DMA
burst , B(i) PER1
2000 DMA .
PER0 PER2,
A(i)/B(i), A(i)-B(i) (i=1, ..., 80h). PER0
, PER2 .
) PER1 A(i)
? .

:
) :
LOAD #0
STORE MemSem
STORE MemSem0
STORE MC0
STORE MC2
LOAD #80h
STORE FF03h
LOAD #1000h
STORE FF05h
STORE MAA0
STORE MAA2
LOAD #1h
STORE FF20h
LOAD #5h
STORE FF00h
Wait: LOAD MemSem
CMP #1
JNZ Wait
LOAD #0
STORE MemSem
LOAD #80h
STORE FF03h
LOAD #2000h
STORE FF05h
STORE MAB0
STORE MAB2
LOAD #1h
STORE FF20h
LOAD #13
STORE FF00h
Wait2: LOAD MemSem
CMP #1
JNZ Wait2
LOAD #3h
STORE FF30h
LOAD #7h

STORE FF10h
ChRd: LOAD FF31h
AND #10h
JZ ChRd
INTD
LOAD MC2
SUB MC0
JL Skip
LOAD (MAA2)
DIV (MAB2)
JMP IncMa
Skip:
LOAD (MAA2)
SUB (MAB2)
IncMa: STORE FF32h
INC MC2
INTE
INC MAA2
INC MAB2
LOAD MC2
CMP #80h
JNZ ChRd
LOAD #0h
STORE FF30h
...
ChPer0: LOAD MemSem0
CMP #1
JZ ChPer0
HALT
DMA_Int: PUSH
LOAD 0
STORE FF20h
STORE FF00h
INC
STORE MemSem
POP
RTI
PER0_Int:PUSH

48 48


LOAD MC0
SUB MC2
JL Skip0
LOAD (MAA0)
DIV (MAB0)
JMP IncMa0
Skip0: LOAD (MAA0)
SUB (MAB0)
IncMa0: STORE FF12h
INC MC0
INC MAA0

Back:

INC MAB2
LOAD MC0
CMP #80h
JNZ Back
LOAD #0h
STORE FF10h
INC
STORE MemSem0
POP
RTI

) . DMA

39.
, , PER0, PER1
PER2 DMA1 DMA2, ,
16 16 . 16 .
:
PER0_CONTROL
FF10h PER1_DATA
FF22h
PER0_STATUS
FF11h PER2_CONTROL
FF30h
PER0_DATA
FF12h PER2_STATUS
FF31h
PER1_CONTROL
FF20h PER2_DATA
FF32h
PER1_STATUS
FF21h
DMA1_CONTROL
FF00h DMA2_CONTROL
FF06h
DMA1_ADDRESS
FF01h DMA2_ADDRESS
FF07h
DMA1_COUNT
FF02h DMA2_COUNT
FF08h
DMA1_DATA
FF03h DMA2_DATA
FF09h
DMA1_STATUS
FF04h DMA2_STATUS
FF0Ah
0 Start , 1 (0-,
1-), 2 Enable , 4 Ready
. 3 DMA (0- (burst), 1-
(cycle stealin)).
. PER0 PER1 PER2.
BP0 BP1 PER0. ,
BP0 BP1 PER1 PER2 ,
BP1 BP0 PER1 PER2. 100h
BP0 BP1 1000h 1100h, . PER0
, PER1 DMA -- ,
PER2 DMA .

; initialize input from PER0 (fill BP0)

LOAD #0
STORE Mfin
LOAD #1000h
SOTRE Ain
LOAD #100h
STORE Cntin
LOAD #5
OUT FF10h
; ...
Wait1: LOAD Mfin
AND #1
JZ Wait1
; initialize output from BP0 and input to BP1
Swap: LOAD #1000h
STORE Aout
LOAD #1100h

STORE Ain
LOAD #1
STORE Dir
Init:
LOAD #0
STORE Mfin
STORE MFout1
STORE MFout2
LOAD #100
STORE Cntin
; init DMAs
LOAD Aout
OUT FF01h
OUT FF07h
LOAD #100h
OUT FF02h
OUT FF08h

49 48


; start controllers
LOAD #5
OUT FF10h
LOAD #Fh
OUT FF00h
LOAD #7
OUT FF06h
LOAD #3h
OUT FF20h
LOAD #3h
OUT FF30h
;
....
Wait2: LOAD Mfin
AND MFout1
AND MFout2
JZ Wait2
LOAD Dir
AND #1
JZ Swap
; initialize output from BP1 and input to BP0
LOAD #1100h
STORE Aout
LOAD #1000h
STORE Ain
LOAD #0
STORE Dir
JMP Init

DMA1Int:PUSH
LOAD #0
OUT FF20h
OUT FF00h
INC
STORE MFout1
POP
RTI
DMA2Int:PUSH
LOAD #0
OUT FF30h
OUT FF06h
INC
STORE MFout2
POP
RTI
Per0Int: PUSH
IN FF12h
STORE (Ain)
INC Ain
DEC Cntin
JNZ Back0
LOAD #0
OUT FF10h
INC
STORE MFin
Back0: POP
RTI

;stop PER0

40.
/ , ,
PER0, PER1, PER2 16 16 .
16 . :
PER0_CONTROL
F010h PER1_CONTROL
F020 PER2_CONTROL
F030h
PER0_STATUS
F011h PER1_STATUS
F021 PER2_STATUS
F031h
PER0_DATA
F012h PER1_DATA
F022 PER2_DATA
F032h

0 Start , 3
(0-, 1-), 7 Enable ,
15 Ready .
, IV 1 PER1 PER2.
PER2 PER1.
e PER0 a(i)
e PER1 PER2.
, 1000h, 100h .
PER0 , e PER1 PER2 .
, . PER0
, PER1 PER2 .

Wait:

MOV head, #1000h

MOV tail, #1000h
MOV cnt, #0h
AND IMR, #FFF9h
OUT F010h, #1
OUT F020h, #89h
OUT F030h, #89h
IN R0, F011h
AND R0, #8000h

50 57

JZ Wait
IN R0, F012h
INTD
MOV (head), R0
OR IMR, #6h
ADD head, #1
CMP head, 1100h
JNZ Skip0
MOV head, 1000h
Skip0: CMP cnt, #100h
JZ Tail0
ADD cnt, #1h
JMP Skip1
Tail0: ADD tail, #1h
CMP tail, #1100h
JNZ Skip1
MOV tail, 1000h
Skip1: INTE
JMP Wait
PER1 PER2:
INTD
PUSH R0
IN R0, F031h
AND R0, #8000h
JNZ Per2
Per1: OUT F022h, (tail)
JMP Tail1
Per2: OUT F032h, (tail)
Tail1: ADD tail, #1h
CMP tail, 1100h
JNZ Skip2
MOV tail, 1000h
Skip2: SUB cnt, #1h
JNZ Back
AND IMR, #FFF9h
Back: POP R0
INTE
RTI

41.
/ , ,
PER0 PER1 16 16 .
, SP .
PC. 16 . :
PER0_CONTROL
PER0_STATUS
PER0_DATA

F010h
F011h
F012h

PER1_CONTROL
PER1_STATUS
PER1_DATA

F020h
F021h
F022h

0 Start , 3
(0-, 1-), 7 Enable , 15 Ready
.
) PER0 a(i)
PER1. FIFO (First In First Out
, ) .
(: void transferData(void * buffer, int size);).
: struct IOStruct {void* buffer; int size; int dir; int* memSem; };
PER0 , PER1 . PER0
, PER1 .
) 800h a PER0
PER1?

51 52

)
:
PUSH BP
MOV BP, SP
PUSH R0
PUSH R1
PUSH R2
MOV R0, struct0
MOV (R0)0h, (BP)2h; // buffer
MOV (R0)1h, (BP)3h; // size
MOV Full, #0h
MOV WrP, #0h
MOV R1, struct1
MOV (R1)0h, (BP)2h; // buffer
MOV (R1)1h, (BP)3h; // size
AND IMR, #FFFDh; //disabled PER1
MOV Empty, #1h
MOV RdP, #0h
MOV F010h, #1h
MOV F020h, #89h

;// start PER0

;// start PER1

Check0: TST F011h, #8000h

JZ Check0
Wait_for_Place: CMP Full, #1h
JZ Wait_for_Place; //wait(Full);
MOV R2, (R0)0h
ADD R2, WrP
MOV (R2), F012h
MOV Empty, #0h
OR IMR, #2h
;// enabled PER1
;WrP:=(WrP+1) mod bufferSize
ADD WrP, #1h
CMP WrP, (R0)1h
JNZ Skip0
MOV WrP, #0h
Skip0: INTD
CMP WrP, RdP
JNZ Skip1
MOV Full, #1h
Skip1: INTE
JMP Check0
MOV F010h, #0h
MOV F020h, #0h
POP R2
POP R1
POP R0
POP BP
RTS

PER1:
IntPER1:
PUSH R0
PUSH R1
PUSH R2
MOV R0, struct0
MOV R1, struct1
MOV R2, (R1)0h
ADD R2, RdP

52 52

MOV F022h, (R2)

MOV Full, #0h
;RdP:=(RdP+1) mod bufferSize
ADD RdP, #1h
CMP RdP, (R1)1h
JNZ Skip2
MOV RdP, #0h
Skip2: CMP RdP, WrP
JNZ Back
MOV Empty, #1h
AND IMR, #FFFDh; //disabled PER1
Back: POP R2
POP R1
POP R0
RTI
) 800h

42.
/ , ,
PER0, PER1 PER2 16 16 .
, SP .
PC. 16 . :
PER0_CONTROL
PER0_STATUS
PER0_DATA

F010h
F011h
F012h

PER1_CONTROL
PER1_STATUS
PER1_DATA

F020
F021
F022

PER1_CONTROL
PER1_STATUS
PER1_DATA

F030h
F031h
F032h

0 Start , 3
(0-, 1-), 7 Enable , 15 Ready
.
PER0 num
a(i) PER1 PER2.
, . PER0 ,
PER1 , PER2
. PER0 , .
,
(: void transferData(void *buffer, int size, int num);).
: struct IOStruct {void* buffer; int size; int dir; int memSem; };

:
PUSH BP
MOV BP, SP
PUSH R0
PUSH R1
PUSH R2
PUSH R3
PUSH R4
MOV cnt0, #0h
MOV R0, struct0
MOV (R0)0h, (BP)2h; // buffer
MOV (R0)1h, (BP)3h; // size
MOV (R0)3h, 0h; // Sem0 = #0
MOV WrP, #0
MOV cnt1, #0h
MOV R1, struct1
MOV (R1)0h, (BP)2h; // buffer
MOV (R1)1h, (BP)3h; // size
MOV (R1)3h, 0h; // Sem1 = #0
AND IMR, #FFFDh; //disabled PER1
MOV RdP, #0h

53 52


MOV cnt2, #0h
MOV R2, struct2
MOV (R2)0h, (BP)2h;
MOV (R2)1h, (BP)3h;
MOV (R2)3h, 0h;
AND IMR, #FFFBh;

// buffer
// size
// Sem2 = #0
//disabled PER2

MOV cnt, #0h

MOV cntx, #0h
MOV num, (BP)4h
OUT F010h, #1h ;
OUT F020h, #89h;
OUT F030h, #89h;

//start PER0
//start PER1
//start PER2

Check0: IN R4, F011h

AND R4, #8000h
JZ Check0
Wait_for_Place: CMP (R0)1h, cnt
JZ Wait_for_Place;
INTD
MOV R3, (R0)0h
ADD R3, WrP
IN (R3), F012h
ADD cnt, #1h
ADD cnt0, #1h
OR IMR, #6h; //enabled PER1, enabled PER2
;WrP:=(WrP+1) mod bufferSize
ADD WrP, #1h
CMP WrP, (R0)1h
JNZ Skip0
MOV WrP, #0h
Skip0: INTE
CMP num, cnt0h
JNZ Check0
OUT F010h, #0h
Wait1: CMP (R1)3h, #1h
JNZ Wait1
Wait2: CMP (R2)3h, #1h
JNZ Wait2
POP R4
POP R3
POP R2
POP R1
POP R0
POP BP
RTS
Prekidna rutina za PER1:
IntPER1:
PUSH R0
PUSH R1
PUSH R2
MOV R0, struct2
MOV R1, struct1
MOV R2, (R1)0h
ADD R2, RdP
OUT F022h, (R2)

54 52

INTD
SUB cnt, #1h
ADD cnt1, #1h
ADD cntx, #1h
;RdP:=(RdP+1) mod bufferSize
ADD RdP, #1h
CMP RdP, (R1)1h
JNZ Skip1
MOV RdP, #0h
Skip1: CMP num, cntx
JNZ Ret1
OUT F020h, #0h
MOV (R1)3h, #1h
OUT F030h, #0h
MOV (R0)3h, #1h
JMP Back1
Ret1: CMP cnt, #0h
JNZ Back1
AND IMR, #FFF9h;
Back1: POP R2
POP R1
POP R0
RTI
Prekidna rutina za PER2:
IntPER2:
PUSH R0
PUSH R1
PUSH R2
MOV R0, struct1
MOV R1, struct2

Rol2:

INTD
;WrP:=(WrP -1) mod bufferSize
CMP WrP, #0h
JN Rol2
SUB WrP, #1h
JMP Skip2
MOV WrP, (R1)3h

Skip2: MOV R2, (R1)0h

ADD R2, WrP
OUT F032h, (R2)
SUB cnt, #1h
ADD cnt2, #1h
ADD cntx, #1h
CMP num, cntx
JNZ Ret2
OUT F020h, #0h
MOV (R1)3h, #1h
OUT F030h, #0h
MOV (R0)3h, #1h
JMP Back2
Ret2: CMP cnt, #0h
JNZ Back2
AND IMR, #FFF9h;
Back2: POP R2
POP R1
POP R0
RTI

Copyright 2012

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