designfeature By Alan Elbanhawy, Fairchild Semiconductor Corp

AS POWER-SUPPLY SIZE AND PERFORMANCE DEMANDS

INCREASE, SELECTING THE RIGHT SWITCHING DEVICES
BECOMES MORE COMPLEX. A STRAIGHTFORWARD METHOD
SIMPLIFIES THE SELECTION PROCESS, SPEEDS YOUR DEVELOPMENT, AND HELPS YOU TO OPTIMIZE YOUR DESIGN.

A simple guide to selecting

power MOSFETs
iven the wide selection of MOSFETs available of 1.5V, resulting in a duty cycle D for Q1 of
now and the shrinking real estate allotted for 1.5/1250.125 and 12D for the synchronous rectimotherboard power supplies, its increasingly fier Q2. Switching losses dominate the power dissiimportant to use a dependable, consistent method pation in Q1, owing to its relatively small duty cycle
for selecting the right MOSFET. Such a method can compared with that of Q2. Q1s voltage excursion is
speed development cycles while optimizing applica- the source voltage. Although Q2 must also stand off
the full supply voltage, at the beginning of its switchtion-specific designs.
PC-motherboard and power-supply designers, ing interval, the body diode clamps the filter inducwho frequently go through the power-MOSFET se- tor to ground, so Q2s excursion is limited to a diode
lection process, can benefit from an automated drop. The small duty cycle and large excursion put
process that uses a spreadsheet. This common tool demands on Q1s rise- and fall-time performance.
can significantly reduce the selection time while af- Conduction losses, which are a function of RON,
fording the designer an intimate, step-by-step look dominate Q2s power dissipation. Minimizing this
at the selection process. Compared with algorithmic ohmic term requires a device with the lowest on-reprogramming languages, implementing a selection sistance to handle the load current based on cost exmethod in a spreadsheet provides for greater inter- pectations and efficiency requirements.
action, easy fine-tuning, and simple provisions for
building and maintaining a parts database.
To limit the scope of this discussion, consider a
MOSFET-selection method for the synchronous
buck-converter topology, which suits dc/dc conQ1
verters for PC motherboards and telecommunications applications. The search for the right MOSFET
VP1
L
for a specific application involves minimizing the
losses and understanding of how these losses are dependent on the switching frequency, current, duty
cycle, and the switching rise and fall times. This information guides the selection tool development.
Q2
C
RL
Once you choose a topology, you can base the
MOSFET selection on its position in the circuit and
VP2
a few device parameters, such as breakdown voltage,
current-carrying capability, RON, and the RON
temperature coefficient. The goal is to miniFigure 1
mize conduction and switching and to
choose a device with adequate thermal properties.
Examining a typical buck converter reveals how The buck-converter topology uses two n-channel MOSFETs.
device requirements vary significantly depending on Q1 is the switching or control MOSFET, and Q2 is the syncircuit position (Figure 1). This circuit takes power chronous rectifier. L and C comprise the output filter, and RL
from a 12V source and provides an output voltage is the load resistance.

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November 22, 2001 | edn 87

designfeature Selecting power MOSFETs

The spreadsheet includes calculations
16
of static and dynamic losses, the latter of
which is the sum of switching and gatedrive losses. To facilitate the dynamic12
loss calculations, you need to refer to representative waveforms (Figure 2). Prior
to switching, the MOSFETs power dissipation derives from conduction losses.
8
The area under the blue triangle
Figure 2
depicts the dynamic loss during
the switching transition time, which oc4
curs twice per cycle. The total dynamic
loss, therefore, is proportional to the
switching frequency.
0
The conduction loss is proportional to
93.400US
the MOS devices on-state channel reID(M1)
sistance:
PC (Q1) = I2D1R ON1D,
2
PC (Q2 ) = ID
2R ON 2 (11D),

where ID is the drain current, RON is the

channel resistance at the manufacturers
specified nominal ambient temperature,
and D is the duty cycle of Q1.
Charging and discharging the gate capacitance contributes to the switching
losses. This loss also depends on the
switching frequency:
PG = VG2 CGS f ,

where VG is the gate-drive voltage, CGS is

the gate-source capacitance, and f is the
switching frequency.
THE UPS AND DOWNS OF MOSFET SELECTION
The requirements for the control
switch, Q1, and the synchronous rectifier, Q2, differ. Current, voltage, and power-dissipation ratings are key parameters
that determine the suitability of a device

for either position. Q1s power dissipation is given by:

P(Q1) = I2RMS R ON1D +
1

f QG1VG1 + (t r + t f )IRMS VS .
2

(1)

In Equation 1, the first term reflects

the conduction loss, and the second term
accounts for the dynamic and gate losses. IRMS is the drain current; RON is the
channel resistance; D is the duty cycle; f
is the switching frequency; tr and tf are the
switching rise and fall times, respectively; and VS is the input source voltage.
Similarly, Q2s power dissipation is given by:
P(Q2 ) = I2RMS R ON 2 (11D) +

f QG2 VG2 + (t r + t f )IRMS VD .

2

As in the previous case, the first term

is the conduction loss, and the second
TRACE THERMAL RESISTANCE
term is the switching loss. Note that D is
Q1s duty cycle. The last term, VD, is the
body-diode forward voltage. You
Figure 3
can reduce this loss and improve the
circuits switching dynamics by connecting a Schottky diode across Q2.
With the power dissipation calculated
for the two devices, you can calculate the
temperature rise from the thermal resistances of the package and heat sink as:

60
55
50
45
40
35
30
25
20
0

0.5

1.5

2.5

SQUARE INCH, 2-OZ COPPER

You can express the thermal resistance of a 2oz copper pc-board trace in degrees Celsius per
watt, as a function of the trace area. This thickness of copper is typical of most pc boards.

88 edn | November 22, 2001

93.500US

93.520US

Switching Q1 results in characteristic waveforms for ID (green) and VDS (red). The product of these
two waveforms gives the instantaneous power dissipation, PD, (blue).

and

8C/W

93.420US
93.440US
93.460US
93.480US
V(M1:d,M1:S)
ID(M1)*V(M1:d,M1:S)/8
TIME

T = R P,

(2)

where DT is the temperature rise over ambient in degrees Celsius, P is the devices
total power dissipation, and RQ is the total thermal resistance taken as the sum of

the junction-to-case resistance of the

FETs package and the heat-sink thermal
resistance. Theres also a small case-toheat-sink term, which is often negligibleparticularly when you use modern
thermal interface materials. The heat sink
can be an explicit mechanical device or
a pc-board trace with adequate surface
area (Figure 3).
Although these equations are simple
enough to allow a quick check of a given
MOSFETs suitability in a specific application, the strong dependency of RON on
the junction temperature somewhat
complicates the calculation. A temperature rise of about 808C causes a 40% increase in the value of RON. You need to include this behavior in the analysis of the
conduction losses to calculate the actual
temperature rise.
If you include the RONs temperature
coefficient in Equation 1, you get:
P(Q1 ) = I2RMS R ON1(1 + T )D + PD (Q1),

and
P(Q2 ) = I2RMSR ON1(1 + T )(11D) +
PD (Q2 ),

where d is the temperature coefficient of

RON in 8C-1, and PD is the dynamic loss
term, which is independent of RON.
When you substitute these variables
into Equation 2 and solve for the devices
DTs, you find that:
T (Q1) =

R [I2RMSR ON1D + PD (Q1)] (3)

,
1 R I2RMSR ON1D

and
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designfeature Selecting power MOSFETs

T (Q2 ) =
R [I2RMSR ON1(1 D) + PD (Q2 )]
1 R I2RMS R ON1(1 D)

(4)
.

Equation 4 provides the junctiontemperature rise as a function of the load

current and a specific set of MOSFET parameters. A junction temperature of
about 1058C is usually a good first cut for
commercial applications.
CALCULATING THE DYNAMIC LOSSES
The rise and fall times depend on characteristics of both the MOSFET and your
gate-drive circuit. The gate charge, QG, is
the product of the gate capacitance and
the drive voltage, usually given at 4.5V.
The gate capacitance combines with the
gate drives output impedance to limit the
gate rise and fall times:
1t

VG = VP 11e R PC G ,

V
t = 1R PCG ln 11 G ,
VP

and
t r = t f = 1R P

QG
V
ln 11 G .
VP
VP

(5)

In these equations,VG is the equivalent

gate voltage, VP is the gate-drive pulse
amplitude, RP is the gate-drive output impedance, and CG is the gate capacitance.
The MOSFET is fully on when VG
reaches 99% of VP. If you substitute this
relationship back into Equation 5, the
rise and fall times reduce to:
Q
t r = t f 4 .6 R P G .
VP
You can now calculate the total dynamic loss for each device:
1

PD (Q1) = f QG1VG1 + (t r + t f )IRMS VS ,

2

data sheet or from the dimensions of the

pc-board trace. Figure 3 shows the pcboard-trace thermal resistance of a single-layer pc board with 2-oz copper, versus a square copper area with the
MOSFET located in its center. Depending on the available pc-board area, the
copper can act as a heat sink for the
MOSFET. It is worth noting that for small
devices, increasing the area beyond the 2
square inches will not appreciably lower
the thermal resistance.
In a spreadsheet, compile a database of
MOSFETs suitable for your application.
For the synchronous rectifier, Q2, the
MOSFET must meet the voltage and current requirements of the application. It
must also have a sufficiently low RON, so
that the conduction loss is small enough
to meet the efficiency target. For this
MOSFET, the gate charge plays a secondary role in power dissipation.
For the control device, Q1, the dynamic or switching losses are the predominant factor, and conduction losses
play a secondary role. The MOSFET
should meet the voltage and current
specification with as low a gate charge as
possible to keep the dynamic losses
small. Secondarily, seek a device with a
moderate RON.
Solve equations 3 and 4 for the temperature rise for all the MOSFETs in the
database. Then you can select the MOSFET that meets your temperature-rise,
package, and price requirements. A
spreadsheet sheet that solves equations
3 and 4 for a selection of MOSFETs allows the simultaneous evaluation of
several MOSFETs. By using a spreadsheet this way, you can perform a whatif analysis to select the optimum MOSFETs for the application. You can adapt
this basic method to other topologies so
long as youve gained an understanding
of the conduction and switching-loss
requirements for each device in your
design.k

and
1

PD (Q2 ) = f QG2 VG2 + (t r + t f )IRMS VD ,

2

where VG is the gate drive for the referenced device.

COMPLETING THE DESIGN
Determine the thermal resistance of
the heat sink from the manufacturers

90 edn | November 22, 2001

Authors bio graphy

Alan Elbanhawy is senior staff engineer at
Fairchild Semiconductor International.
He has more than 30 years experience in
power-supply design and R&D management, covering aerospace, military, commercial, and industrial applications. He
holds a bachelor of science in electrical
engineering.
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