FinFET and Other New Transistor Tech Hu PDF

FinFET and other New
Transistor Technologies
Chenming Hu
Univ. of California
Chenming Hu, July 2011
May 4 2011 NY Times Front Page

NY Times news article:
Intel will use 3D FinFET for 22nm
Most radical change in decades
There is a competing SOI technology
Other Background Info

TSMC, IBMnew transistors soon
Since 2001 ITRS shows FinFET and
ultra-thin-body UTB-SOI as the two
successor MOSFETs
SOITEC UTB-SOI recently available
IBM 2009 5nm UTB SOI paper
New MOSFET Structures
Cylindrical FET
Ultra Thin Body SOI
Good Old MOSFET Nearing Limits

Vt, S (swing) and Ioff
are sensitive to Lg &
dopant variations.
high design cost
high Vdd, hence
high power usage
Finally painful enough for change.

Power Consumption Problems

1.Not just a chip and package thermal
issue.
2.ICs use a few % of worlds electricity
today and
Power per chip is growing.
IC units in use also growing.
3.If power consumption is not reduced,
industry future growth is at risk.
Want Low Vt and Low Ioff

Need smaller
S and less
variations of
S and Vt
How Vt Variation & S Got So Bad
Drain Current, IDS (A/m)
MOSFET becomes resistor at very

small L - Drain competes with Gate to
control the channel barrier.
L
Gate
Gate
10-3
10-5
Cg
Smaller
Size
shrink
size
or larger Vd
10-7
10-9
10-11
0.0
0.3
0.6
Insulator
Drain
Source
Cd
0.9
Gate Voltage, VGS (V)

Reducing EOT is Not Enough

Gate
Drain
Source
Leakage Path
Gate cannot control the

leakage current paths
that are far from the gate.
One of Two Ways to Better Vt and S
Source
The gate controls a thin body from

more than one side.
Gate Length
Gate
Drain
Source
Drain
Gate
FinFET body is a
thin fin
Fin Height
Fin Width
N. Lindert et al., DRC paper II.A.6, 2001
FinFET- 1999
Undoped Body. 30nm etched thin fin.
Vt set with gate work-function (SiGe).
0.6
Vt at 100 nA/m, Vd = 0.05 V
Vt [V]
0.4
0.2
0.0
-0.2
-0.4
Fin width: 20 nm
-0.6
0
10
20
30
Lg [nm]
X. Huang et al., IEDM, p. 67, 1999

40
50
State-of-the-Art FinFET on Buk Si

20nm Hi Perf
C.C. Wu et al.,
2010 IEDM
Gate
STI Si
STI
28nm SoC
C.C. Yeh et al.,
2010 IEDM
FinFET is Easy to Scale

10nm Lg AMD
2002 IEDM
5nm Lg TSMC
2004 VLSI Symp
3nm Lg KAIST
2006 VLSI Symp
Lg =
5 nm
because leakage is well suppressed if

Fin thickness =or< Lg
Thin fin can be made with the same Lg
patterning/etching tools.
Second Way to Better Vt and S
Ultra-thin-body SOI (UTB-SOI)

No leakage path far from the gate.
Drain Current [A/um]
1.E-02
Gate
Source
UTB
Drain
SiO2
Si
1.E-04
1.E-06
Tsi=8nm
Tsi=6nm
Tsi=4nm
1.E-08
1.E-10
1.E-12
Y-K. Choi, IEEE EDL, p. 254, 2000
0.2
0.4
0.6
0.8
Gate Voltage [V]

Most Leakage Flows >5nm Below Surface
Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000

Silicon Body Needs to be <Lg/3

For good swing and device variation
Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000

UTB-SOI
3nm Silicon Body, Raised S/D
Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001

State-of-the-Art 5nm
Thin-Body SOI
ETSOI, IBM
K. Cheng et al, IEDM, 2009
Both Thin-Body Transistors Provide

Better swing.
S & Vt less sensitive to Lg and Vd.
No random dopant fluctuation.
No impurity scattering.
Less surface scattering (lower Eeff).
Higher on-current and lower leakage

Lower Vdd and power consumption
Further scaling and lower cost
Back-Gate Bias Option

UTB-SOI
FinFET
Gate 1
Gate 2
Si
STI
STI
Similarities
1996: UC Berkeley proposed to DARPA two
25nm Transistors. Both of them
use body thickness as a new scaling parameter
can use undoped body for high and no RDF
1999: demonstrated FinFET
2000: demonstrated UTB-SOI (Ultra-Thin Body)
Since 2001: ITRS highlights FinFET and UTBSOI
Now: Intel will use Trigate FinFET.
Soitec readies +-0.5nm substrates for UTBSOI
Both FinFET & UTBSOI better than planar bulk!
Main Differences
FinFET body thickness ~ Lg. Investment by fabs
UTBSOI thickness ~1/3 Lg. Investment by Soitec
FinFET has clear long term scalability. UTBSOI
may be ready sooner depending on each firms
readiness with FinFET.
FinFET has larger Ion or can use lower Vdd.
UTBSOI has a good back-gate bias option.
UTBSOI
Gate 1
Gate 2
Si
FinFET
STI
STI
What May Happen

FinFET will be used at 22nm by Intel and later
by more firms through and beyond 10nm.
Some firms may use UTBSOI to gain/protect
market at 20 or 18nm if FinFET is not option.
If so, competition between FinFET and UTBSOI
will bring out the best of both.
If not----- back to first bullet.
FinFET BSIM Compact Model Verified

FinFET Fabricated at TSMC.
Lg = 30 nm-10um
Lg = 50nm
1
Vd = 50mV
25
1n
Vd = 1.2V
0
0.0
0.4
0.8
1p
1.2
Gate Voltage (V)
Id-Vd
Ibulk
1m
Lg = 50nm
100p
Vd = 1.2V
10p
1p
0.0
0.4
0.8
Drain Current (A)
Id-Vg
Bulk Current (A)
Drain Current (A)
50
1.2
Gate Voltage (V)
50 Lg = 50nm
Vg = 1.2 - 0.4V
Id-Vd
25
0
0.0
0.4
0.8
1.2
Drain Voltage (V)
M. Dunga, 2008 VLSI Tech Sym

Reduce C
f C Vdd
Reduce all capacitances.
30
Vacuum-Sheath Interconnect
CTOTAL Delay, CM Crosstalk Noise
Dielectric Beam
Load Capacitance : CO
Etch Stop layer
Mutual Capacitance : CM
Metal
Total Capacitance : CTOTAL

J. Park, Electronics Letters, p. 1294, 2009
Beam Dielectric Constant
Effective k of Vacuum-Sheath
Interconnects
2.25
1.6
2.9
2.0
3.3
1.7
2.1
2.3 2.2
2.4 No Solution
2.5
3.6
No Solution
2.6
3.9
1.9
1.8
1.5
1.4
1.3
20
30
40
50
60
70
80
Air Percentage (%)

J. Park, Electronics Letters, p. 1294, 2009
Vacuum Spacer to Reduce CGC
CGOX : Gate Oxide Capacitance
CGC : Gate-to-Contact Capacitance

CGOX CGC
CGOX < CGC

Contacts
Gate
Scale Down
Vacuum Spacer Self-Aligned Contact

20nm MOSFET comparison
Oxide
Spacer
Vacuum
Oxide
Vacuum
Spacer
Selfaligned
contact
(SAC)
Inverter
Delay, ps
6.15
(1)
5.05
(0.82)
Inverter
switching
energy, fJ
24.2
(1)
18.8
(0.78)
Relative
Area
0.7
J. Park, IEEE EDL, p.1368, 2009

Log Drain Current Id
Future Low Voltage Green Transistor
S<60mV/dec
S>60mV/dec
Gate Voltage Vg
35
How to reduce Vdd to 0.15V?

1.Reduce Vdd Vt to < 0.1V with highmobility-channel material, or subthreshold circuits.
2.
Reduce Vt to 50mV. Need a device

that is free of the 60mV/decade
turn-off limit.
Origin of the 60mV/decade Limit

VG
A potential
barrier controls
the electron flow.
COX
Ec
Ev
Source
Channel
Drain
Leakage current is determined by Boltzmann

distribution or 60 mV/decade, limiting MOSFET, bipolar,
graphene MOSFET
So, let electrons go through, not over, the

energy barrier semiconductor tunneling
or MEMS
Semiconductor Band-to-Band Tunneling:

EC
generating electron/hole pairs
EV
P-
N+
N+
A known mechanism of leakage current since

1985.
Called Gate Induce Drain Leakage (GIDL).
J. Chen, P. Ko, C. Hu, IEDM 1985
Green Transistor --Simulation

P+ Pocket
S
N+
C. Hu, 2008 VLSI-TSA, p.14, April, 2008
G
N-
P+
Buried Oxide
P+
Pocket
Gate
Hole flow
Electronband
flow diagram
Energy
N+ Source
P+ Drain
Simulated carrier generation rates
Abrupt turn-on due to over-lap of valence/conduction

bands; adjustable turn-on voltage.
Reduce Vdd by Reducing Eg

Simulated impact of Eg scaling
1E-02
Eg=0.36eV, Vdd=0.2V, EOT=5 , CV/I=0.42pS
1E-03
IDS (/m)
1E-04
1E-05
1E-06
Eg=0.69eV, Vdd=0.5V, EOT=7 , CV/I=2.2pS
1E-07
Eg=1.1eV, Vdd=1V, EOT=10 , CV/I=4.2pS
1E-08
1E-09
Eg=0.36eV
1E-10
Eg=0.69eV
Eg=1.1eV Lg=40nm
1E-11
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage, VGS (V)
Vdd scales down faster than Eg.

Simulated gFET Inverter VTC

Good voltage gain at 0.1V
200
VDD: 0.2 V
VDD: 0.15 V
Output Voltage, VOUT (mV)
150
VDD: 0.1 V
100
50
0
0
50
100
150
Input Voltage, VIN (mV)
200

Hetero-junction gFET
Strained Si on Ge has 0.18eV effective
tunneling Eg.
III-V.
Gate
N+ Drain
Si
EC offset
EV
Gate Oxide
P+ Source
EC
Gate
Ge Substrate
Ge tFET
Si-Ge HtFET
Si
Ge
A. Bowonder, Internl Workshop Junction Tech., 2008

Summary
FinFET and UTB-SOI are viable new
sub-22nm transistors.
Different performances, investment
costs, wafer costs, scaling barriers.
Their BSIM SPICE models are
available free
Capacitance and tunnel gFET are
potential opportunities.
43

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FinFET and other New

Chenming Hu, July 2011

May 4 2011 NY Times Front Page

Chenming Hu, July 2011

Other Background Info

Chenming Hu, July 2011

New MOSFET Structures

Chenming Hu, July 2011

Good Old MOSFET Nearing Limits

Finally painful enough for change.

Power Consumption Problems

Chenming Hu, July 2011

Want Low Vt and Low Ioff

Chenming Hu, July 2011

How Vt Variation & S Got So Bad

Drain Current, IDS (A/m)

MOSFET becomes resistor at very

Gate Voltage, VGS (V)

Reducing EOT is Not Enough

Gate cannot control the

One of Two Ways to Better Vt and S

The gate controls a thin body from

Chenming Hu, July 2011

X. Huang et al., IEDM, p. 67, 1999

State-of-the-Art FinFET on Buk Si

Chenming Hu, July 2011

FinFET is Easy to Scale

because leakage is well suppressed if

Second Way to Better Vt and S

Ultra-thin-body SOI (UTB-SOI)

Y-K. Choi, IEEE EDL, p. 254, 2000

Gate Voltage [V]

Most Leakage Flows >5nm Below Surface

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000

Silicon Body Needs to be <Lg/3

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000

3nm Silicon Body, Raised S/D

Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001

Chenming Hu, July 2011

Both Thin-Body Transistors Provide

Higher on-current and lower leakage

Back-Gate Bias Option

Chenming Hu, July 2011

What May Happen

Chenming Hu, July 2011

Chenming Hu, July 2011

FinFET BSIM Compact Model Verified

Gate Voltage (V)

Drain Current (A)

Bulk Current (A)

Drain Current (A)

Gate Voltage (V)

Drain Voltage (V)

M. Dunga, 2008 VLSI Tech Sym

Chenming Hu, July 2011

Chenming Hu, July 2011

Chenming Hu, July 2011

Chenming Hu, July 2011

Reduce all capacitances.

Chenming Hu, July 2011

Etch Stop layer

Total Capacitance : CTOTAL

Beam Dielectric Constant