OPERATOR'S MANUAL: 808 ANALOG SIGNAL PROCESSOR The 808 Analog Signet Processor is an analog conputer that can function a3 « stand~ Mone unit or operate with external accessories to mect a variety of instrumentation Gnd sinulseion applications. features internal to the 808 are described below. |The Eetuevings is 4 SEGC of exteinad sccesnories that expand computing capabiasties and operator functions MODEL 785 CONTROL UNIT- Conbines multiple 808 units into a single operating systen. Tneludes a 8 1/2 digit digital voltneter and central address for setting attenuacors and readout of amplifier outputs, Ineludes a push button slow tine and repetitive Spezotion node, coperolfo,operste conbined s0s|s fs/s, general putposs analog simula. Gen’systen. Rack mountable ina full wideR, $-1/2" high panel space WoDEL. 731 ATTENUATOR GROUP- Adds seven attenuators each having @ push button coef Welene setting suitehs Rack mountable inva half width, 31/2" high panel space. WoDst, 709 VDFG- An eleven segment, variable siope, variable breakpoint diode fonction generator’ “Rack mountable in a helf width, 31/2" high panel space MODEL, 727 THREE MODE CONTROLLER- Provides the proportional, rate and reset control Rhetion for simulation and on-line applications. Rack noultable in a half width, ST/2""high panel. space. BANANA PLUG MOBULES- A variety of switch and non-linear functions are available. Nodules plug directiy into the 808 patch panel fecks: DESCRIPTION OF 808 INTERNAL FEATURES 1.0 aMp/Por ADDRESS ‘The Aup/Pot AdGress switch 1s an 11 position, 2 pole rotary switch. One section Teste Goptttler cutputs for externas) readoit; the other section selects coef Helene potentioncter outputs for setting attonuator constants. The amplifier se- Eieigrt diver Ls connected! to the Amplifier Readout bus; the potentioneter selector iS tgnnebad t2 the Potentioneter Readout Bus- 4.1 MODE SELECTOR ‘The Mode Selector switch is a 2 position, 12 pole rotary switch. It provides @ nun- Bee Of functions that distinguish the computer's Pot Set and Operate nodes 1.1.1 Setting of Coefficient Potentioneters ‘The'tap end Iaput-toveach coerrictent potentiometer is connected to one of six poles.” in the OFR position the poles are svitched to the patch panel input; in RRe'por SET position the poles are switched to positive reference, Thus in the Pot Set mode the inputs to all potentioueters are replaced by positive reference and the potentioncter output Veluss are neasurenents of voltage divider ratios. 1.1.2_Integrator Node Control Bae fore Tetconmected to the Node Control gvitch pole. Tp the POT S27 position the pole’ is switched to ground; in the OPR position the pole Ls switched to’ the OP FEtch panat jacket” Hise in the Roc’ Sectaode sit thclgrscors are placed, late an initial condition; in tho operate node Integrators are controlled by the OF node control logic: 1.1.5 External_Readout Meter bag gore ds Connected tothe Readout Meter Bus. In che POT, SET position, the pole is Ghitehed to the Potentioneter leadout bus; in the GPR position the pole is switched fo the Aupitfier Readout Bus. 11.4 Mold Tonibit EREHOMTT Tnbagrator initial condition mode the hold suitch is shut off, chereby Holating the input resistor network. It is necescary, however, to. set potentio~ eters with theif resistor loads contected.. Therefore, during the Pot Set node each Jncegrator hold guiteh is inhibited; it is held in an “on” condition and the resis~ Ege Betwork summing junction ie ground potentiel. A separate hold inhibit logic Efrcule"Ts round of the quad amplifier assembly.” 4 posicive Logic input enables the fold suite to operate normaliy: @ negative input inhibits the switch. This one Role of the Moge Selector switch 1s connected to the Hold Inhabit Bus. In the POT Bit‘position ‘the pole ir connected to negative 10 volts; In the OPR the pole is svitehed to positive referenc COMDIAL, tne.OPERATOR'S: MA 1.2 MODE CONTROL The Mode Control svitch is a single polo, double throw, center off cogsle switeh That produces logic levels to operate thé 80 integrator mode svitches. when the Mods Selector switch is in the OPR position the pole is cuniected to the pucch panel OP Sus, The OP Bus has three states. Ground or a positive volsage places integra: fors hte the Initial Condition sede. Ai-s or more’ negative voltage’ places integra~ tors inte the Oporate mode, A voltage level between “1.5 and -3.5 volts places the tegrators into tho Hold node. In the "KC" position the pole is switched to ground. Im the "OP" position the pole is switched fo the Mode Control Bus. (Tho bus 1s pulled to the Operate nede Level, by a°22K resistor connected to -10 volts. For external mode control the Node Con- Bol guiteh is placed into the "OP" position and the Mode Control Bus ts pulled to round and/or the Hold node level.) "ta the "il" position the Node Control Bus 43. Pulled tg the Hold mode level through a Ik resistor that is connected from the pote fo groun 41.3. COEFFICIENT POTENTIONETERS ‘The covgficient potentioneters are ten turn, SK ohm variable resistors arranged as Tttenustors with’eheir potton ends grounded: Procedures for setting covfficients Sre'Tisted as fo1lona? 1. Goetfictents are set after all patching is completed EL Position the Node Selector suiteh te Por Se 5) Position the Aup/Pot Address switch to the number of the potentioneter to be set, 4, Connects digital voltmeter to the Readout Motor Bus found in the rear ‘Feunk and Readout Connector. 5. Mjust'the potentioneter until the desired setting 4s observed. 1.4 OVERLOAD INDICATOR ‘The "OVLD" lamp is a light alarm that indicates when one oF more of the eight patch pene! aupiisie? gurputs*exceed either positive oF nogacive 10 voits reterenee. 1.5 POWER Power is on when the POWER toggle switch is in the up posicion. 1.6 PATCH PANEL Patch panel operations are described in a separate patching section 1.7, TRUNK AND READOUT CONNECTOR A twenty-five pin rack and panel connector found st the rear on the $08 unte pre- Vides convenient input/output connections. The following 1: 2 description of pia Connections. (\unbers are left to right, top to totton facing the unit's rear) Description eo, eseription Teunk 4 (pacah panel fe anel Fick) TEE ae Noon atsplay paver (160 yolts) * Trunk 3 {patch panel jack) 15, Vee'Logic power (+5 volts) * EEURE 2 fpaeeh panel j2ch) Is: NE ‘Trunk I (patch panel Jack) i xe ‘ine scale Relay * baal Node Contfol Bus, see para. 1.2 19. NC Meter Readout Bus, see'pard. i-1.3° 20) NC mplifier Readout Bus, seo pare io 21. NC Syaten Ground 22! Trunk § (patch panel jack) SYo"Foues Reference 38. Trunk 7 (paten panel Jack) Sib Volts Refe 2! Trunk 6 (patch panel Jack) Ug voles 8, Trunk § (patch panel Jack) SIS vores 4 Included only when. Condyna digital yoltaeter is supplied F when the quad anpiifier beards have the tise scale relay. pvovision, -18 volts Connected tothe Tine Scale Relay termination will enersize the relay. Th the onergized state integrators are in a slow time condition: is the Ja-energized State integrators are ine high speed condition COMDIMA, ne.808 SYSTEM SCHEMATIC syeten Seoine——— lI wig sRT ene? oe ee HS volt Suppiy: Eran 6 Trunk 14 Readout Connsetar Tayout of G08 Assenbiles —— —— mpitier sesdout Bus —— irter Readout Bus ———= Nose ‘control Bus SS Hise Senie Relay esa Teun 2 ‘Trani 3 — trunk 1 ‘Trunk and Readout Comector = 2 kg 1 amp Fuse 116-2. Power Supply — 962) Dua tur tipi ier Networks —hareter strip [sti =2 Guad Amplifier Assemblies input Resistor Networks a oe fad Indloater Input gunning resistors for integra tof and susmer amplifiers are located fon the Resistor Network Boarés. Re" Sistore are f.00K and $0.0k ok, metal film, 0.18 Color coding of pover wiring is: sI5y"sReds “130. “White; 10V “Yellow; *i0V"-Ofange; wiring Schematic mere Reacour Bus AupLIRIER READOUT BUS Potentioneter Paton Panel Wipers 2) AMWP/POT ADDRESS NODE SELECTOP MODE CoNTROL pein can Posi) ince Sete Recay Potentione ter Pateh 5 COBFPICIEND POTENTIONBTERSee 8 3 72 Y os Ble * A oo Le | I Niagram Assembly Drawing€.2.8 MODEL 082 DUAL MULTIPLIER ADJUSTMENT (For Serial Now, 1142) For GP-& computers of serial numbers greater than 114, the Model 982 Dual Multiplier ind readjusted. 'necensnry, during the computer's initia checkout Thereafter, the fctwork should be periedwcaliy checked to sumure its mont accurate operation. About 1020 minstes should be allowed for warm-up before adjusting oF checking Let Hand Multiplier Network Right Hand Multiplier Network Adjustment consiate of zero offect balancing and trim for gain and neariy. The sup ested procedure for adjustment Ie 1 With the patch panel terminations X and ¥ patched to ground, adjust potentiometer Zelahown in Fig. C.2-Bol) for 8 sero output Program an integrator to sweep from minus to plus reference. For convenience, place the GP-6 into the repetitive operation mode, Display the ramp ve the multiplier out= put. Patch the ramp to the Y input, the X input should remain patched to ground, Ad. [fst the Ce potentiometer ania beat sero curve in obtained. Reverse the X and ¥ iapat connections. Adjust the potentiometer Yo until «best zero carve ta obta Patch Reference to the X oput andthe ramp to the ¥ Input, Sum the multiplier output swith the correct polarity of the ramp to that an error curve in obtained. Adjust the Potentiometsr Ga until the beet error curve ie obtained, Revares the X and Y inpate pa eee tena ele eleanor chorea ‘Trim potentiometer Gx ao tht the best srror curve forOPERATOR'S MANUAL: 3.10 THE MODEL 701 VARIABLE DIODE FUNCTION GENERATOR ‘The Medel 701 VDFG is programmed as an Input network, FOr operation, it must be cone ected to the summing junction of an operational ampliGier. When the feedback ofthis Amplifier is 2 zesietor, such as shown in Fig. B.10-1, the YDFG fonction appears ar ite utput, For a detailed discussion of diode function generation, see Chapter 12 of the "GP-6 Analog Simulation and Computation Programming Manual repatx o [TE Fos Positive Reference QT Negative Reference Q—4 ‘The following procedures may be used for setting function 1, Construct an output/inpst plot of the function to be set. ‘The curve should be drawn ‘on graph paper with full scale co-tedinates relating to computer reference, 2. Connect computer reference to the "and "=" jacks found on the VDFG panel, 3. Connect the VDFG to the summing junction az shown Sn Fig. B. 10-1 4, Connect a ramp that aweepe from negative reference to positive reference as the VDFG Input. (The GP-6 computer Lime base may be Weed es this input ramp.) 5, Set up of the VDFG is eaclest When the computer is in the repetitive operation mode pd the function is displayed on an oscilloscope. Setting in the slow time mode may Ie ei fee eye cep a Input. The eleven segments will be presented in a manner similay to that shown Center Stope Punetion ‘Output Parallax Fig, 3.10.2 GTead nd ee jectoa Up TaES—a recente — Negative Inpite © Positive Inpte FT 6. To seta function, first vary the "Parallax adjustment until the function intersects the Y ania at the desired position 1. Next, tot the "Slope! adjotmest to the desiced center slope. The center slope ex- tends from -1 volt to +1 volt input 8. Adjust individual slopes until the desired function is dieplayed, Individual bres point slope adjustments should be set in numeric aequence from the origin, 9. Replace the ramp with the desired program inpit It is noted that an overload condition of the output amplifier will aifect set up, I this amplifier overloads during + repetitive operation set up, it will be necessary to readjust the function when the overload condition ie removed ‘The output amplifier feedback resistor controls the gain of function adjustments, The range of individual slopes may be increased by raising the resistor value. Slopes may iso be increased by placing # co-eificient potentiometer in series with the amplifier ‘utput and the feodbuck resistor. In this case, adjustment gains ore increased by the ‘reciprocal of the potentiometer setting.