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AVSP-4412 100G Retimer

Bidirectional 4x28G

Product Brief

Description

Features

To meet the demand for data buffering at 100G and beyond, Avago leverages its industry-leading 28nm CMOS
SerDes technology, with its unique Decision Feedback
Equalization (DFE) architecture, to create the Vortex Signal
Integrity family.

Full-duplex quad retimer from 1 to 28 Gbps


Supports backplane interface defined in CEI-25G-LR
Supports chip-to-chip and chip-to-module interfaces
defined in CEI-28G-SR and VSR
Supports MDIO Interface (IEEE 802.3-2012 Clause 45)
Supports KR backchannel (IEEE 802.3 Clause 72)
Programmable Tx: amplitude, de-emphasis main, pre
and post-cursor
Programmable and adaptive Tx equalization: CTLE +
13 tap DFE
Integrated blocking caps at Rx
Diagnostics: pattern generator (PRBS and user defined),
error detector, eye monitor, temperature sensor, input
and output polarity swapping
Protocol agnostic
32dB reach at 25G
BER =1017
Self-loading of firmware and initialization settings from
EEPROM
Up to 16 retimers per I2C bus
Power supply: 1V and 2.5V (0.9V optional)
11x11 BGA: 12 x 12 mm package with 1mm pitch
Operating junction temperature: 0 to 125 C
Integrated API facilitates seamless software integration

The AVSP-4412, a protocol-agnostic, low power, quad 28G


bidirectional retimer, is suitable for both backplane and
port side applications. With this device, Avago offers data
center, enterprise, and OTN switch and router manufacturers best-in-class jitter, crosstalk, and reach. The embedded backchannel allows for automatic link training such
that the Rx and Tx of each channel can be optimized without simulation or system validation to determine the best
EQ settings.
The AVSP-4412 features test and channel analysis capabilities such as pattern generation, eye capture, and error
detection. The user can control the device via MDIO, I2C,
or JTAG, and the Avago-provided API facilitates seamless
software integration.

Block Diagram

Rx

28G Tx/Rx SerDes slice 7


28G Tx/Rx SerDes slice 6
28G Tx/Rx SerDes slice 5
28G Tx/Rx SerDes slice 4

Tx

28G Tx/Rx SerDes slice 3


28G Tx/Rx SerDes slice 2
28G Tx/Rx SerDes slice 1
28G Tx/Rx SerDes slice 0

Tx

Rx

SBus Ring

JTAG

JTAG (TAP)
Controller

SBus Control
Spico Interface

MDIO/I2C
Interface
MDIO or I2C

Figure 1. AVSP-4412 Block Diagram

Applications
The AVSP-4412 is used in backplanes as well as in port side
applications where it is placed in front of optical modules
(CFP2, CFP4, QSFP28) or direct-attach copper cables.

Application diagram
8
ASIC

8801
8801

4412

4
ASIC

4412

Switch

Backplane
Figure 2. AVSP-4412 Functional Diagram

4412

QSFP28

4412

CFP4

4412

CFP2

Line Card

Compliant with the following:


CEI-11G-SR/MR/LR, CEI-28G-VSR, CEI-25G-LR
XAUI, XLAUI, CAUI-4 and CAUI-10
100GBASE-CR4/KR4/SR4/LR4/ER4
100GBASE-CR10/SR10
40GBASE-CR4/KR4/SR4/LR4
10GBASE-KR/CR/SR/LR/ER
OTU4.4 and 4.10 data rates

Performance

Figure 3a. 25G Eye diagram from AVSP-4412 eye monitor


after 1m backplane

Figure 3b. 25G Eye diagram from AVSP-4412 eye monitor


after 5m 26AWG copper cable

Link Training (IEEE-802.3ba Clause 72)


ASIC

AVSP-4412

ASIC
A

SerDes 07

Tx

Serial data

Rx

Parallel data

Tx

Tx equalization
(Manchester encoding)

Rx

Serial data

Tx

Parallel data

Rx

Serial data

Rx

Serial data

Tx

SerDes 3

AVSP-4412 features backchannel communication


paths between SerDes to support Link Training
(IEEE-802.3ba Clause 72).
In addition to the SerDes 07 and SerDes 03 backchannel illustrated in Figure 4, there are three
other backchannels comprised of the remaining
six SerDes.
When Link Training is requested, the AVSP-4412
will negotiate optimum Tx and Rx settings with
the remote ASIC.

ASIC Rx <=> 07 Tx to train channel A-A: the backchannel path follows ASIC Rx ASIC Tx 15 Rx 15 Tx
15 Rx <=> ASIC Tx to train channel B-B: the backchannel path follows 15 Rx 07 Tx ASIC Rx ASIC Tx

Figure 4. Link Training Data Flow

For product information and a complete list of distributors, please go to our web site:

www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2014 Avago Technologies. All rights reserved.
AV02-4416EN - February 25, 2014