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Bidirectional 4x28G
Product Brief
Description
Features
To meet the demand for data buffering at 100G and beyond, Avago leverages its industry-leading 28nm CMOS
SerDes technology, with its unique Decision Feedback
Equalization (DFE) architecture, to create the Vortex Signal
Integrity family.
Block Diagram
Rx
Tx
Tx
Rx
SBus Ring
JTAG
JTAG (TAP)
Controller
SBus Control
Spico Interface
MDIO/I2C
Interface
MDIO or I2C
Applications
The AVSP-4412 is used in backplanes as well as in port side
applications where it is placed in front of optical modules
(CFP2, CFP4, QSFP28) or direct-attach copper cables.
Application diagram
8
ASIC
8801
8801
4412
4
ASIC
4412
Switch
Backplane
Figure 2. AVSP-4412 Functional Diagram
4412
QSFP28
4412
CFP4
4412
CFP2
Line Card
Performance
AVSP-4412
ASIC
A
SerDes 07
Tx
Serial data
Rx
Parallel data
Tx
Tx equalization
(Manchester encoding)
Rx
Serial data
Tx
Parallel data
Rx
Serial data
Rx
Serial data
Tx
SerDes 3
ASIC Rx <=> 07 Tx to train channel A-A: the backchannel path follows ASIC Rx ASIC Tx 15 Rx 15 Tx
15 Rx <=> ASIC Tx to train channel B-B: the backchannel path follows 15 Rx 07 Tx ASIC Rx ASIC Tx
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2014 Avago Technologies. All rights reserved.
AV02-4416EN - February 25, 2014