es MAHI Digital Systems US OTA TU LTT Synthesis An Integrated Approach Pe eSCie til rio SOCIETYDigital Systems Design with VHDL and Synthesis: An Integrated Approach wo K.C. Chang BD COMPUTER SOCIETY Los Alamitos, California Washington ® Brussels ® Tokyo}9 Chang} K, C. (Kou-Chuan), 1957 — al systems design with VHOL and eynthesis : an integrated tronic digital computers — Circuits — Design and construction — Data processing. 2. VHDL (Hardware description language). 3. System design - Data processing. |. Title. K7688.4.C435 1999 621.39'2—de21 gu js1ao Wet CW ‘Copyright © 1999 by The Institute of Electrical and Electronics Engineers, inc. All rights reserved, Copyright and Reprint Permissions: Abstracting is permitted with credit t0 the source. Libraries are permitted to photocopy isolated pages beyond the limits of US copyright law, for private use of their patrons, Other Lopying, reprint. or republication requests should be addressed to: IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. IEEE Computer Society Press Order Number BP00023 Library of Congress Number 99-24750 ISBN 0-7695-0023-4 Addiionol copies may be ordered from: IEEE Computer Society Press IEEE Service Center IEEE Computer Society Customer Service Center 445 Hoes Lane Watanabe Building 10662 Los Vaqueros Circle P.O. Bex 1331 1-4-2 Minami-Aoyama P.O. Box 3014 Piscataway, NJ 08855-!331 Minato-ku, Tokyo 107-0062 + Los Alamitos, CA 90720-1314 Tel: +1-732.981-0060 JAPAN Tel: +1-714-821-8380 Fax: +1-732-981-967 Tel: +81-3.3408-3118 Fas: +1-714-821-4641 miscustserv@ computer org Fax: +81-3.3408-3553, ex ooks@ computer.org tokyo ofe@computer.ong Publisher: Matt Loeb Manager of Production, CS Press: Deborah Plummer Advertising/Promotions: Tom Fink Production Editor: Denise Hurst Printed in the United States of America oD) COMPUTER @ SOCIETY exe 549 Y 999609. 004Dedicated to my parents, Chia-Shia and Jin-Swei, my wife, Tsai-Wei, and my children, Alan, Steven, and JocelynPreface The advance of very large-scale integration (VLSI) process technologies has made “system on a chip” a feasible goal for even the most complex system. The market has demanded shorter design cycles than ever before, while design complexity continues to increase, Traditional schematic capture design approaches are no longer sufficient to be competitive in the industry. New design processes and methodologies are required to design much more complex systems within a shorter design cycle. Fur- thermore, the gap between the design concept and implementation must be mini- mized. The goal of this book is to introduce an integrated approach to digital design principles, process, and implementation. This is accomplished by presenting the digi- tal design concepts and principles, VHDL coding, VHDL simulation, synthesis com- mands, and strategies together. Itis the author’s belief that it is better to learn digital design concepts and princi- ples together with the high-level design language, verification, and synthesis. Over- looking key digital design concepts will result in inefficient designs that don’t meet performance requirements. Without the high level design language, the design con- cepts cannot be captured fast enough. Lacking the verification techniques results in a design with errors. Not knowing the synthesis strategy and methodology does not allow the design to be synthesized with the desired results. Therefore, an integrated approach to design concepts, principles, VHDL coding, verification, and synthesis is crucial. To accomplish this in a book is challenging since there are so many potential combinations of design concepts with techniques for VHDL coding, verification, and synthesis. The author has approached this challenge by focusing on the ultimate end products of the design cycle: the implementation of a digital design. VHDL code con- ventions, synthesis methodologies, and verification techniques are presented as tools to support the final design implementation. By taking this approach, readers will be taught to apply and adapt techniques for VHDL coding, verification, and synthesis to various situations. To minimize the gap between design concepts and implementation, design con- cepts are introduced first. VHDL code is presented and explained line by line to cap- ture the logic behind the design concepts. The VHDL code is then verified using VHDL test benches and simulation tools. Simulation waveforms are shown and explained to verify the correctness of the design. The same VHDL code is synthe- sized, Synthesis commands and strategies are presented and discussed. Synthesized schematics and results are analyzed for area and timing. Variations on the design tech- niques and common mistakes are also addressed. This book is the result of the author’s practical experience as both a designer and an instructor. Many of the design techniques and design considerations illustrated throughout the chapters are examples of viable designs. The author’s teaching experi-vi Preface ence has led to a step-by-step presentation that addresses common mistakes and hard- to-understand concepts in a way that makes learning easier. Practical design concepts and examples are presented with VHDL code, simula- tion waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships. Unique features of the book include the fol- lowing: 1. More than 207 complete examples of 14,099 lines of VHDL code are devel- oped. Every line of VHDL code is analyzed, simulated, and synthesized with simulation waveforms and schematics shown and explained. VHDL codes, simulation waveforms, and schematics are shown together, allowing readers to grasp the concepts in the context of the entire process. 2. Every line of VHDL code has an associated line number for easy reference and discussion. The Courier font is used for the VHDL code portion because each character of this font occupies the same width, which allows them to line up vertically. This is close to how an American Standard Code for Information Interchange (ASC file appears when readers type in their VHDL code with any text editor. 3. The VHDL code examples are carefully designed to illustrate various VHDL constructs, features, practical design considerations, and techniques for the particular design. The examples are complete so that readers can assimilate overall ideas more easily. . Challenging exercises are provided at the end of each chapter so that readers can put into practice the ideas and information offered in the chapter. . A complete Finite Impulse Response filter (700K+ transistors) ASIC design project from concept, VHDL coding, verification, synthesis, layout, to final timing verification is provided 10 demonstrate the entire semi-custom stan- dard cell design process. 6. A complete microcontroller (AM?2910) design project from concept, VHDL coding, verification, synthesis, to release to a gate array vendor for layout, to final postlayout timing verification with test vector generation is used to demonstrate the entire gate array application-specific integrated circuit (ASIC) design process . A complete error correction and detection circuit (TI SNS4ALS616) design is taken from concept, VHDL coding, verification, synthesis, to a field pro- grammable gate array (FPGA) implementation. . Synthesis commands and strategies are presented and discussed for various design situations. . Basic digital design circuits of counters, shifters, adders, multipliers, divid- ers, and floating-point arithmetic are discussed with complete VHDL exam- ples, verification, and synthesis, 10. Test benches VHDL coding and techniques are used and demonstrated along with the design examples. 11, Preferred practices for the effective management of designs are discussed. 12. VHDL design partitioning techniques are addressed and discussed with examples. 13. An entire chapter (Chapter 8) is dedicated to clock- and reset-related cit- cuits. Clock skew, short path, setup and hold timing, and synchronization between clock domains are discussed with examples. s x ~ °0.1. Organization OF THE BOOK vii 14. Commonly used custom blocks such as first in, first out (FIFO), dual port random access memory (RAM), and dynamic RAM models are discussed with examples. 15. Alll figures in the book are available through the Internet to assist instruc- tors. 16. VHDL code examples are available through the Internet. 0.1 ORGANIZATION OF THE BOOK This book is divided into 15 chapters and one appendix. Appendix A is a VHDL pack- age example that has been referenced in many examples in the chapters. The details of each chapter are 2s follows: Chapter I describes design process and flow. Chapter 2 describes how to write VHDL to model basic digital circuit primitives or gates. Flip-flop, latch, and three-state buffer inferences are illustrated with examples. VHDL synthesis rules are presented to provide readers with an under- standing of what circuits will be synthesized from the VHDL. Chapter 3 presents the VHDL simulation and synthesis design environments. Synopsys simulation and synthesis design environments and design tools are introduced. Mentor QuickVHDL. simulation environment is also discussed. A typical design process for a block is discussed to improve the debugging pro- cess, Chapter 4 presents VHDL modeling, synthesis, and verification of several basic combination circuits such as selector, encoder, code converter, equality checker, and comparators. Each circuit is presented with different VHDL models and their differences and trade-offs are discussed. Chapter 5 concentrates on several binary arithmetic circuits. Half adder, full adder, ripple adder, carry look ahead adder, countone, leading zero, and barrel shifter are presented with VHDL modeling, synthesis, and test bench. Chapter 6 discusses sequential circuits such as counters, shift registers, parallel to serial converter, and seria! to parallel converter with VHDL modeling, synthe- sis, and test bench. Chapter 7 presents a framework to organize registers in the design. Registers are categorized and discussed. Partition, synthesis, and verification strategies of reg- isters are discussed. VHDL modeling, synthesis, and verification techniques are ilustrated. Chapter 8 is dedicated to clock- and reset-related circuits. The synchronization between different clock domains is discussed, The clock tree generation, clock delay, and clock skew are presented and discussed with timing diagrams and VHDL code. The issues of gated clock and clock divider are also introduced. Chapter 9 presents examples of dual-port RAM, synchronous and asynchronous FIFO, and dynamic RAM VHDL models. These blocks are commonly used as custom drop-in macros. They are used to interact with the rest of the design so that the complete design can be verified.vill Preface Chapter 10 illustrates the complete semicustom ASIC design process of a finite impulse response ASIC design through the steps of design description, VHDL coding, functional verification, synthesis, layout, and back-annotated timing verification. Chapter 11 discusses the concept of a microprogram controller. The design of a AMD AM2910 is presented through the gate array design process from VHDL coding to postlayout back-annotated timing verification. The test vector genera- tion is also illustrated. Chapter 12 discusses the principles of error and correcting Hamming codes. An actual TI EDAC integrated circuit is used as an example to design from VHDL code to all steps of FPGA design process. Chapter 13 presents the concepts of binary fixed-point multiplication algorithms such as Booth-Wallace multiplier. The VHDL coding, synthesis, and verifica- tion are presented. Chapter 14 discusses the concepts of binary fixed-point division algorithms. VHDL coding, synthesis, and verification are presented. Chapter 15 discusses the floating-point number representation. Floating-point addition and multiplication algorithms are discussed and implemented in VHDL. They are verified and synthesized. Appendix A lists a package that is used and referenced by many examples. 0.2 AUTHOR'S NOTE This book assumes that readers have the basic knowledge of VHDL syntax, modeling, synthesis concepts, and Boolean algebra. To acquire some background in VHDL, readers are referred to my previous book (Digital Design and Modeling with VHDL and Synthesis, 1EEE Computer Society Press, 1997) which concentrates on the com- plete VHDL language, syntax and coding techniques. The recommended VHDL background can be obtained from Chapters 2, 3, 4, 5, 6, 7, and 8 of that book. This book concentrates on the digital design from a basic half adder to a complete ASIC design, using VHDL coding, simulation, and synthesis techniques. The interfaces to FPGA and ASIC layout tools are also addressed. ‘Synopsys and Mentor Modeltech (QuickVHDL, which is similar to Modelsim) VHDL simulators, Exemplar FPGA synthesis, and Synopsys ASIC synthesis tools are used in this book. These tools are widely used and available throughout university and industry settings. The book is intended for both practicing engineers and as a college text. Chap- ters are divided according to specific designs, from simple to complex. Techniques for VHDL coding, test bench, verification, synthesis, design management, and actual0.3. Acknowledgments ix design examples are good references for practicing engineers. The book also provides a robust introduction to digital design. It presents the basic design concepts of a half adder, full adder, ripple adder, carry look ahead adder, counter, shift register, multi- plier, divider, floating-point arithmetic unit, error correction and detection unit, micro- controller, FIFO, dual port RAM, dynamic RAM, to a 700 thousands transistor finite impulse response filter ASIC design. These design concepts and disciplines are rein- forced by actual VHDL code, verification strategies, simulation commands and wave- forms, and synthesis commands and strategies. VHDL code is available for reference and practice. Previous experiences with VHDL, as suggested earlier, would be help- ful. However, an understanding of the code conventions can also be acquired from this book. Most students will soon become practicing engineers. This book not only gives you a block diagram, but also, more importantly, shows you how each design concept ‘can be captured, implemented, and realized in real life. An old Chinese saying is: “do not let your eyes and head reach higher than your hands,” which is to say that it is bet- ter to be able to do it with your hands, rather than just think and see something that is out of your grasp. I wrote this book to help the reader cope with both the design revolution that is taking place, as well as the increased demand for design complexity and a shortened design cycle. 0.3 ACKNOWLEDGMENTS This book would have been impossible without the following people: Ron Fernandes, who edited the entire first manuscript. My wife, Tsai-Wei, and my children, Alan, Steven, and Jocelyn, who were patient and sacrificed many of our weekends and dinners together. I owe my children so many smiles and bedtime stories because I often got home late and tired. My brothers, sisters, and many friends who encouraged and supported me. Ramagopal Madamala and Tsipi Landen at Chip Express provided support in running through the place and route tools for the design in Chapter 11. The Institute of Electrical and Electronics Engineers (IEEE) Computer Society Press editorial team, Mathew Loeb, Cheryl Baltes, and Denise Hurst contributed many valuable comments. Additionally, Joseph Pomerance did a skillful and thorough editing of the manuscript. The author deeply appreciates all of these people.Contents Chapter 1 INTRODUCTION 1 1.1 Integrated Design Process and Methodology 1 1.2 Book Overview 2 Chapter 2 VHDLAND DIGITAL CIRCUIT PRIMITIVES 4 21 Flip Flop 4 2.2 Latch 15 2.3 Three-State Buffer 18 2.4 Combinational Gates 22 25 VHDL Synthesis Rules 26 2.6 Pads 30 2.7 Exercises 30 Chapter 3 VHDL SIMULATION AND SYNTHESIS ENVIRONMENT AND 31 32 3.3 34 35 3.6 DESIGN PROCESS 32 ‘Synopsys VHDL Simulation Environment Overview 32 Mentor Quick VHDL Simulation Environment 36 Synthesis Environment 39 Synthesis Technology Library 45 VHDL Design Process for a Block 47 Exercises 52Contents Chapter 4 BASIC COMBINATIONAL CIRCUITS 4.1 Selector 53 4.2 Encoder 68 43 Code Converter 71 4.4 Equality Checker 73 4.5 Comparator with Single Output 79 4.6 Comparator with Multiple Outputs 82 4.7 Exercises 89 Chapter 5 BASIC BINARY ARITHMETIC CIRCUITS 5.1 Half Adder and Full Adder 91 5.2 Carry Ripple Adder 97 5.3. Camry Look Ahead Adder 101 54 Countone Circuit 119 5.5 Leading Zero Circuit 123 5.6 Barrel Shifter 132 5.7 Exercises 137 Chapter 6 BASIC SEQUENTIAL CIRCUITS 6.1 Signal Manipulator 143 6.2 Counter 150 6.3 Shift Register 166 64 Parallel to Serial Converter 177 65 Serial to Parallel Converter 180 6.6 Exercises 186 1 143xii Chapter 7 REGISTERS 7.1 General Framework for Designing Registers 187 7.2 Interrupt Registers 189 7.3. DMA and Control Registers 193 7.4 Configuration Registers 196 75 Reading Registers 201 7.6 Register Block Partitioning and Synthesis 202 7.7 Testing Registers 213 7.8 Microprocessor Registers 219 7.9 Exercises 221 Chapter 8 CLOCK AND RESET CIRCUITS 8. Clock Buffer and Clock Tree 222 8.2 Clock Tree Generation 225 83 Reset Circuitry 228 8.4 Clock Skew and Fixes 230 85 Synchronization between Clock Domains 238 86 — Clock Divider 242 8.7 Gated Clock 246 88 Exercises 250 Chapter 9 DUAL-PORT RAM, FiFO, AND DRAM MODELING 91 Dual-Port RAM 251 9.2 Synchronous FIFO 260 9.3 Asynchronous FIFO 266 9.4 Dynamic Random Access Memory (DRAM) 274 95 Exercises 286 Contents 187 222 251Contents Chapter 10 A DESIGN CASE STUDY: FINITE IMPULSE RESPONSE FILTER ASIC DESIGN 10.1 Design Description 288 10.2 Design Partition 293 10.3 Design Verification 307 10.4 Design Synthesis 322 10.5 Worst-Case Timing Analysis 325 10.6 Best-Case Timing Analysis 329 10.7 Netlist Generation 331 \ 10.8 Postlayout Verification 334 10.9 Design Management 337 10.10 Exercises 339 xili Chapter 11 A DESIGN CASE STUDY: A MICROPROGRAM CONTROLLER DESIGN 341 11.1 Microprogram Controller 341 11.2. Design Description and Partition 344 11.3. Design Verification 362 11.4 Design Synthesis 377 11.5 Postsynthesis Timing Verification 382 11.6 Preparing Release Functional Vectors 383 11.7 Postlayout Verification 387 11.8 Design Management 387 11.9 Exercises 389 Chapter 12 ERROR DETECTION AND CORRECTION 12.1. Error Detection and Correction Code 390 12.2 Single Error Detecting Codes 390 12.3 Single Error Correcting Codes 391 124 — Single Error Correcting and Double Error Detecting Codes 393 390xiv Contents 12.5 Error Detecting and Correcting Code Design Example 394 12.6 Design Verification 400 127 Design Synthesis 403 128 Netlist Generation and FPGA Place and Route 407 12.9 Exercises 407 Chapter 13 FIxED-POINT MULTIPLICATION 408 13.4 Multiplication Concept 408 13.2. Unsigned Binary Multiplier 409 13.3 2's Complement Multiplication 419 13.4 Wallace Tree Adders 423 13.5 Booth-Wallace Tree Multiplier 425 13.6 Booth-Wallace Tree Multiplier Verification 429 13.7 Booth-Wallace Tree Multiplier Synthesis 431 13.8 Multiplication with Shift and Add 437 13.9 Exercises 442 13.10 References 444 Chapter 14 FixED-POINT DIVISION 445 14.1 Basic Division Concept 445 142 32-Bit Divider 451 143 Design Partition 452 144 Design Optimization 453 145 Design Verification 458 14.6 Design Synthesis 462 14.7 Exercises 465 148 Reference 466Contents Chapter 15 FLOATING-POINT ARITHMETIC 15.1 Floating-Point Number Representation 467 15.2 Floating-Point Addition 468 15.3. Floating-Point Multiplication 479 15.4 Exercises 484 Appendix A PACKAGE PACK Index 467 485 496Chapter 1 Introduction ‘Welcome to the book! The advance of very large-scale integration (VLSI) process technologies has made “system on a chip” feasible for very complex systems. This is partly responsible for the market demand for much shorter design cycles even though design complexity has continued to increase. There are many design and VHDL code examples, simulation waveforms, and synthesized schematics shown in this book to illustrate their correspondence. VHDL code can be downloaded from the Internet for exercises. All examples have been veri- fied with VHDL simulation and synthesis tools to ensure high fidelity of the VHDL code. All VHDL codes are listed line by line for reference and discussion in the text. Each VHDL example is complete, no fragments so that the complete picture is clear to you. Design techniques of VHDL coding, verification, and synthesis that imple- ment the design concepts and principles are illustrated with actual examples through- out the book. In the next section, an integrated design process and methodology is introduced to serve as our base line design flow and approach. 1.1 INTEGRATED DESIGN PROCESS AND METHODOLOGY Figure 1-1 shows a flow chart that describes an integrated VHDL design process and methodology. The design is first described in VHDL. VHDL coding techniques will be applied to model the design efficiently and effectively. A preliminary synthesis for each VHDL code is done to check for obvious design errors such as unintended latches and insufficient sensitivity list before the design is simulated. This also ensures that all VHDL code can be synthesized. This process is discussed and illus~ trated in Chapter 2 as the VHDL design process for a block. A test bench is developed to facilitate the design verification. Test bench examples and verification techniques are discussed throughout the book for various designs. A more detailed synthesis can be started (in parallel with the test bench development) to calibrate design and timing constraints. The design architecture may require a change, based on the timing result. The complete design can be verified with the test bench. There will be iterations2 Chapter 1 Introduction among the VHDL coding, synthesis, test bench, and simulation. After the design is free of design errors, the complete and detailed synthesis is done. A netlist can be gen- erated for the layout tool to do the layout. The layout may be performed with Field Programmable Gate Array (FPGA), gate array, or standard cell layout tools. The lay- out tool can generate another VHDL netlist with the timing delay file in Standard Delay Format (SDF), which can be used for simulation with the test bench. Using the simulation results, test vectors can be generated for the foundry to test the fabricated . ASIC design. A FPGA design does not need the test vector. The layout can be per- formed in-house or by a vendor. For the ASIC design, the layout tool can generate a GDSII file to describe the masks for fabrication, ‘The synthesis tool can also generate a VHDL netlist for postsynthesis and pre- layout simulation. This is not common. The postlayout simulation is preferred since the timing generated from the layout tools is much closer to the actual hardware. Note also that the test bench should be used for both functional simulation and postlayout timing simulation without the need to change. in this book, many examples are used to illustrate all the steps of the process described in Figure 1-1. ‘Test bench development Figure 1-1 VHDL design process and methodology. 1.2 BOOK OVERVIEW Chapter 2 describes how to write VHDL to model basic digital circuit primitives or gates. Flip-flops, latches, and three-state buffers inference is illustrated with exam- ples. VHDL synthesis rules are presented to provide guidelines what circuits will be synthesized by synthesis tools.1.2. Book Overview 2 Chapter 3 presents the VHDL simulation and synthesis design environments. ‘Synopsys simulation and synthesis design environments and design tools are intro- duced. Mentot QuickVHDL simulation environment is also discussed. A typical design process for a block is discussed to improve the debugging process. Chapter 4 presents VHDL modeling, synthesis, and verification of several basic combination circuits such as selector, encoder, code converter, equality checker, and comparators. Each circuit is presented with different VHDL models so that their dif- ferences and trade-offs are discussed. Chapter 5 concentrates on several binary arithmetic circuits. Half adder, full adder, ripple adder, carry look ahead adder, count one, leading zero, and barrel shifter are presented with VHDL modeling, synthesis, and test bench. Chapter 6 discusses sequential circuits such as counters, shift registers, parallel to serial converter, and serial to parallel converter with VHDL modeling, synthesis, and test bench, Chapter 7 presents a framework to organize registers in the design. Registers are categorized and discussed, Partition, synthesis, and verification strategies of registers are discussed. VHDL modeling, synthesis, and verification are illustrated. Chapter 8 is dedicated to clock- and reset-related circuits. The synchronization between different clock domains is discussed. Clock tree generation, clock delay, and clock skew are presented and discussed with timing diagrams and VHDL code. The issues of gated clock and clock divider are also introduced. Chapter 9 presents examples of dual-port RAM, synchronous and asynchronous FIFO, and dynamic RAM VHDL models. These blocks are commonly used as custom drop-in macros. They are used to interact with the rest of the design so that the com- plete design can be verified. Chapter 10 illustrates the complete semicustom ASIC design process of a Finite Impulse Response ASIC design through the steps of design description, VHDL cod- ing, functional verification, synthesis, layout, back-annotated timing verification. Chapter 11 discusses the concept of a microprogram controller. The design of a AMD AM2910 is presented through the gate array design process from VHDL coding to postlayout back-annotated timing verification. Test vector generation is also illus- trated. Chapter 12 discusses the principles of error and correcting Hamming codes. An actual TI EDAC integrated circuit is used as an example to design from VHDL code to all steps of FPGA design process. Chapter 13 presents the concepts of binary fixed-point multiplication algorithms such as Booth-Wallace multiplier. The VHDL coding, synthesis, and verification are presented. Chapter 14 discusses the concepts of binary fixed-point division algorithms. VHDL coding, synthesis, and verification are presented. Chapter 15 discusses the floating-point number representation. Floating-point addition and multiplication algorithms are discussed and implemented with VHDL codes. They are verified and synthesized.Chapter 2 VHDL and Digital Circuit Primitives Digital circuit primitive gates are basic building components such as AND, NAND, NOR, and INVERTER used by synthesis tools to construct designs. In this chapter, we will use VDL to describe these basic digital circuit primitive gates to show how basic digital circuit gates can be described in VHDL so that the synthesis tools can get the design we want. It is important to understand the correspondence between VHDL and basic digital circuit gates. 2.1 FLIP-FLOP AD flip-flop is the most common sequential element used in the digital design. Fig- ure 2-1 shows a D flip-flop schematic symbol. It has two inputs, D and CLK, which represent data and clock, respectively. It has a data output port Q. The following VHDL code can be used to model the D flip-flop. The IEEE library and std_logic_1164 package are referenced in lines 1 and 2. Input and output ports are described in the VHDL entity from lines 3 to 7. Figure 2-1 D flip-flop symbol,24 Flip-Flop 5 1 library IEEE; 2 use IEEE.std_logic_1164.al1; 3 entity DFF is 4 port( 5 CLK, D: in std_logic; 6 Q out std_logic); 7 end DEF; 8 architecture RTL of DFF is 9 begin 10 seq0 : process 11 begin 2 wait until CLK’event and CLK = ‘1’; 33 a0 14 end proces: 15 end RTL; The behavior of the D flip-flop is modeled inside the VHDL architecture from lines 8 to 15. A concurrent process statement (lines 10 to 14) is used. Recall that dur- ing the initialization phase of the simulation, every object (which is not initialized with a value) is initialized to its leftmost value of its basic type. Type std_logic is an enumerated type with values (“U’, ‘X’, ‘0’, ‘1’, ‘2’, “W’, ‘L,, ‘H? and ‘-’) to indicate certain conditions such as uninitialized, forcing unknown, forcing ‘0’, forcing ‘1’, high impedance, weak unknown, weak ‘0’, weak ‘1’, and don’t care, respectively. Since D, CLK, and Q are declared as std_logic type, they are initialized to the unini- tialized value ‘U’. Every concurrent process statement is evaluated until it is sus- pended. In this case, after D, CLK, and Q are initialized to ‘U’, the process statement is evaluated from the beginning (line 11) until line 12. The process is then suspended as it waits for the rising edge of the clock signal CLK. Figure 2-2 shows the simula- tion waveform obtained by running the following Quick VHDL simulation commands: run 50, force D 0, force CLK 0, run 50, force CLK 1, run 50, force CLK 0, force D 1, run 50, force CLK 1, run 50, force CLK 0, run 50, force CLK 1, run 50, force CLK 0, force D 0, run 50, force CLK 1, run SO, force CLK 0, run 50, force CLK 1, run 50. Basically, we use the run command to advance the simulation time, and use the force command to change the input signal values. The first command, run 50, advances the simulation time to 50 ns. Signals CLK, D, and Q have the same value ‘U’ since their values have not been assigned. At time 50 ns, D and CLK are both set to ‘0’. The simulation time is advanced to 100 ns where the clock signal CLK is assigned to ‘1’, At this time, the process statement proceeds through lines 12, 13, 14, and back to 11. It is again suspended at line 12. The output signal Q is updated from ‘U’ to ‘0’. Signal D is assigned to ‘1’ at time 150 ns. At time 200 ns, clock signal CLK is assigned to ‘1’, the process statement is executed again (line 12, 13, 14, back to 11), and suspended once more at line 12. Signal Q is updated to ‘I’ and the simulation process is repeated as before.Chapter 2 VHDL and Digital Circuit Primitives Vcccccneerioniececeiceeciseeetvereeneeepeccrtor aya cr cP eer ce crete cece eeeeer eee Ee Ons 2501s 500ns Figure 2-2 D flip-flop simulation waveform. From the simulation waveform, it is easy to see that signal Q follows signal D with a delay. Whatever the value of signal D before the rising edge of the clock CLK, it is captured as the value of signal Q. This is the reason we often refer toa D flip-flop asa delay flip-flop. Note that the DFF VHDL code is synthesized to the schematic shown in Figure 2-1. The D flip-flop has only one Q output; output Qn (inverted Q) is not connected. We can modify the DFF VHDL slightly to include the Qn output as shown in line 6. A temporary signal DFF is declared in line 9, which is used in line 14. Output signals Q and Qn are assigned in line 16. The DFFON VHDL code is synthesized 10 the sche- matic as shown in Figure 2-3. 1 library IEEE; 2 use IEEE.std_logic_1164.al1; 3 entity DFFQN is 4 port ( 5 CLK, D: in std_logic; 6 Q Qn + out std logic); 7 end DFFON; 8 architecture RTL of DFFQN is 9 signal DEF : std_logic; 19 begin 11 seq0 : process 12 begin 13 wait until CLK’event and CLK = ‘1'; 4 DEF <= D; 15 end process; 16 <= DFF; Qn <= not DEF; 17 end RT;24 Flip-Flop 7 > Gla —_{[7> Gn Figure 2-3 D flip-flop with Qn output. The above D flip-flop is the simplest version. It does not have the synchronous or asynchronous reset input. Also, there are other ways to write VHDL to infer D flip- flops. The following VHDL code shows various ways to infer D flip-flops. 1 Library IEEE; 2 use IEEE.std_logic_1164.all; 3 entity FFS is 4 port( 5 CLOCK : in std_logic; 6 ARSTn : in std logic; 7 SRST : in std logic; 8 DIN : in std_logic_vector(5 downto 0); 9 DoT +: out std_logic_vector(5 downto 0)); 10 end FFS; ‘The ffs.vhd code infers six flip-flops with four process statements. Note that cach process statement has the expression (CLOCK’event and CLOCK = ‘1’) to check the rising edge of the clock signal CLOCK in lines 15, 20, 32, and 38. Every target signal (signals appearing on the left-hand side of the signal assignment state- ments) affected by the rising edge expression infers a number of flip-flops depending on the target signal width. Processes seq0 (lines 13 to 17) and seql (lines 18 to 26) use a wait statement inside a process statement without a sensitivity list. The target signal to infer a flip- flop can have a Boclean expression on the right-hand side of the signal assignment statements as in lines 16, 24, and 26. The target signal value can also be affected by other sequential statements such as the if statement in lines 21 to 25. These Boolean expressions and sequential statements would result in combination circuits before the D input of the D flip-flop as shown in Figure 2-5 synthesized schematic. Processes seq2 (lines 28 to 35) and seq3 (lines 36 to 46) use a process statement with a sensi-Chapter2 VHDL and Digital Circuit Primitives tivity list. There is no wait statement inside the process statement. As we recall, a Process statement should have either a sensitivity list or at least a wait statement, but not both. 11 architecture RTL of FFS is 12 begin 13 seqd : process 14 begin 15 wait until CLOCK’event and CLOCK = ‘1"; 16 DOUT(O) <= DIN(O) xor DIN(1); 17 end process; 18 seql : process 19 begin 20 wait until CLOCK’event and CLOCK = a if (SRST = ‘0') then 22 23 24 DOUT(1) <= DIN(1) nand DIN(2); 25 end if; 26 DoUr(4) <= SRST and (DIN(1) nand DIN(2))7 27 end process; 28 seq? : process (ARSTn, CLOCK) 29° begin 30 if (ARST| = ‘0") then 31 DOUT(2) <= '0'; 32 elsif (CLOCK’event and CLOCK = ‘1’) then 33 POUT(2) <= DIN(2) nor DIN(3); 4 end if; 35 end process; 36 seq3 ? process (CLOCK) 37 begin 38 Lf (CLOCK’event and CLOCK = ‘1) then 39 DOUT(5) <= SRSTn and DIN(3); 40 if (SRST™m = ‘0') then 41 Dour(3) <= ‘0’; 42 else 43 DOUT(3) <= DIN(3); “4 end if; 45 end if; 46 end process; 47 end RTL;21 Flip-Flop [> oouris:e Loc > arsto> DIN(5 81 noe PD» Figure 2-4 Synthesized schematic for ffs.vhd. The input signals SRSTn and ARSTn are used to synchronously and asynchro- nously reset the flip-flops. SRSTn is used in lines 21, 26, 39, and 40 to show various ways to synchronously reset the flip-flops. The synchronous behavior is modeled by checking the rising edge before the SRSTn signal affects the target signal values. In other words, the event on signal SRSTn will not change the result until the clock ris-