1.

Question 1 :
//question 1
module q(a,b,c,f);
input a,b,c;
output f;
wire q,w,e,r,t,y;
not (q,a);
and(w,q,b);
not (e,b);
and (r,e,c);
not (t,c);
and (y,a,t);
or(f,y,r,w);
endmodule
2. Question 2:
//question2
module q(a,b,c,d,f);
input a,b,c,d;
output f;
wire z,x,v,n,m,l,k,j,i;
not(z,a);
not(x,b);
not(v,c);
not(n,d);
and(m,z,x,v,n);

and(l,a,b,n);
and(k,a,c);
and(j,c,d);
and(i,z,b,d);
or(f,m,l,k,j,i);
endmodule
3. Question 3:
//question3
module Question_3(a,b,c,d,f);
input a,b,c,d;
output f;
wire q,w,e,r,t,y,u,i,o,p;
not(q,a);
not(w,b);
not(e,c);
not(r,d);
or(t,a,w,c);
or(y,c,r,a);
or(u,a,w,r);
or(i,c,r,w);
or(o,q,b,e);
or(p,e,d,b);
and(f,t,y,u,i,o,p);
endmodule
4. Question 4:

//question 4
module q(a,b,c,f);
input a,b,c;
output f;
reg f;
always@(*)
begin
if(a==b&&b==c&&c==a)
f=0;
else
f=1;
end
endmodule
5. Question 5:
//question5
module q(a,b,c,d,f);
input a,b,c,d;
output f;
reg f;
always@(*)
case ({a,b,c,d})
4'b0000 : f=1;
4'b0011 : f=1;
4'b0101 : f=1;
4'b0111 : f=1;

4'b1010 : f=1;
4'b1011 : f=1;
4'b1100 : f=1;
4'b1110 : f=1;
4'b1111 : f=1;
default : f=0;
endcase
endmodule
20. Question 20 :
//question 20
module pipo( din ,clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din;
end

endmodule
//question 21
module piso_q21(d_in ,clk ,reset ,load ,d_out );
output d_out ;
reg d_out ;
input [3:0] d_in ;
wire [3:0] d_in ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= d_in;
else begin
d_out <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule

//question 22
module piso_q21(d_in ,clk ,reset ,load ,d_out );
output d_out ;
reg d_out ;
input [3:0] d_in ;
wire [3:0] d_in ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= d_in;
else begin
d_out <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule
// question 23

module uni_sfrg_q23 (data_out, msb_out, lsb_out, data_in,msb_in, lsb_in, s1, s0, clk,
rst);
output [3:0] data_out;
output

msb_out, lsb_out;

input [3:0] data_in;

input

msb_in, lsb_in;

input

s1, s0, clk, rst;

reg

// Hold
// Serial shift from msb

// Serial shift from lsb

// Parallel load

[3:0]data_out;

assign msb_out= data_out[3];

assign lsb_out= data_out[0];
always @ (posedge clk)
begin
if (rst) data_out<=0;
else case ({s1, s0})
0 : data_out <= data_out;
1 : data_out <= {msb_in, data_out[3:1]};
2 : data_out <= {data_out[2:0], lsb_in};
3 : data_out <= data_in;
endcase
end
endmodule