United International University (UIU)

Dept. of Computer Science & Engineering (CSE)

COURSE OUTLINE (Section : SB)
Course Code: CSE 225
Course Title: Digital Logic Design
Summer Trimester: 2015
Instructor

Maitraye Das

Counseling hr.

Sun
Mon
Tues
Wed

Room No.

401 (Campus 01)

Email

maitraye@cse.uiu.ac.bd

Website

www.sites.google.com/sites/maitrayeurmi/for-students

Text books

[Mano1] Logic and Computer Design Fundamentals. M. Morris Mano and

Charles R. Kime, 2nd/3rd Edition.

2.00 PM - 3.30 PM
12.40 PM 4.30 PM
2.00 PM - 3.30 PM
12.40 PM 2.10 PM

[Mano2] Digital Logic and Computer Design. M. Morris Mano (1979).

Evaluation

Tests Policy

Grading

Attendance

5%

Assignments

5%

Class Tests

20%

Midterm

30%

Final

40%

Schedule of the mid-terms: 7th week of the semester

4 class tests will be taken, best 3 will be considered.
Mid-terms and final exams will be closed book, closed notes. The materials for
final exam will be informed in due time. There will be no grade exemptions
from the final. Final examination is not comprehensive.
If you are absent from a test, and you have not spoken to me personally
beforehand, your grade for the test will be zero.
The course grade will be determined from a weighted average of the class
tests, assignments, mid-term exams and the final. The letter grades will be
assigned as follows:
Letter Grade Marks

Grade Point Letter Grade

Marks

Grade Point

A (Plain)

90-100

4.0

C+ (Plus)

70-73

2.33

A- (Minus)

86-89

3.67

C (Plain)

66-69

2.00

B+ (Plus)

82-85

3.33

C- (Minus)

62-65

1.67

B (Plain)

78-81

3.00

D+ (Plus)

58-61

1.33

B- (Minus)

74-77

2.67

D (Plain)

55-57

1.00

Lecture Plan
Topics

Weeks

Introduction: Course Overview, Number System, Base Conversion,

Arithmetic Operations, BCD coding

1-2

Combinational Logic Circuit (Part 1, Part 2, Part 3): Binary Logic

and Gates, Boolean Algebra, Minterms and Maxterms, SOP, POS,
Simplification Of Boolean Functions, Map Manipulation, Additional
Gates (NAND, NOR, XOR, etc.), Universal NAND implementation

3-6

Midterm

Combinational Logic Design (Part 1, Part 2): Design topics, Design

Procedure, Decoder, Encoder, Multiplexer, Adder

8-9

Sequential Logic (Part 1, Part 2, Part 3): Latches, Flip Flops, Race
Around Problems, Excitations Table, Slides from University of Illinois

10-11

Register: Register With Parallel Load, Shift Register

Counter: Ripple Counter, Synchronous Counter, Arbitrary counter
using flip-flops.

12-13