EECS 470 Fall 16

Homework 5
Due Mon. Dec. 5th at 6pm eastern via gradescope. No late homeworks.
Name: _______________________________ unique name: ________________
This is an individual assignment, all of the work should be your own. Assignments that are difficult to read will lose at least 50%
of the possible points and we may not grade them at all. This assignment is worth a bit less than 2% of your grade in the class
and is graded out of 30 points. Remember you may drop one homework assignment.

a) We have discussed three classes of prefetching mechanisms: spatial/stride prefetchers, run-ahead/pre-execution

prefetchers, and address-correlation prefetchers. For each of the access patterns below, identify which class of
prefetcher is likely to provide the most performance improvement.
i) Traversing a linked list. [2]
ii) A loop accessing a large two-dimensional array. [2]
iii) A loop that probes a large hash table. Loop iterations are independent. [2]
iv) A piece of code that examines several fields in network packet headers to make routing decisions. [2]
2) Given a virtually indexed, physically-tagged cache that is four-way associative and has 64-byte blocks, what is the
largest total size the cache could have if pages were 4KB in size? What is the largest number of sets it could have in
that case? How would these two values change if the cache were direct-mapped? [5]
3) Describe one hardware and one software solution to mitigate the synonym problem in the D-cache. [6]
4) In one or two sentences, explain why it is difficult to support multiple page sizes in a hardware TLB. [4]
5) Draw the state transition diagram for a three-state MSI (Modified-Shared-Invalid) coherence protocol for a snoopy
bus-based symmetric multiprocessor. Draw only the stable states (i.e., your diagram should have three states,
Modified, Shared, and Invalid). Include transition arrows for all events that can occur in a state. For each
transition, label it with Event => Reaction.
[7 points]
Events
CPU Read
CPU Write
Bus Read Request (read by another CPU)
Bus Write Request (write by another CPU)

Possible Reactions
Invalidate line
Write Back line