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Low Power VLSI Design

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Time: 3 hrs.

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Note: Answer any FIVE full qwestions"

(08 Marks)
a. Explain the need for Low Power VLSI design.
b. With usual notations show that dynamic power dissipation in an inverter is given by
Pa: C. V'f The chip size of a CPU is 15mm x 25mm with clock frequency of 300 MHz

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operating at3.3V. The length of the clock routing is estirnated to be twice the circumference
of the chip. Assume that the clock signal is routed on a metal layer with a width of 1.2pm
and the parasitic capacitance of the metal layer is I fFitrrm2. What is the power dissipation of
the clock signal?
(12 Marks)

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a. Explain with neat diagram, the structure of MIS diode. f)raw the energy band diagram of
unbiased MIS diode.
(08 Marks)
b. Explain the advantages and lirnitations of SPICE Power Analysis Method. (06 Marks)
c. Derive an expression for number of samples 'N' required for stopping criteria in Monte
Carlo Sirnulation.
(06 Marks)

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c. Briefly explain the characterization

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What are Glitches? What

minimized?
b. Explain bnefly the itrliowing

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Derive relation between Conditional probability and Frequency.

(07 Marks)

For combinational circuit, rvrite the algorithm horv Transition density is used for power
analysis at gate level.

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Compute the transition density and static probability of Y : ab + c. Given P(a) : 0.2 ,
P(b):0.3 , F(c):0.4 , D(a): 1 , D(b) :2 and D(c):3.
(t0Marks)
b. Define Signal Entropy. Explain power estimation of combinational logic using entropy
analysis.
(I0 Martrs)

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(07 Marks)

of logic signals.

(06 Marks)

their effect on power

i) Latches ii)

consumption?

How can they

be

(10 Marks)

Flip flops.

(10 Marks)

What is Gate Reorgani'zation? Briefiy explain different power saving techniques through
Gate reorganization, Signal gating and Logic encoding techniques.
(12 Marks)
What is Precotnputation Logic? E,xplain the precompr-rtation logic for an n - bit comparator.
(08 Marks)

Discuss sources of Power dissipation in SRAM and DRAM.

How do you optimize power consumption for design case like FIR filter?

Explain the power analysis and estimation technique at the algorithrn ievel.
b. Write short notes on :
i) 8 - bit Wallace multiplier.
ii) Low power digital cell library.

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(10 Marks)
(10 Marks)

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(10 Marks)