module dff(input a,b,clk,rst_n, output reg q);

reg temp_q;
always @(a,b)begin
temp_q = a+b;
end

always@(posedge clk or negedge rst_n)begin

if(!rst_n)begin
q<= 0;
end
else begin
q <= temp_q;
end
end

endmodule