Architecture of Intel 80286

Key Features

16-bit date bus

24-bit non-multiplexed bus

Packaged in a 68-pin ceramic pack

80286 has 2 24 = 16 M Byte of physical memory accessibility

Fig 32.1 Basic Architecture of 80286

Memory Bank
Memory of 80286 is setup as an odd bank and an even bank, just as it is for the 8086. The even bank is enabled when A 0 is low
and the odd bank is enabled when
is low. To access an aligned word, both A 0
will be low.

Fig 32.2 Memory banks in 80286

Memory Addressing in 80286
1.

Real Addressing Mode - It is just like as in 8086. Address is 20 bit with 16 bit segment and 16 bit offset. When 80286 is
hardware reset, it automatically enters real address mode.

2.

Protected Virtual Addressing Mode (PVAM) - In this we have 1 GByte of virtual memory and 16 Mbyte of physical memory.
The address is 24 bit. To enter PVAM mode, Processor Status Word (PSW) is loaded by the instruction LPSW.

Fig 32.3 Load Processor Status Word

PE-ProtectionEnable
MP - Monitor Processor Extension
EM - Emulate Processor Extension
TS - Task Switch
Hardware reset is the only way to come out of protected mode.
80286 Memory Management Scheme
Memory is organized into logical segments. Segment size can be anywhere between 1 Byte to 16 KByte. All 24 address pins are
active and 16 MByte of physical memory is available.
Descriptor
It is 8-byte quantity. Each segment has a descriptor. There are two main types of descriptor

Segment Descriptor

System control Descriptor

Format of a Descriptor

Fig 32.4 Descriptor Format

Access Right byte definition

7
6-5
4

Present (P)

1 - Yes
0 No

Descriptor Privilege level (DPL)

0 to 3

Segment Descriptor

1 - Segment
0 Control

For segment descriptor, i.e. for S = 1, bits 3-0 have the following meaning -

E
Expansion/ Confirming

0 - Data
1 - Code
If code, Confirming: 1 means 'Yes', 0 means 'No'
If data, Expand down: 1 - Yes, 0 - No (normal case)

R/W

If code, Readable: 1 - Yes, 0 - Not

If data, Writeable: 1 - Yes, 0 - Not

Accessed (A)

A = 0, Not accessed
A = 1, Accessed

Descriptors are contained in a descriptor table. There are two categories of descriptor table - global and local. A system has only
one global descriptor table or GDT. A local descriptor table or LDT is set up in the system for each task or closely related group of
tasks. Each task can have its own descriptor table and memory area defined by the descriptors in it.
Accessing Segments
The 80286 microprocessor keeps the base address and limits for the descriptor tables currently in use in internal registers. These
registers are load descriptor table register (LDTR) and global descriptor table register (GDTR). Descriptor in memory is addressed
by adding segment selector to these registers. The descriptors contain the base address of segments, which when added with the
offset in the virtual address points to the required memory location.
Accessing a Segment of Higher Privilege Level
Tasks operate at the lowest privilege level. Usually, segments at a lower privilege level are not allowed to access segments at a
higher privilege level directly. However, a lower level segment can access a higher level segment indirectly by a Gate Descriptor.
The details of a gate descriptor are given herewith.

Fig 32.5 Privilege Level

Gate Description Format

Fig 32.6 Gate Descriptor Format

Name

Value

Description

Type

Call gate

Task gate

Interrupt gate

Trap gate

Descriptor contents are NOT valid

Descriptor contents are valid

DPL

0-3

Descriptor privilege level

Word Count

0-31

Number of words to copy from callers stack to called

procedures stack. Only used with called gates.

Selector to target code segment (call, interrupt, task gates)

Destination Selector

16-bit Selector
Selector to target task state segment (task gate)

Destination Offset

16-bit Offset

Entry point within the target code segment

Task Switching and Task gates

Each task in a PVAM system has a 22-word task state segment (TSS) associated with it. A TSS holds copies of all registers and
flags, the selector for the tasks' LDT, and a link to the TSS of the previously executing task.
Descriptors for each task state segment are kept in the global descriptor table. A task register (TR) in the 80286 holds the selector
and the task state segment descriptor for the currently executing task. The load task register (LTR) instruction can be used to
initialize the task register to the task state segment for a particular task. During a task switch the task register is automatically loaded
with the selector and descriptor for the new task.
Method of Task Switching
1.

Long jump or call instructions that contain a selector which points to the Task State segment descriptor

2.

IRET

3.

Selectors in a long jump or call points to a task gate

4.

Interrupt occurs and the vectors point to a task gate descriptor

80286 Interrupt Handling

Real addressing mode has 256 interrupts with types 0-255. Each interrupt takes 4 bytes, so we have to reserve 1KByte of memory
for interrupt.
In PVAM mode also we have 256 interrupts but it is not assigned a fixed memory. The interrupt descriptor table can be anywhere in
the physical memory. Base address of interrupt descriptor table is stored in interrupt descriptor table register (IDTR). The particular
descriptor is accessed as follows (Interrupt Type * 8) + IDTR

Descriptor

Intel 80386 - A 32-bit Microprocessor with Memory Paging Facility

Intel 80386 is a logical extension of the 80286 microprocessor. The basic architecture of 80386 is given here.

Fig. 33.1 Basic architecture of 80386 microprocessor

Features of 80386:

More highly pipelined than 80286

Instruction fetching, instruction decoding, instruction execution and memory management are all carried out in parallel.

32-bit data bus

32-bit non-multiplexed address bus

232 = 4 Gigabyte of physical memory

246 or 64 Terabyte of virtual memory.

Instruction set compatibility :

Instruction sets of Intel microprocessors have upward compatibility (for example, a program written in 80186 can run in any higher
80286 or 80386 architecture).

Fig. 33.2 Instruction sets of Intel microprocessors (8086/8088 to 80386) are upward compatible
Segment registers:

Real address mode of 80386

After reset, the 80386 starts from the memory location FFFFFFF0 H under real address mode. In real address mode, 80386 works
as a fast 8086 with 32 bit registers and data types. The addressing techniques, memory size, interrupt handling in this mode of
80386 are similar to the real addressing mode of 80286. In real address mode, the default operand size is 16 bit but 32 bit operands
and addressing modes may be used with the help of override prefixer.

Maximum physical memory = 1Mega byte 0000 0000 - 000FFFFF (A 0 -A 19 ).

Maximum virtual memory: 2 14x2 32 = 2 46 bytes or 64 Terabytes.
Protected Virtual Addressing Mode (PVAM)
80386 operates in two memory management modes in PVAM. They are given as follows
1. Non Paged mode:
MMU operates similar to 80286.Virtual addresses are represented with a selector component and an offset component. The selector
component is used to index a descriptor in a descriptor table. The descriptor contains the 32 bit physical base address for the
segment. The offset part of the virtual address is added to the base address to produce the actual physical address. The offset part
of a virtual address can be 16 or 32 bits so segment can be as large as 4 gigabytes.
Hence the virtual memory size is

2 13 *2*2 32 = 2 46 bytes or 64 Terabytes.

Advantage of segmentation of memory: Segments corresponds to code and data structures in the program. Hence segmentation is
useful.
Limitation of segmentation of memory : If we need only a part of memory, even then we have to swap the whole segment content.
This will increase the time for execution.

Paged mode: In this mode, instead of segments, 4 kbytes of fixed page length are used.
Limitation : Pages do not correspond to the logical structure of the program.
Advantage : Pages can be quickly swapped.
Conversion of linear address into physical address:

Fig. 33.3 Address translation mechanism in 80386 paging unit

Page directory
Page directory entry

Page table entry

P = entry can be used in address translation

P= 1 Yes
P = 0 No
A = accessed
A = 1 page is accessed
= 0 page is unaccessed
D = dirty bit
Dirty bit is set before any write operation to the page.
Dirty bit is undefined for page directory entries.

U/S and R/W bits are used to provide protection.

U/S

R/W

permitted for level3

permitted for levels 2,1,0

None

Read/Write

None

Read/Write

Read only

Read/Write

Read-write

Read/Write

Use of Translation Look-aside Buffer (TLB) in 80386

It is cumbersome and time consuming to calculate the physical address from linear address for every memory location. A
Translation Look-aside Buffer (TLB) simplifies the process. TLB is a page table cache, which stores the 32 recently accessed page
table entries.
The paging unit receives a 32-bit linear address from the segmentation unit. The upper 20 bits of the linear address is compared
with all 32-entries in the translation look-aside buffer (TLB) to check if it matches with any of the entries. If it matches, the 32-bit
physical address is calculated from matching TLB entry and placed on the address bus.

Fig. 34.1 TLB organization in 80386

Structure of TLB:
TLB has 4 sets of eight entries each. Each entry consists of a TAG and a DATA. Tags are 24 bit wide. They contain 20 upper bits of
linear address, a valid bit and three attribute bits. The Data portion of each entry contains higher 20 bits of the Physical address.

Fig. 34.2 Structure of TLB

Introduction to Intel 80486:
CPU 80486 DX from Intel is the first 32-bit microprocessor to have an inbuilt floating point unit. It retained the complex instruction
set of 80386 but introduced more pipelining for speed enhancement. 80486 has five stages of pipelining. Two out of five stages are
used for decoding complex instructions of 80486 architecture. The 80486 is also the first amongst the xxx86 processors to have an
on-chip cache. This 8 Kbytes of cache is a unified data and code cache and acts on the physical addresses.

Note: 80486 SX does not have floating point unit

32-bit address lines: (A 2 - A 31 , BE 0 - BE 3 )
32-bit data lines: (D 0 - D 31 )

Pentium Architecture
The Pentium family of processors originated from the 80486 microprocessor. The term ''Pentium processor'' refers to a family of
microprocessors that share a common architecture and instruction set. The first Pentium processors were introduced in 1993. It runs
at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. Some of the features of Pentium architecture are

Complex Instruction Set Computer (CISC) architecture with Reduced Instruction Set Computer (RISC) performance.

64-Bit Bus

Upward code compatibility.

Pentium processor uses Superscalar architecture and hence can issue multiple instructions per cycle.

Multiple Instruction Issue (MII) capability.

Pentium processor executes instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple

instructions so that it takes less time to execute two instructions in a row.

The Pentium processor fetches the branch target instruction before it executes the branch instruction.

The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for instructions and one for data. It allows the
Pentium processor to fetch data and instructions from the cache simultaneously.

When data is modified, only the data in the cache is changed. Memory data is changed only when the Pentium processor
replaces the modified data in the cache with a different set of data

The Pentium processor has been optimized to run critical instructions in fewer clock cycles than the 80486 processor.

Fig 35.1 Superscalar Architecture of Pentium

The Pentium processor has two primary operating modes 1.

Protected Mode - In this mode all instructions and architectural features are available, providing the highest performance
and capability. This is the recommended mode that all new applications and operating systems should target.

2.

Real-Address Mode - This mode provides the programming environment of the Intel 8086 processor, with a few
extensions. Reset initialization places the processor in real mode where, with a single instruction, it can switch to protected
mode

The Pentium's basic integer pipeline is five stages long, with the stages broken down as follows:
1.

Pre-fetch/Fetch : Instructions are fetched from the instruction cache and aligned in pre-fetch buffers for decoding.

2.

Decode1 : Instructions are decoded into the Pentium's internal instruction format. Branch prediction also takes place at this
stage.

3.

Decode2 : Same as above, and microcode ROM kicks in here, if necessary. Also, address computations take place at this

stage.
4.

Execute : The integer hardware executes the instruction.

5.

Write-back : The results of the computation are written back to the register file.

Fig 35.2 Pentium pipeline stages

Floating Point Unit :
There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8 stages of pipelining. First five are similar to
integer unit. Since the possibility of error is more in Floating Point unit (FPU) than in integer unit, additional error checking stage is
there in FPU. The floating point unit is shown as below

Fig 35.3

Floating Point Unit

FRD - Floating Point Rounding

FDD - Floating Point Division
FADD - Floating Point Addition
FEXP - Floating Point Exponent
FAND - Floating Point And
FMUL - Floating Point Multiply

Architecture of 8086
Unlike microcontrollers, microprocessors do not have inbuilt memory. Mostly Princeton architecture is used for microprocessors
where data and program memory are combined in a single memory interface. Since a microprocessor does not have any inbuilt
peripheral, the circuit is purely digital and the clock speed can be anywhere from a few MHZ to a few hundred MHZ or even GHZ.
This increased clock speed facilitates intensive computation that a microprocessor is supposed to do.
We will discuss the basic architecture of Intel 8086 before discussing more advanced microprocessor architectures.
Internal architecture of Intel 8086:
Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and 20-bit address bus. The lower 16-bit address lines and 16-bit data
lines are multiplexed (AD0-AD15). Since 20-bit address lines are available, 8086 can access up to 2 20 or 1 Giga byte of physical
memory.
The basic architecture of 8086 is shown below.

Fig 29.1 Basic Architecture of 8086 Microprocessor

The internal architecture of Intel 8086 is divided into two units, viz., Bus Interface Unit (BIU) and Execution Unit (EU).
Bus Interface Unit (BIU )
The Bus Interface Unit (BIU) generates the 20-bit physical memory address and provides the interface with external memory
(ROM/RAM). As mentioned earlier, 8086 has a single memory interface. To speed up the execution, 6-bytes of instruction are
fetched in advance and kept in a 6-byte Instruction Queue while other instructions are being executed in the Execution Unit (EU).
Hence after the execution of an instruction, the next instruction is directly fetched from the instruction queue without having to wait
for the external memory to send the instruction. This is called pipe-lining and is helpful for speeding up the overall execution
process.

8086's BIU produces the 20-bit physical memory address by combining a 16-bit segment address with a 16-bit offset address. There
are four 16-bit segment registers, viz., the code segment (CS), the stack segment (SS), the extra segment (ES), and the data
segment (DS). These segment registers hold the corresponding 16-bit segment addresses. A segment address is the upper 16-bits
of the starting address of that segment. The lower 4-bits of the starting address of a segment is always zero. The offset address is
held by another 16-bit register. The physical 20-bit address is calculated by shifting the segment address 4-bit left and then adding
that to the offset address.
For Example:

Code segment Register CS holds the segment address which is 4569 H

Instruction pointer IP holds the offset address which is 10A0 H
The physical 20-bit address is calculated as follows.
Segment address : 45690 H
Offset address
:+ 10A0 H
Physical address : 46730 H