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Sach PIC PDF
Sach PIC PDF
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- S chn PIC18F4331
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- S lc tnh nng ni bt ca PIC18F4331
Ngun dao ng ni n 8MHz, dao ng thach anh ln ti 40MHz
Tiu th ngun thp (nanoWatt)
5 Knh vo ra (Port A, B, C, D, E)
ADC 10 - bit tc cao vi 9 knh vo (AN0 ~ AN8)
4 knh PWM 14-bit
Khi phn hi chuyn ng (Encoder)
2 knh CCCP
3 chn ngt ngoi
Giao tip ni tip RS232, RS485, I2C, SPI
ICSP v ICD
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- Cu trc bn trong vi iu khin PIC
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Cu trc v khi chc nng c bn trong Vi iu khin PIC
2.1 Khi to xung dao ng
Mch to dao ng c s dng cung cp xung ng h cho Vi iu khin.
Xung ng h l cn thit Vi iu khin c th thc thi chng trnh lp trnh bn
trong n. Mi loi Vi iu khin PIC h tr nhng kiu mach to dao ng khc nhau
nh mch dao ng thch anh (XT, HS), mch dao ng RC, mch dao ng ni, cc
ngun dao ng chun bn ngoi khc. Trong cc loi mch dao ng trn th mch dao
ng RC v mch dao ng thch anh l 2 loi thng hay c s dng, nht l mch
dao ng thch anh.
Mch dao ng thch anh (XT, HS): S mch dao ng thch anh di y l
mch dao ng ph bin cho PIC. y chnh l ngun cung cp xung ng h chnh cho
CPU v tt c cc khi trong PIC. Hai chn OSC1 (chn 13) v OSC2 (chn 14) c mc
vi mch dao ng thch anh bn ngoi. Cc in tr C1 v C2 l cn thit khi mc
mch dao ng thch anh cho PIC. Tr s ca chng xem bng di y.
u im ca mch ny l tn s dao ng chnh xc v cho tn s dao ng cao.
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decoded by a central processing unit. We can then select from the table of all
the instructions a set of actions which execute a assigned task defined by
instruction. As instructions may within themselves contain assignments
which require different transfers of data from one memory into another, from
memory onto ports, or some other calculations, CPU must be connected with
all parts of the microcontroller. This is made possible through a data bus and
an address bus.
Arithmetic logic unit is responsible for performing operations of adding,
subtracting, moving (left or right within a register) and logic operations.
Moving data inside a register is also known as 'shifting'. PIC16F84 contains
an 8-bit arithmetic logic unit and 8-bit work registers.
In instructions with two operands, ordinarily one operand is in work register
(W register), and the other is one of the registers or a constant. By operand
we mean the contents on which some operation is being done, and a register
is any one of the GPR or SFR registers. GPR is an abbreviation for 'General
Purposes Registers', and SFR for 'Special Function Registers'. In instructions
with one operand, an operand is either W register or one of the registers. As
an addition in doing operations in arithmetic and logic, ALU controls status
bits (bits found in STATUS register). Execution of some instructions affects
status bits, which depends on the result itself. Depending on which
instruction is being executed, ALU can affect values of Carry (C), Digit Carry
(DC), and Zero (Z) bits in STATUS register.
STATUS Register
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PIC16F84 has. RP1 bit is not used, but is left for some future expansions of
this microcontroller.
01 = first bank
00 = zero bank
bit 4 TO Time-out ; Watchdog overflow.
Bit is set after turning on the supply and execution of CLRWDT and SLEEP
instructions. Bit is reset when watchdog gets to the end signaling that
overflow took place.
1 = overflow did not occur
0 = overflow did occur
bit 3 PD (Power-down bit)
This bit is set whenever power supply is brought to a microcontroller : as it
starts running, after each regular reset and after execution of instruction
CLRWDT. Instruction SLEEP resets it when microcontroller falls into low
consumption mode. Its repeated setting is possible via reset or by turning
the supply off/on . Setting can be triggered also by a signal on RB0/INT pin,
change on RB port, upon writing to internal DATA EEPROM, and by a
Watchdog.
1 = after supply has been turned on
0 = executing SLEEP instruction
bit 2 Z (Zero bit) Indication of a zero result
This bit is set when the result of an executed arithmetic or logic operation is
zero.
1 = result equals zero
0 = result does not equal zero
bit 1 DC (Digit Carry) DC Transfer
Bit affected by operations of addition, subtraction. Unlike C bit, this bit
represents transfer from the fourth resulting place. It is set in case of
subtracting smaller from greater number and is reset in the other case.
1 = transfer occurred on the fourth bit according to the order of the result
0 = transfer did not occur
DC bit is affected by ADDWF, ADDLW, SUBLW, SUBWF instructions.
bit 0 C (Carry) Transfer
Bit that is affected by operations of addition, subtraction and shifting.
1 = transfer occurred from the highest resulting bit
0 = transfer did not occur
C bit is affected by ADDWF, ADDLW, SUBLW, SUBWF instructions.
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2.4
B nh RAM v cc ch nh a ch trong PIC
B nh Flash RAM
Bank v Thanh ghi iu khin vic truy cp b nh
Cc ch truy cp RAM (trc tip,gin tip)
Lp trnh truy cp b nh RAM
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2.4
T chc b nh ROM + EEPROM
2.4.1 B nh chng trnh Flash Program Memory
B nh chng trnh (sau y vit tt l b nh flash) l ni lu tr cc chng
trnh m ngi lp trnh vit ra, nhm lm cho PIC thc hin ng chc nng mong
mun. B nh flash l b nh va c th c, ghi v xa c trong qu trnh hot ng
ca PIC. Qu trnh c s thc hin c tng byte mi ln, qu trnh ghi vo b nh
thc hin theo mi khi 8 bytes cho mt ln ghi v vic xa b nh flash s thc hin
xa tng khi 64 bytes cho mi ln thc hin.
2.4.1.1 c ghi d liu gia b nh flash v RAM
thc hin vic c, ghi b nh flash, c hai hot ng cho php vi x l thc
hin vic di chuyn cc byte d liu gia b nh flash v b nh RAM l : Table
Read (TBLRD) v Table Write (TBLWR).
B nh chng trnh ca PIC c rng l 16-bit, trong khi b nh RAM l 8bit. Qu trnh thc hin c/ghi Table Read v Table Write c thc hin thng qua
mt thanh ghi 8-bit l TBLAT.
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2.4.1.2 Cc thanh ghi iu khin
C bn thanh ghi m nhn chc nng iu khin qu trnh trao i d liu vi
b nh Flash, l:
EECON1
EECON2
TABLAT
TBLPTR
Thanh ghi EECON1 v EECON2:
Thanh ghi EECON1 l thanh ghi iu khin vic truy cp b nh Flash v
EEPROM. Thanh ghi EECON2 khng phi l mt thanh ghi vt l, c EECON2 s lun
cho kt qu l 0. EECON2 c dnh ring cho vic ghi v xa b nh flash.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit6
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B nh EEPROM
Thanh ghi iu khin vic truy cp b nh
Lp trnh c d liu t EEPROM, F-ROM
Lp trnh ghi d liu vo EEPROM, F-ROM
Ch bo v (Code Protect)
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2.5 T chc vo/ra trong PIC
Gii thiu chung v cc cng vo/ra trong PIC: Cng l mt nhm cc chn ca Vi
iu khin, chng c th c truy cp ng thi hay theo tng bit mt, c trng thi
hin c trn cng. V mt vt l, mi cng l mt thanh ghi nm bn trong Vi iu khin
v c kt ni n cc chn ca Vi iu khin. Cng ng vai tr l mt kt ni vt l
gia CPU v th gii bn ngoi.
Physically, port is a register inside a microcontroller which is connected by wires to the
pins of a microcontroller. Ports represent physical connection of Central Processing Unit with
an outside world. Microcontroller uses them in order to monitor or control other components
or devices. Due to functionality, some pins have twofold roles like PA4/TOCKI for instance,
which is in the same time the fourth bit of port A and an external input for free-run counter.
Selection of one of these two pin functions is done in one of the configuration registers. An
illustration of this is the fifth bit T0CS in OPTION register. By selecting one of the functions
the other one is disabled.
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ghi ADCON1. Mc nh khi khi ng cc chn PORTA c thit lp l chn vo
tng t. Khi lp trnh ta cn ch iu ny.
PORTB v TRISB
PORTB c 8 chn t RB0 cho n RB7 tng ng vi rng l 8 bit. Thanh ghi
iu khin hng d liu ca PORTB c tn l TRISB cng c di l 8 bit, tng ng
vi 8 bit ca PORTB. Thit lp gi tri 1 cho mi bit trong thanh ghi TRISB s nh
ngha chn tng ng vi bit l chn vo d liu, v thit lp 0 cho mi bit trong
TRISB nh ngha chn tng ng l chn xut d liu.
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RBPU = 0;
port_buffer = PORTB;
// Kch hot in tr ko
// c gi tr ca PORTB vo bin port_buffer
Lp trnh ch ra (Output)
- Thit lp 0 cho cc bit ca thanh ghi TRISB
- Xut d liu ra cng (ghi gi tr vo thanh ghi PORTB)
V d:
TRISB = 0b00000000;
// PORTB l cng ra
PORTB = 0xAA;
// Xut gi tr 0xAA ra cng B
Trn y ch l hai v d nh v lp trnh vo ra cho PIC, bi lp trnh chi tit s
c trnh by cui chng.
Trong cc chn ca PORTB, 4 chn t RB4 n RB7, ngoi chc nng l chn vo
ra, chng cn sinh ra ngt gi l ngt On-Change. Ngt s xy ra khi ti cc chn c
s chuyn trng thi t logic 1 sang 0 hay ngc li. Chi khi c 4 chn ny c thit lp
ra chn vo th ngt mi xy ra (nu mt trong cc chn RB7 ~ RB4 l chn vo th ngt
khng xy ra khi c s chuyn trng thi trn cc chn ). Ta thng ng dng ngt
On-Change ny trong vic qut ma trn bn phm, khi cc hng ca phm c ni n
4 chn ny, vic x l ngt s xc nh phm no c nhn.
Ngoi ra PORTB cn c chn RB0 l chn vo ngt ngoi (INT0), cc chn RB7PGD, RB6-PGC, RB3-PGM c kt hp khi s dng tnh nng In-Circuit Debugger v
Low-Voltage Programming.
PORTC v TRISC
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2.6 Timer/Counter
M t chung v Timer (cu trc)
Cc b Timer l thnh phn khng th thiu trong mi con Vi iu khin, n cn
thit cho vic xc nh chnh xc mt khong thi gian tri qua.
Cc b Timer trong PIC (0,1,2)
Mi Vi iu khin PIC c mt s lng cc b Timer nht nh, ti thiu l 3 b
Timer l Timer0, Timer1, Timer2. Trong Timer0 v Timer2 l 8 bit, cn Timer1 la 16
bit.
Thanh ghi iu khin
Tnh ton thi gian cho Timer
Lp trnh cho mt b Timer
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