Appendix A SIC/XE Instruction Set and Addressing Modes Instruction Set In the following descriptions, uppercase letters refer to specific registers. The notation m indicates a memory address, n indicates an integer between 1 and 16, and rl and r2 represent register identifiers. Parentheses are used to denote the contents of a register or memory location, Thus A ¢ (m..2m+2) specifies that the contents of the memory locations mt through m+2 are loaded into register A; m..m+2 < (A) specifies that the contents of register A are stored in the word that begins at address m. The letters in the Notes column have the following meanings: P Privileged instruction X Instruction available only on XB version F Floating-point instruction « C Condition code CC set to indicate result of operation (<, =, ot >) ‘The Format column indicates which SIC/XE instruction format is to be iised in assembling each instruction; 3/4 means that either Format 3 or Format 4 can ‘be used. All instructions for the standard version of SIC are assembled using the format described in Section 1.3.1 (which is compatible with Format 3). Instruction subfields that are not required, such as the address field for an. RSUB instruction, are set to zero. 495Appendix A” SIC Instruction Set and Addressing Modes Mnemonic ADD m ADDF m ADDR 11,2 AND m CLEAR ri COMP m COMPF m COMER 11,12 DIV m DIVE m DIVR rix2 FIX FLOAT HIO Im JEQ m JGT m JET m JSUB m LDA m LDB m LDCH m LDF m LDL m LDS m LDT m LDX m LPS m MUL m Format 3/4 3/4 2 3/4 2 3/4 3/4 2 3/4 Opeode BENS ARSSSSSSESRLSRFSSRRERERREESAB Effect At (A) + (mand) | Fe (f+ (mms) XE 2 (2)+ (71) x A& (A) & (m.m42) rleO x | (A): @m.m+2) c | ): (nms5) XFC i (1): 2) xc Ac (A) / (m.ms2) Fe @)/ (mms) XF 12+ (2) / (1) x Ae @®) [convert tointeger] XF Fe(A) [converttofioating} XF Halt1/O channel number (A) PX PCem PC emi CC set to= PCe mif CC set to> PC emif CCéetto< Le PO; PCem Ae (mami2) Be (m.m+2) x A rightmost byte] <— (m) Fe (mms) XF Le (mmi2) Se (m.mi2) x T<(m.mi2) x X<(m.ms2) Load processor status from PX information beginning at address m (see Section 6.2.1) Ae (A)* (n.me2)Instruction Set Ninemonic Format Opcode _Effect Notes MULF m 3/4 0 Fe @)* (m.ms5) XE MULR r1x2 2 98 12. (12) * (r1) x NORM 1 8 F< (F) [normalized] a OR m 3/4 “ Ae (A) | (mm42) RDm 3/4 D8 Alrightmost byte] «data P from device specified by (m) RMO 1x22 AC Rec) RSUB 3/4 ac Pce (Ll) SHIFTL rn. 2 AS t1¢ (rl); left circular shift X nbits. {In assembled instruction, 12=n-1} SHIFIR rin 2 AS 11 (¢l);right shiftnbits, =X with vacated bit positions set equal to leftmost bit of (r1). {in assembled instruction, r2=n-l} so 1 FO Start I/O channel number (A); PX address of channel program is given by (6) SSK m 3/4 BC Protection key for addressm PX + (A) (see Section 6.2.4) STA m 3/4 oc m.mi2<-(A) STB m 3/4 6 m.m+2.< (B) x STCH m 3/4 54 m€ (A) [rightmost byte] STF m 3/4 80 mumt5 € (F) F XF STI m 3/4 Dt Interval timer value PX (m..m#2) (see Section 6.2.1) STL m 3/4 4 mumt2 (1) STS m 3/4 7 m.mi2& (8) x STSW m 3/4 ES m.mt2 — (SW) P SIT m 3/4 84 muni2¢ (1) x SIX m 3/4 10 mame SUB m 3/4 1c Ae (A)=(m.m+2) SUBF m 3/4 5c Fe ()—(m.mt5) XFAppendix A SIC Instruction Set and Addressing Modes Mnemonic Format Opcode _Effect Notes SUBR riz2 2 94 2e(2)-(e) x SVC n 2 BO Generate SVCinterrupt. fn X assembled instruction, rl =n} Mm 3/4 EO ‘Test device specified by(m) P ci TIO 1 FS ‘Test I/O channel number (A) PX C ™m 3/4 2c X ©0041; 00: (m.n42) c TDR rl 2 BB Xe) +1; 0: @1) xc WD m 3/4 pe Device specified by (an) (A) P [rightmost byte] Instruction Formats Format 1 (1 byte): . Format 2 (2 bytes): 8 4 4 * [acinomae | Format 3 (8 bytes): 6 4444 20 Addressing Modes The following addressing modes apply to Format 3.and 4 instructions. Combinations of addressing bits not included in this table are treated as errors by the machine. In the description of assembler language notation, ¢ indicates a constant between 0 and 4095 (or a memory address known to be in this range); m indicates a memory address or a constant value larger than 4095. Further information can be found in Section 1.3.2.Addressing Modes 499 | The letters in the Notes column have the following meanings: 4 Format4 instruction D __Ditect-addressing instruction ‘A Assembler selects either program-counter relative or base-relative mode S Compatible with instruction format for standard SIC machine. Operand value can be between 0 and 32,767 (see Section 1.3.2 for details). Assembler Calculation Addressing Flagbits language _of target type nixbpe notation address TA Operand Notes Simple 110000 ope _— disp (tay D \ 110001 +opm addr (TA) 4D 110010 opm. PC) +disp may A 110100 opm —(B) + disp (tA) A 111000 © opcX — disp +00 (TA) D 111001 +op mX addr +(X) (TA) 4D 111010 = opmxX_ (PC) +disp +(X) (TA) A 111100 opmX (B)+disp+(%)_ (TA) A 000--- - opm _b/p/e/disp (TA) Ds 001--- op mX b/p/e/disp + (X) (TA) Ds Indirect 100000 op @c — disp (mA) oD 100001 +op @m addr (ma) 4D 100010 op@m (PC) +disp «qma)) A | 100100 op @m (8) +disp (ma) A | Immediate 010000 op fe disp TA D \ 010001 +op#m addr TA 4D i 010010 op#m (PC) +disp TA A 010100 op #m B) +disp TA A eee