SS crpnesss PERFORM Features sm High Speed Oba t2ns ‘= Low Active Power leg = 250 mA at 12s ‘= Low CMOS Standby Power Olega = 50 mA, 1 Operating Voltages of 3.3 £03 V = 2.0 V Data Retention ‘= Automatic Powor Down when Deselected ‘= TTL Compatible Inputs and Outputs 1 Available in Pb-troe 48-ball FBGA Package Logic Block Diagram CY7C1079DV33 2-Mbit (4 M x 8) Static RAM Functional Description ‘The CY7C1079DV33 is @ high performance CMOS Static RAM organized as 4,194,304 words by 8 bits. ‘Towtite to the device, take Chip Enable (CE) and Write Enable (WE) input LOW. Data on the eight VO pins (VO, through VWO>) 's then writen into the location specified on the address pins (Ap through Az). ‘To read from the device, take Chip Enable (CE !"h LOW. Output Enable (OE) LOW while forcing the Write Enable ich Under these condtons, the cotets of the memory location specified by the address pins appear on the VO pins. See Truth Table (Single Chip Enable) on page & for a complete ‘description of Read and White modes. ‘The input and output pins (VOp through VO) are placedin a high pedance state when ha devi is deselacied (C= '” HIGH. the outputs are disabled (OE HIGH), or during a write operation (Cet Swans We LOW, ‘The CY7C107@DV33 is available in a 48-ball FEGA package. zerrezez72z a ¢ we g +>10)-10; y 3 ceases rr ES = Lew * benseertere Sesto SSS rr tt = en Et era ge cnn Ee Cypress Semiconductor Corporation 198Champlon Coun = SanJose, CA 651941700 + 408-4s-2000 Document Number: 001-50282 Rev. *D Revised April 27, 2011 (+1 FoodtackSires CY7C1079DV33 Document Number: 001-50282 Rew. *D Page 2014 Lo) FeedbackBirvcs CY7C1079DV33 Selection Guide Description en Tait Mamma Access Time 7 [Maximum Operating 250) ma [Maximum CMOS Standby Curent 3 mA Pin Configuration Figure 4. 48-ball FBGA (Single Chip Enable) 123 4 6 6 SOOOSS OOOO®S | OOGOHS | OOOO "Nc pins a not connec the Page sot 14