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BRIO E LABS


 
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a OS Gate Design
Pass Transistors
a OS Latches & Flip-Flops
Standard aell Layouts
Stick Diagrams

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a









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Activity:
Sketch a 4-input a OS NAND gate

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a









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Activity:
Sketch a 4-input a OS NOR gate

A
B
a
D
Y

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a






 


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aomplementary a OS logic gates

n OS

 

p OS

  

inputs
a.k.a. static a OS

Pull-up OFF

Pull-up ON

Pull-down OFF Z (float)

Pull-down ON

X (crowbar)

a

 

a



p OS
pull-up
network

output
n OS
pull-down
network




 
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n OS: 1 = ON
p OS: 0 = ON

 : both must be ON




: either can be ON

a
g1
g2

OFF

OFF

ON

b
(b)

a
g2

(c)

a
g1

g2
b

(d)

a



ON

OFF

OFF

OFF

a

 

b
OFF

g1

(a)

g2

g1

OFF

ON

ON

ON

ON

ON

ON

OFF




  
  

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aomplementary a OS gates always produce 0 or 1

Ex: NAND gate
Series n OS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Y
Requires parallel p OS
A

Rule of a  a


Pull-up network is complement of pull-down
Parallel -> series, series -> parallel

a

 

a






  

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a   can do any inverting function

Ex: Y = ( . + C. )
C

(a)

( )
C

C
(c)

(d)

C
Y

(f)
(e)

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a






j |
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Y = ((A+B+a).D)

a

 

a






j |
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Y = ((A+B+a).D)

A
B
a

D
Y
D

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  of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
n OS pass strong 0
But degraded or weak 1
p OS pass strong 1
But degraded or weak 0
Thus n OS are best for pull-down network

a

 

a






 

Transistors can be used as switches

a

 

a






 

Transistors can be used as switches

In ut
s

stron

de raded
In ut

ut ut

de raded

stron

a

 

ut ut

a






  


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M

Pass transistors produce degraded outputs

    pass both 0 and 1 well

a

 

a






  


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Pass transistors produce degraded outputs

    pass both 0 and 1 well

Input
g
a

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
b
gb

a

 

g
b

gb

Output

b
gb

a










  
produces Z when not enabled

EN

EN

EN
Y

A
EN

a

 

a










  
produces Z when not enabled

EN

EN
Y

EN
Y

A
EN

a

 

a






 
 


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Transmission gate acts as tristate buffer

Only two transistors
But 
 

Noise on A is passed on to Y

N
A

Y
N

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Tristate inverter produces restored output

Violates conduction complement rule
Because we want a Z output
A
EN
Y
EN

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Tristate inverter produces restored output

Violates conduction complement rule
Because we want a Z output
A

A
EN
Y

EN = 0
Y = 'Z'

EN = 1
Y=A

EN

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a








 
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2:1 


chooses between two inputs
S

D1

D0

a

 

D0

0
Y

D1

a








 
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2:1 multiplexer chooses between two inputs

S

D1

D0

a

 

a



D0

0
Y

D1





! 
 
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o



 




How many transistors are needed?

a

 

a







! 
 
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o

How many transistors are needed? 20

D1
S
D0

D1
S
D0
a

 

2
4

a






  



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Nonrestoring mux uses two transmission gates

a

 

a






  



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Nonrestoring mux uses two transmission gates

Only 4 transistors

S
D0
Y

S
D1
S
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a






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Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter

D0
S

S
D1

D0

D1

S
Y

Y
S

D0

S
D1

a

 

a



0
1




"

 
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4:1 mux chooses one of 4 inputs using two selects

a

 

a






"

 
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4:1 mux chooses one of 4 inputs using two selects

Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
Or four tristates
D0
S0
D0

S1

0
D1

D1

0
Y

Y
D2

D3

1
D2

D3

a

 

a








Ahen aLK = 1, latch is


D flows through to Q like a buffer
M Ahen aLK = 0, the latch is 

Q holds its old value independent of D
M a.k.a.

 
 or

   

M

C
tc

a

 

a








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ultiplexer chooses D or old Q

aLK

aLK

Q
Q

0
aLK

aLK

aLK

a

 

a









Q
D

aLK = 1

Q
D

aLK = 0

aLK

D
Q
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a






#!$
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Ahen aLK rises, D is copied to Q

At all other times, Q holds its value
a.k.a.   



,  






a

 

a






#!$
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Built from master and slave D latches

C

C
C
C

atch

C
atch

a

 

a






#!$

D

aLK = 0

aLK = 1

aLK

D
Q

a

 

a






O  

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Back-to-back flops can malfunction from clock skew

Second flip-flop fires late
Sees first flip-flop change and captures its result
aalled 
  

 or
 
aLK1
aLK2
Q1

Flop

Flop

aLK1

aLK2
Q2

Q1
Q2

a

 

a






    %
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M

Nonoverlapping clocks can prevent races

As long as nonoverlap exceeds clock skew
Ae will use them in this class for safe design
Industry manages skew more carefully instead

M

a

 

a









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Layout can be very time consuming

Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
n OS at bottom and p OS at top
All gates include well and substrate contacts

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j 
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Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates
etal1 VDD rail at top
etal1 GND rail at bottom
32 by 40

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a







%
M

  
 help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers

a

 

a






A %
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A 

 is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track

a

 

a






A 
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Aells must surround transistors by 6

Implies 12 between opposite transistor flavors
Leaves room for one wire track

a

 

a






j


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Estimate area by counting wiring tracks

ultiply by 8 to express in

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a






j |
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Sketch a stick diagram for O3AI and estimate area

Y = ((A+B+a).D)

a

 

a






j |
M

Sketch a stick diagram for O3AI and estimate area

Y = ((A+B+a).D)

a

 

a






j |
M

Sketch a stick diagram for O3AI and estimate area

Y = ((A+B+a).D)

a

 

a