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Description
Applications
Schematics
Package Outlines
8 VCC
N/C 1
8 VCC
+ 1
VF1
+ 2
7 VE
_ 2
6 VO
7 V01
VF
_
V
5 GND
N/C 4
6N137
HCPL2601
HCPL2611
6 V02
8
1
F2
5 GND
+ 4
HCPL2630
HCPL2631
Enable
Output
NC
NC
H
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
January 2011
Symbol
Parameter
Value
Units
TSTG
Storage Temperature
-55 to +125
TOPR
Operating Temperature
-40 to +85
TSOL
C
mA
EMITTER
IF
DC/Average Forward
Single Channel
50
Input Current
30
VE
Single Channel
5.5
VR
Each Channel
5.0
PI
Power Dissipation
Single Channel
100
mW
45
DETECTOR
Supply Voltage
VCC
(1 minute max)
7.0
50
mA
IO
Output Current
50
VO
Output Voltage
Each Channel
7.0
PO
Collector Output
Single Channel
85
mW
Power Dissipation
60
Single Channel
*For peak soldering reflow, please refer to the Reflow Profile on page 11.
Symbol
Parameter
Min.
Max.
Units
IFL
250
IFH
*6.3
15
mA
VCC
4.5
5.5
VEL
0.8
VEH
2.0
VCC
TA
-40
+85
*6.3mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0mA or less.
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Parameter
Test Conditions
Min.
Typ.*
Max.
Unit
1.8
EMITTER
VF
IF = 10mA
BVR
IR = 10A
CIN
Input Capacitance
VF = 0, f = 1MHz
IF = 10mA
ICCH
Single Channel
10
Dual Channel
10
15
ICCL
Single Channel
VCC = 5.5V,
IF = 10mA
13
Dual Channel
VE = 0.5V
IEL
IEH
VEH
TA = 25C
VF / TA
1.4
1.75
5.0
V
60
pF
-1.4
mV/C
DETECTOR
VEL
mA
mA
14
21
-0.8
-1.6
mA
-0.6
-1.6
mA
2.0
(3)
0.8
Switching Characteristics (TA = -40C to +85C, VCC = 5V, IF = 7.5mA unless otherwise specified)
Symbol
TPLH
TPHL
AC Characteristics
Test Conditions
Propagation Delay
Time to Output HIGH
Level
RL = 350,
CL = 15pF(4) (Fig. 12)
Propagation Delay
Time to Output LOW
Level
TA = 25C(5)
TA = 25C
Min.
Typ.*
20
45
Max. Unit
75
ns
100
25
45
75
ns
100
3
35
ns
tr
RL = 350, CL = 15pF
(Fig. 12)
50
ns
tf
12
ns
tELH
Enable Propagation
Delay Time to Output
HIGH Level
20
ns
tEHL
Enable Propagation
Delay Time to Output
LOW Level
20
ns
Common Mode
Transient Immunity
(at Output HIGH Level)
10,000
V/s
Common Mode
Transient Immunity
(at Output LOW Level)
|CMH|
|VCM| = 400V
|CML|
HCPL2611
|VCM| = 400V
HCPL2611
5000
10,000
10,000
15,000
V/s
10,000
5000
10,000
10,000
15,000
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3
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
DC Characteristics
Test Conditions
Min.
Typ.*
Max.
Unit
100
IOH
VOL
.35
0.6
IFT
mA
Max.
Unit
1.0*
Characteristics
Test Conditions
Min.
Typ.*
Input-Output Insulation
Leakage Current
VISO
RI-O
VI-O = 500V(12)
1012
1MHz(12)
0.6
pF
CI-O
f=
2500
VRMS
1. The VCC supply to each optoisolator must be bypassed by a 0.1F capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Each channel.
3. Enable Input No pull up resistor required as the device has an internal pull up resistor.
4. tPLH Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tr Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., VOUT > 2.0V). Measured in volts per microsecond (V/s).
11. CML The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., VOUT < 0.8V). Measured in volts per microsecond (V/s).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Conditions:
IF = 5 mA
VE = 2 V
VCC = 5.5V
0.7
0.6
IOL = 12.8 mA
0.5
IOL = 16mA
0.4
0.3
IOL = 6.4mA
0.2
IOL = 9.6mA
0.1
30
16
10
0.1
0.01
0.001
0.0
-40
-20
20
40
60
80
0.9
1.0
1.1
VCC = 5 V
100
RL = 4 k (TPLH)
80
60
RL = 1 k (TPLH)
40
RL = 350 (TPLH)
RL = 1 k
RL = 4 k (TPHL)
RL = 350 k
11
13
15
50
1.5
1.6
IF = 15mA
IF = 10mA
40
IF = 5mA
35
30
Conditions:
VCC = 5 V
VE = 2 V
VOL = 0.6 V
25
20
-40
-20
20
40
60
80
Conditions:
VCC = 5.0 V
VO = 0.6 V
1.4
45
1.3
20
1.2
3
RL = 350
RL = 1k
2
RL = 4k
5
RL = 350
4
RL = 4k
RL = 1k
1
-40
0
-20
20
40
60
80
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
80
60
Conditions:
IF = 7.5mA
VCC = 5A
40
20
RL = 1 k
-60
RL = 350
-40
-20
20
40
60
80
RL = 4 k (tr)
500
400
Conditions:
IF = 7.5 mA
VCC = 5 V
300
200
RL = 1 k (tr)
100
RL = 350 (tr)
-60
100
-40
-20
TA TEMPERATURE (C)
40
60
20
80
100
(tf)
TA TEMPERATURE (C)
120
100
RL = 4 k (TELH)
80
60
40
RL = 1 k (TELH)
RL = 350 (TELH)
20
0
-60
RL = 1 k
RL = 4 k
RL = 350
RL = 350
RL = 1 k
RL = 4 k
-40
-20
20
40
60
RL = 4 k TPLH
100
80
60
RL = 1 k TPLH
40
RL = 350 TPLH
RL = 1 k
RL = 4 k
RL = 350
(TEHL)
80
20
-60
100
-40
-20
TA TEMPERATURE (C)
20
40
60
TPHL
80
100
TA TEMPERATURE (C)
15
10
0
-60
-40
-20
20
40
60
80
100
TA TEMPERATURE (C)
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Pulse
Generator
tr = 5ns
Z O = 50
+5V
IF = 7.5 mA
VCC
IF = 3.75 mA
Input
(IF )
Output
(VO )
t PHL
2
Input
Monitor
(I F)
.1 f
bypass
RL
Output
(VO )
CL
47
GND
tPLH
1.5 V
90%
Output
(VO )
10%
5
tf
tr
Pulse
Generator
tr = 5ns
Z O = 50
Input
Monitor
(V E)
+5V
3.0 V
Input
(VE )
VCC
1.5 V
t EHL
7.5 mA
.1 f
bypass
RL
1.5 V
Output
(VO )
t ELH
Output
(VO )
CL
GND
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7
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits
VCC
IF
A
+5V
.1 f
bypass
350
B
VFF
GND
Output
(VO)
VCM
Pulse Gen
Peak
VCM
0V
CM H
5V
Switching Pos. (A), IF = 0
VO
VO (Min)
VO (Max)
Switching Pos. (B), I F = 7.5 mA
VO
0.5 V
CM L
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8
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Option
Description
6N137S
SD
6N137SD
6N137W
6N137V
VDE0884
WV
6N137WV
SV
6N137SV
SDV
6N137SDV
Marking Information
1
V
3
2601
XX YY T1
Definitions
1
Fairchild logo
Device number
VDE mark (Note: Only appears on parts ordered with VDE option
See order entry table)
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9
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Ordering Information
12.0 0.1
4.90 0.20
4.0 0.1
1.55 0.05
4.0 0.1
0.30 0.05
1.75 0.10
7.5 0.1
13.2 0.2
10.30 0.20
1.6 0.1
10.30 0.20
0.1 MAX
16.0 0.3
Reflow Profile
Temperature (C)
300
215 C, 1030 s
250
225 C peak
200
150
100
50
Ramp up = 3C/sec
0
0
0.5
1.5
2.5
3.5
4.5
Time (Minute)
Peak reflow temperature: 225C (package surface temperature)
Time of temperature higher than 183C for 60150 seconds
One time soldering reflow is recommended
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers
Tape Specifications
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Build it Now
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Advance Information
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Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
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The datasheet is for reference information only.
Rev. I77
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