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current
next
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input state

#
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A/0
reset

0
1

D/1

1
0
0
0
0
0
0
0
0

B/0

C/0

A
A
B
B
C
C
D
D

0
1
0
1
0
1
0
1

current
output

A
A
B
A
C
A
D
A
D

0
0
0
0
0
0
0
1
1

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reset

D/1
1

1,
78

current
next
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input state

B/0

1
0
1

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0
A/0

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1
0
0
0
0
0
0
0
0

00
00
01
01
10
10
11
11

0
1
0
1
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1
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00
00
01
00
10
00
11
00
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current
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0
0
0
0
0
0
0
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1

9'8

78

MSB+ = LIn + MIn

LSB+ = L'In + MIn

Out+ = ML

Notation
M := MSB
L := LSB
In := Input
2

2, #

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MSB+ = LIn + MIn

AND2

PRN

MSB

CLRN

OR2

Out+ = ML

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PRN

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51

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44

In

Out

53

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In
MSB 52

AND2

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45

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47

48
41

LSB

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MSB 43
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Clock

42

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&
:

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present
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0

Reset

&
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&

inputs
D N
0 0
0 1
1 0
1 1
0 0
0 1
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10

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15

next
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5
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5
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15

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15
15

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0
0

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3

present state inputs

Q0 Q1
D N
0 0
0 0
0 1
1 0
1 1
0 1
0 0
0 1
1 0
1 1
1 0
0 0
0 1
1 0
1 1
1 1

next state present

P1 P0
output
0 0
0
0 1
0
1 0
0

0 1
0
1 0
0
1 1
0

1 0
0
1 1
0
1 1
0

1 1
1

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K-map for P1

K-map for P0

Q1Q0
Q1
DN 00 01 11 10
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01 0 1

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11 X X

X X

10 1 1

1 1

2, #
K-map for Open

Q1Q0
Q1
DN 00 01 11 10
00 0 1 1 0
N
D

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1 1

11 X X

X X

10 0 1

1 1

Q0

Q1Q0
Q1
DN 00 01 11 10
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N
D

01 0 0

1 0

11 X X

X X

10 0 0

1 0

Q0

P1 = Q1 + D + Q0N

Q0

if FFs do not have a reset pin then

A BC 83 8C <

P0 = Q0'N + Q0N' + Q1N + Q1D

P1 = reset'(Q1 + D + Q0N)

OPEN = Q1Q0

P0 = reset'(Q0'N + Q0N' + Q1N + Q1D)

A BC D
< 8 C <D8 C < 8 C 3
A < BC C
1

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A <

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Reset

Reset

A < BC C B/
C 838C <0
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C D
<8C <D
8C <8C 30
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D

0
[0]
N

N'D'

5
[0]
N

N'D'

10
[0]
N+D

N'D'

N'D'/0

N/0
5

D/0

N'D'/0

N/0
10

D/1

N'D'/0

N+D/1

15
[1]

/1

15

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40

always @(in or state)

`define zero 0
`define one1 1
`define two1s 2

case (state)
`zero:
// last input was a zero
begin
if (in) next_state = `one1;
else
next_state = `zero;
end
`one1:
// we've seen one 1
begin
if (in) next_state = `two1s;
else
next_state = `zero;
end
`two1s:
// we've seen at least 2 ones
begin
if (in) next_state = `two1s;
else
next_state = `zero;
end
endcase

module reduce (clk, reset, in, out);

input clk, reset, in;
output out;
reg out;
reg [2:1] state;
// state variables
reg [2:1] next_state;
always @(posedge clk)
if (reset) state = `zero;
else
state = next_state;

.
?@

?@

?@

*
#

always @(state)
case (state)
`zero: out = 0;
`one1: out = 0;
`two1s: out = 1;
endcase
endmodule

!+

*)

module reduce (clk, reset, in, out);

input clk, reset, in;
output out;
reg out;
reg state;
// state variables
reg next_state;
always @(posedge clk)
if (reset) state = `zero;
else
state = next_state;
always @(in or state)
case (state)
`zero:
// last input was a zero
begin
out = 0;
if (in) next_state = `one;
else
next_state = `zero;
end
`one:
// we've seen one 1
if (in) begin
next_state = `one; out = 1;
end else begin
next_state = `zero; out = 0;
end
endcase
endmodule

module reduce (clk, reset, in, out);

input clk, reset, in;
output out;
reg out;
reg state; // state variables
always @(posedge clk)
if (reset) state = `zero;
else
case (state)
`zero:
// last input was a zero
begin
out = 0;
if (in) state = `one;
else
state = `zero;
end
`one:
// we've seen one 1
if (in) begin
state = `one; out = 1;
end else begin
state = `zero; out = 0;
end
endcase
endmodule

#
!