Lab 4

EXPERIMENT 1
AIM: To implement binary to grey code convertor
TRUTH TABLE: Binary to Grey Code
X0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

X1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

X2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

X3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Y0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Y1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

Y2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity grey2bin is
port(x0,x1,x2,x3: in STD_LOGIC;y0,y1,y2,y3: out STD_LOGIC);
end grey2bin;
architecture Behavioral of grey2bin is
begin
process(x1,x2,x3,x0)
begin
y0 <= x0 XOR x1;
y1 <= x1 XOR x2;
y2 <= x2 XOR x3;
y3 <= x3;
end process;
end Behavioral;
OUTPUT

Y3
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

EXPERIMENT 2

AIM: To implement grey to binary code convertor

TRUTH TABLE: Grey Code to Binary

X0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

X1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

X2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

X3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Y0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Y1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

Y2
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1

CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity abcd is
port(x0,x1,x2,x3: in STD_LOGIC;y0,y1,y2,y3: out STD_LOGIC);
end abcd;
architecture Behavioral of abcd is
begin
y3 <= x3;
y2 <= x3 xor x2;
y1 <= x3 xor x2 xor x1;
y0 <= x3 xor x2 xor x1 xor x0;
end Behavioral;

OUTPUT

Y3
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0

EXPERIMENT 3

AIM: To implement SR Flip Flop

TRUTH TABLE: SR Flip Flop
S
0
0
1
1

R
0
1
0
1

CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity srflipflop is
port(clk,s,r: in STD_LOGIC;q: out STD_LOGIC);
end srflipflop;
architecture Behavioral of srflipflop is
begin
srprocess: process(clk) is
variable p: STD_LOGIC:='X';
begin
if(clk='1') then
if(s='1' and r='1') then
q <= 'X';p:='X';
elsif (s='1' and r='0') then
q <= '1';p:='1';
elsif (s='0' and r='1') then
q <= '0';p:='0';
elsif (s='0' and r='0') then
q<=p;
else
q<='X';p:='X';
end if;
end if;
end process srprocess;
end Behavioral;
OUTPUT

Qn+1
Qn
0
1
X