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Slva079 PDF
Slva079 PDF
ABSTRACT
This report provides an understanding of the terms and definitions of low dropout (LDO)
voltage regulators, and describes fundamental concepts including dropout voltage,
quiescent current, standby current, efficiency, transient response, line/load regulation, power
supply rejection, output noise voltage, accuracy, and power dissipation. Each section
includes an example to increase the understandability.
Contents
1
Dropout Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quiescent Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10
11
Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12
13
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Figures
1
2
3
4
5
6
7
8
2
2
3
4
5
6
6
7
1
SLVA079
Dropout Voltage
Dropout voltage is the input-to-output differential voltage at which the circuit ceases to regulate
against further reductions in input voltage; this point occurs when the input voltage approaches
the output voltage. Figure 1 shows a typical LDO regulator circuit. In the dropout region, the
PMOS pass element is simply a resistor, and dropout is expressed in terms of its on-resistance
(Ron).
V
dropout
+ IoRon
(1)
V dropout _
+
Ii
OUT
IN
Io
LDO
Co
Vi
GND
Vo
CSR
Dropout Voltage:
_
V dropout =Io XR on
3.3
off
regulation region
region
dropout
voltage
0
2.0
3.6
10
SLVA079
Quiescent Current
Io
Ii
IN
OUT
+
LDO
Co
Vi
GND
CSR
Iq
Vo
_
Quiescent Current::
I q = I i Io
+ Ii * Io
(2)
Quiescent current consists of bias current (such as band-gap reference, sampling resistor, and
error amplifier currents) and the gate drive current of the series pass element, which do not
contribute to output power. The value of quiescent current is mostly determined by the series
pass element, topologies, ambient temperature, etc.
For bipolar transistors, the quiescent current increases proportionally with the output current,
because the series pass element is a current-driven device. In addition, in the dropout region the
quiescent current can increase due to the additional parasitic current path between the emitter
and the base of the bipolar transistor, which is caused by a lower base voltage than that of the
output voltage. For MOS transistors, the quiescent current has a near constant value with
respect to the load current since the device is a voltage-driven device. The only things that
contribute to the quiescent current for MOS transistors are the biasing currents of bandgap,
sampling resistor, and error amplifier. In applications where power consumption is critical, or
where small bias current is needed in comparison with the output current, an LDO voltage
regulator using MOS transistors is essential.
Standby Current
Standby current is the input current drawn by a regulator when the output voltage is disabled by
a shutdown signal. The reference and the error amplifier in an LDO regulator are not loaded
during the standby mode, as shown in Figure 4.
SLVA079
EN (high)
+
+
Is
V CC
Vi
Reference
V ref
V CC
V o =0[V]
GND
Standby current = I s
when output is disabled
Switch positions are shown with EN high (standby mode)
Efficiency
The efficiency of LDO regulators is limited by the quiescent current and input/output voltages as
follows.
Efficiency
)
I oV o
Io
Iq V
100
(3)
To have a high efficiency, drop out voltage and quiescent current must be minimized. In addition,
the voltage difference between input and output must be minimized, since the power dissipation
of LDO regulators accounts for the efficiency. (Power Dissipation = (Vi Vo)Io). The input/output
voltage difference is an intrinsic factor in determining the efficiency, regardless of the load
conditions.
Example:
1. What is the efficiency of the TPS76933 3.3-V LDO regulator with the following operating
conditions? Input voltage range is 3.6 V to 4.5 V. Output current range is 80 mA to
100 mA. The maximum quiescent current is 17 A. Then, the minimum efficiency is
obtained as follows:
Efficiency
mA @ 3.3 V
+ (100100
100 + 73.3 %
mA ) 17 A)4.5 V
2. What is the efficiency if input voltage range is 3.6 V to 4 V under the same conditions as
the above? The minimum efficiency is improved as follows:
Efficiency
V
+ (100100mAmA) @173.3A)4
100 + 82.5 %
V
SLVA079
Transient Response
The transient response is the maximum allowable output voltage variation for a load current step
change. The transient response is a function of the output capacitor value (Co), the equivalent
series resistance (ESR) of the output capacitor, the bypass capacitor (Cb) that is usually added
to the output capacitor to improve the load transient response, and the maximum load-current
(Io,max). The maximum transient voltage variation is defined as follows:
DVtr,max + C o,max
) C Dt1 ) DVESR
I
(4)
Where t1 corresponds to the closed loop bandwidth of an LDO regulator. VESR is the voltage
variation resulting from the presence of the ESR (RESR) of the output capacitor. The application
determines how low this value should be.
Io
IN
OUT
LDO
Vi
GND
C o=
4.7uF
Cb
ESR
Load
Ii
Vo
V tr,max
t1
Line Regulation
Line regulation is a measure of the circuits ability to maintain the specified output voltage with
varying input voltage. Line regulation is defined as
Line regulation
+ DDVVo
(5)
SLVA079
Io
IN
OUT
+
LDO
Vi
4.7uF
GND
ESR
Output Voltage
[V]
[V]
Input Voltage
Change of Input
Voltage
7
6
5
0
50
100
Time [us]
150
Load
Ii
Vo
Resultant
Output Voltage
3.340
VLR2
3.320
3.300
3.280
3.260
VL R1
0
50
100
Time [us]
150
1.244mV
3.3
Output Voltage
Variation
2.0
3.5
10
Load Regulation
Load regulation is a measure of the circuits ability to maintain the specified output voltage under
varying load conditions. Load regulation is defined as
Load regulation;
DVo
DIo
(6)
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Io
Ii
IN
OUT
+
LDO
GND
200
100
0
0
50
100
Time [us]
ESR
Output Voltage
Vo [V]
Output Current
I o [mA]
Step Change of
Load Current
Load
Vi
4.7uF
150
Vo
Resultant
Output Voltage
5.2
5.1
5.0
V LDR
4.9
4.8
50
100
Time [us]
150
5.0
4.97 5
4.9 5
30
60
90
120
150
180
Figure 9. TPS76350 LDO Regulator Output Voltage With Respect to Output Currents
SLVA079
IN
+
Vi
OUT
+
Vo
LDO
Co
Vi
V i,ripple
0
Vo, ripple
Vo
GND
CSR
Cb
0
time
time
Ripple Rejection:
PSRR =
Vo, ripple
at all frequencies
V i,ripple
PSRR [db]
0
20
40
60
10
100
1k
10k
100k
1M
10M
frequency
+ Vo,ripple
V
PSRR
at all frequencies
(7)
i,ripple
For example, supply rejection in the frequency band between 100 kHz and 1 MHz is especially
important in applications where the output of a dc/dc switch mode power supply (SMPS) is used
to power the linear regulator. The output ripple of the SMPS is typically in the aforementioned
frequency span. Thus, the figure above does not seem to show a good PSRR performance for
the SMPS applications over the frequency range (100 kHz to 1 MHz). The worst performance
(maximum point in the graph) occurs when RESR is large and Cb is low.
The control loop tends to be the dominant contributor of supply rejection. Low ESR value, a
large output capacitor, and added bypass capacitors improve the PSRR performance, provided
they meet the CSR requirement.
SLVA079
IN
OUT
+
LDO
Vi
Constant
Vi
Co
GND
input
CSR
0
Constant
Load
time
Vo
Vo
Vnoise,peak
0
time
100
IN
OUT
LDO
Vi
+
Co
GND
RESR
Output
Capacitor
Vo
Radd
_
CSR Compensation
Series Resistance
10
Region of Instability
10
Stable Region
Co=4.7uF
0.1
0.01
Region of Instability
0
50
100
150
Io Output Current mA
200
250
+ RESR ) Radd
(8)
An additional resistor can be used if the RESR is too small. An example of a typical stable range
of CSR values is shown in Figure 12. This curve is called tunnel of death. The curve shows that
CSR must be between 0.2 and 9 so that the LDO regulator is stable. Solid tantalum
electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided
they meet the CSR requirements.
SLVA079
Q1( )
+
+
R
+
Vi
Vo
Vs
RL
ga
_ Vref
_
R
_
Vref
11
Accuracy
The overall accuracy considers the effects of line regulation (VLR), load regulation (VLDR),
reference voltage drift (Vo,ref), error amplifier voltage drift (Vo,a), external sampling resistor
tolerance (Vo,r), and temperature coefficient (VTC). It is defined by
Accuracy
|DV
|
LR
) |DVLDR| )
100
(9)
The output voltage variation in a regulated power supply is due primarily to temperature variation
of the constant voltage reference source and temperature variation of the difference amplifier
characteristics, as well as the sampling resistor tolerance. Load regulation, line regulation, gain
error, and offsets normally account for 1 to 3% of the overall accuracy.
Example:
What is the total accuracy of the 3.3 V LDO regulator shown in Figure 13 over the temperature
span from 0 to 125 with the following operating characteristics; temperature coefficient is
100 ppm/C, sampling resistor tolerance is 0.25%, output voltage change resulting from load
regulation and line regulation are 5 mV, and 10 mV, respectively. The accuracy of the
reference is 1%.
The output voltage is given by
Vo
+ R )R R Vref + 2Vref
Therefore, the reference voltage Vref is half of the output voltage (i.e., Vref = 3.3/2[V]), and
DVTC + Temperature
Coefficient
T max
* Tmin @ Vo
+ 100ppmC(125C)(3.3 V) + 41.2 mV
DVo,r + 0.25% of Vo ) 0.25% of VoVref
+ (0.005)(3.3) 3.32 + 27 mV
V + 2 3.3 0.01 + 33mV, where V + V 0.01 +
DVo,ref + 2R
d
ref
2
R d
10
3.3 0.01
2
SLVA079
Accuracy
) 5mV )
(33mV)
3.3 V
T
* TA
Jmax
+
D(max)
R
(10)
qJA
Where
TJmax is the maximum allowable junction temperature.
RJA is the thermal resistance junction-to-ambient for the package, i.e., 285C/W for the
5-terminal SOT23.
TA is the ambient temperature.
+ Vi * Vo Io
(11)
TPS761xx and TPS769xx
0.3
6v 5v
input/output
7v
voltage 9v8v
difference
10V
4v
0.44
3v
2v
0.2
1v
0.1
0.3v
0
0.05
0.1
0.15
input/output
voltage
difference
10V
0.4
Power Dissipation (W)
0.44
Power Dissipation (W)
12
10mV
9v 8v 7v 6v
5v
4v
0.3
3v
0.2
2v
1v
0.1
0.3v
0
0.05
Output Current (A)
0.1
11
SLVA079
13
Summary
This application report described the terms and definitions of low dropout (LDO) voltage regulators,
and provided fundamental concepts.
12
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