1

TUTORIALS

1. INTRODUCTION TO GALOIS FIELD AND BCH CODES................................9

2.1

Block Codes............................................................................................... 9

2.2

Galois Field............................................................................................... .9

2.2.1

Roots of

Equation...10
2.2.2

Primitive Polynomials

2.2.3

GF (2^4)

2.3

Construction of binary BCH codes

10
12
13
3. ENCODER_LFSR DESIGN AND ARCHITECTURE FOR BCH CODE
15
3.1

BCH codes.15

3.1.1

Encoder_LFSR

Design...15
3.2

Encoder_LFSR Design

Architecture.17
3.2.1

Parallel to Serial Shift

Register..17
3.2.2
18

Encoder_LFSR Module Linear Feedback Shift Register(LFSR)..

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3.2.3

Serial to Parallel

Shifter..19
4. ENCODER_LFSR SIMULATION AND SYNTHESIS RESULT..22
4.1

Encoder_LFSR Simulation

Result.22
4.2

Encoder_LFSR Synthesis Result

4.2.1

Encoder_LFSR- Top module.

4.2.2

Parallel to Series

23
23
Shifter....25
4.2 .3

Linear Feedback Shift

Register..27
4.2.4

Series to Parallel

Shifter.29
Block Codes
Block codes are one of the types of channel codes. The definition of the block codes is,
these codes add the redundancy bits to the original message bits and transmit the resultant
longer information bits called codeword for error correction. Theoretically, it is
possible to decode the received codeword with zero possible error provided the coding
technique is subjected to Shannons channel capacity theorem. The block codes are
implemented as (n, k) codes where n indicates the codeword and the k defines the
original information bits. Therefore, the number of redundant bits need to be added in to
the original message bits are given as (n k). The block codes are fixed channel codes.

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The BCH codes and the Reed Solomon codes are the subset of the Block codes, which
are well defined as below. In this project, we had used BCH codes to design
Encoder_LFSR and Decoder [3].
1.1.1.1 BCH Codes
BCH codes are subset of the Block codes. BCH codes are belongs to a power full class of
multiple error correcting codes. BCH codes are based on well-defined mathematical
properties. These mathematical properties are based on the Galois Field or finite fields.
The Finite field has the property that any arithmetic operations on field elements always
have results in the field only. To provide an excellent error correcting capability, the
generator polynomial of the BCH codes has carefully specified roots. With a generator
polynomial of g(x), a t- error correcting cyclic codes is the binary BCH codes, with a
condition that g(x) must be the least degree polynomial over Galois Field GF(2). The
block length of the BCH code, constructed over GF (2^m) is given by n = 2^m 1. BCH
codes are cyclic codes, and the degree r of the generator polynomial of a (n, k) is given
by (n-k). So, the information bits length of the BCH codes is given by k = 2^m 1- r[1]
[2].
INTRODUCTION TO GALOIS FIELD AND BCH CODES
2.1 Block Codes
Block code is a set of words, which is called Codeword. In a Block codes the
Codeword is a combination of an information bits and parity bits. The information bits
are those bits which carries the message while parity bits provide security and ensure that

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the codeword has a correct structure required for the Block codes. Encoder_LFSR
generates the parity bits as well as concatenates them to the information bits. For k
information bits and r- parity bits the generated codeword n will be the sum of
information bits and parity bits, given as n= k + r.
This kind of codes is referred to as (n, k) block code. The position of the codeword is not
fixed, it could be placed at the beginning of the codes (MSB) or at the end of the
information bits (LSB). The codeword could be dispersed throughout the codeword.
There are two types of codeword called, systematic codes and non- systematic. The
codeword in which the information bits are kept together is called systematic codeword
while if the information bits are scattered is called non-systematic codeword. In (n, k)
block codes, k-bits give 2^k different codeword, there are therefore 2^k codeword in a (n,
k) code [1] [2].
2.2 Galois Field
The Galois field was invented by Everest Galois. Galois field has finite number of
elements in it. The theory of Finite field was introduced around 18th century, while its
importance and the widespread applications were widely recognized in recent years. The
Galois field is widely used in number theory, coding theory and cryptography. The
mathematical properties within which BCH codes are defined is also represents Galois
field. The mathematical operations like Additions, Subtractions, Multiplications and
Divisions are performed using Finite field theory. The most basic axioms of the finite
field are:
[1] All the elements in the field forms an Abelian group with additional operator +.

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[2] The non-zero elements in the field forms group with multiplication operator . .
[3] Multiplications by any non zero elements is an automorphism of the Additive group.
BCH codes architecture use field theory as well as polynomial over finite filed. To detect
any error has occurred during transmission a check polynomial is constructed. The BCH
code with distance over the finite field GF (q^m) is constructed by finding polynomial
over GF (q), whose roots include consecutive power of y [4] [6].
2.2.1Roots of Equation
The finite field can be calculated using roots of equation . This is possible because of
one of the property of cyclic codes. The cyclic code has a property that all the codeword
polynomials c(x) has the generator g(x) as a factor. In other words, any root of g(x) = 0,
also give a root of c(x) =0 [4] [6].
Primitive Polynomials
The irreducible polynomials are defined as those polynomials which are divisible of itself
and one and which cannot be factorized. Irreducible polynomials are used to generate GF
(2^m). The root of irreducible polynomial is called a primitive polynomial. is primitive
in GF(2^m) ; primitive is defined as the field element which can generate all non zero
elements of the field. Here, as the primitive element became the root of the irreducible
polynomials, so polynomials become primitive too. For any positive integer m we can get
at least one irreducible polynomial of the degree m. It can be shown that an irreducible
polynomial of degree m is divides by x^r +1 (where r = 2^m -1), which can be used to
find out whether polynomial is an irreducible or not. To build BCH codes over GF (2 4),

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we need to find out the minimal polynomials of powers of . The minimal polynomials of
all elements of GF (24) are given in table below [4].

Table 2.2.2.1 Field elements of GF (24) and Minimal Polynomials [4]

2.2.3 GF (2^4)
The main reason of constructing a GF (2^m) is that they do not have both 0 and 1 as their
roots. This section is provided with a detailed explanation of Galois field (2^4). Consider
the below equation,
P(x) = x4 + x + 1.

(2.1)

From the above equation, it is clear that, neither 0 nor 1 is the root for of the equation. So,
we can say that the 4th equation lies outside of the GF (2^4) field. By assuming as one

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of the root of the equation, p() should be equal to zero. This can be explained by below
equation,
P () = 4 + + 1 = 0

(2.2)

The above equation can be used to generate GF (24). Rearranging the above equation
gives,
4 = + 1

(2.3)

But multiplying to the above equation gives,

4 = + 1
5 = 4. = 2 +

(2.4)

6 = 5. = 3 + 2.

(2.5)

7 = 6. = 4 + 3

(2.6)

8 = 7. = 5 + 4 = 2 + 1

(2.7)

9 = 8. = 3 +
10 = 9. = 2 + + 1
11= 10. = 3 + 2 +

(2.8)
(2.9)
(2.10)

12= 11. = 3 + 2 + + 1

(2.11)

13 = 12. = 3 + 2 + 1

(2.12)

14 = 13. = 3 +1

(2.13)

The higher order field elements can be generated similarly by multiplying to its
previous power. The fifteenth power of can be calculate as below:
15 = 14. = 1.

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Here, the simplification of the fifteenth order gives 1, which is an existing element so;
further powers of will always give the existing elements. Therefore the field GF(2 4) has
the following 16 elements:
0, 1, , 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 [4].
2.3 Construction of binary BCH codes
The BCH code has carefully specified roots to give good error correcting capability. A terror correcting code with generator polynomial g(x) is a binary BCH code if and only if
g(x) is the least-degree polynomial over GF (2) that has,
, 2, 3, 2t
is an element of GF(2m). From above it is clear that with this choice of roots, the
resultant codes will be capable of correcting t error. The generator polynomial g(x) of a
t-error correcting binary BCH code is given by,
g(x) = LCM [ m1(x), m2(x), m3(x), ., m2t(x)]

(2.14)

According to above equation (2.14), the 3-error correcting BCH code for (15, 5) code is
considered. The generator polynomial with,, 2, 3, ... , 6 as the roots is obtained by
multiplying the following minimal polynomials:
Roots
, 2, 4, 8
3, 6, 9, 12
5 10

minimal polynomial
f1(x) = (x+) * (x+2) * (x+4) * (x+8) = 1 + x + x4
f3(x) = (x+3) * (x+6) * (x+12) * (x+9) = 1 + x + x2 + x3 + x4
f5(x) = (x+5) * (x+10) = 1 + x + x2
Table 2.3.1 (15, 5) - Minimal Polynomials [4]

The equation for the generator polynomial g(x) is given as below [4];
g(x) = f1(x) * f3(x) * f5(x) = 1 + x + x2 + x4 + x5 + x8 + x10.

(2.15)

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This chapter covers the detailed explanation about the Galois field and the Block codes. It
also covers the concept of primitive polynomial associated with the Galois field and also
it explained the construction of (15, 5) three error correcting BCH code. The following
chapter explains the BCH Encoder_LFSR design and architecture.

Chapter 3
ENCODER_LFSR DESIGN AND ARCHITECTURE FOR BCH CODE
3.1 BCH codes

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Fig 3.1.1 BCH Encoder_LFSR and Decoder

3.1.1 Encoder_LFSR Design
The Encoder_LFSR design used in this project is most commonly used in the modern
digital communication system. This encoder_LFSR design is almost common to all the
BCH code architecture, which uses the linear feedback shift register for polynomial
division.
The format of the codeword is as follows [4]:
c(x) = xn-k * i(x) + b(x)

(3.1)

Where, codeword c(x) = c0 + c1x +...+ cn-1xn-1

information bits i(x)= i0 + i1x +...+ ik-1xk-1
remainder b(x)= b0 + b1x +...+ bm-1xm-1
also, ci, ji, bi are the subsets of Galois field. If b(x) is taken to be the polynomial such
that the k data bits will be presented in the codeword, which is given as follows:
xn-k * i(x) = q(x) * g(x) - b(x)

(3.2)

BCH codes are implemented as cyclic code. As a result the logic which implements
encoder_LFSR and decoder is controlled into shift register circuits. With the help of

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cyclic code properties the remainder b(x) can be calculated in the linear (n-k) stage shift
register with the feedback connection to the coefficient of generator polynomial.

Fig 3.1.1.1 Encoding circuit for a (n, k) BCH code. [4]

The operation of the encoder_LFSR design of figure 3.3.1.1 is as follows [4]:
[1] For the clock cycle 1 to k,
The original message bits are transmitted without changing its form (during this operation
switch s2_in is in position 2), and the linear feedback shift register calculates the parity
bits (switch s1_in is on now).
[2] For cycle k+1 to n,
The generated parity bits in the linear feedback shift register are transmitted (switch s2_in
is in position 1) and the feedback in the LFSR is switch off (s1_in off).

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3.2 Encoder_LFSR Design Architecture
Figure 3.2.1 shows block diagram of BCH encoder_LFSR. Basically, encoder_LFSR
module is consists of three modules.
[1] 5 bit Parallel to Serial Shift Register
[2] Encoder_LFSR module - Linear feedback shift register
[3] Serial to Parallel Shift Register
In this project we had designed three (15, 5) error correcting BCH code. The input to the
BCH encoder_LFSR is 5- bit message, which is encoded in a 15-bits codeword by adding
10-bit parity bits. The BCH encoder_LFSR uses the linear feedback shift register (LFSR)
for polynomial division. This division generates redundant parity bits.
Parallel to Serial Shift Register:
The input to the parallel to serial shift register is a 5 bit message bits. During the 1 st clock
cycle all the 5 message bits are given as input to the shift register. At the 1 st clock cycle ld
signal is set to high (logic 1), which remains high between 1 st and the 2nd clock pulse and
after that it sets to low (logic 0). So, after the 1st clock cycle all the message bits are
stored in the shift register and starting from the 2nd clock pulse the bits will start shifting
serially with each clock cycle. So, at the end of 6th clock pulse all the 5 message bits are
shifted serially at the output of the parallel to series shifter. The output of the parallel to
series shift register is given as input to the next module called encoder_LFSR module
Linear feedback shift register.

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The below figure shows the block diagram of Encoder_LFSR module.

Fig 3.2.1 Encoder_LFSR Block

3.2.2 Encoder_LFSR Module Linear Feedback Shift Register (LFSR)

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The Encoder_LFSR module is designed with respect to the generated polynomial given
in the equation no.(2.15). Generator polynomial is divided by the incoming 5-bits
message bits. The division is carried out using linear feedback shift register, the
remainders of this division is added with the original message bits to form a codeword.
The (15, 5) code has 10 bits redundant parity bits, and therefore 10 remainder stages are
required. As shown in the figure 3.2.1. These stages are labeled as d0 to d9. The generator
polynomial is represented as follow,
g(x) = f1(x) * f3(x) * f5(x) = 1 + x + x2 + x4 + x5 + x8 + x10.
The generator polynomial has g3= g6= g7= g9 = 0. So there is no feedback to d3, d6, d7
and d9. Thus the equations are:
bf = bin + d9.
d0 = bf
d1 = bf + d0
d2 = bf + d1
d3 = d2
d4 = d3 + bf
d5 = bf + d4
d6 = bf
d7 = d6
d8 = bf + d7
d9 = d8
bout = d9

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The switch signal of Encoder_LFSR remains high during 1st 5 clock cycle to shift the 5
message bits into encoder_LFSR and then it goes low. This will allows the generation and
shifting of parity bits. After the 5 shifts the message bits enter into codeword stage, which
is also a series to parallel shifter. In codeword stage the information bits are divided by
g(x) to give required parity bits. Now next 10 stages are required to move parity bits into
codeword stage. Thus it required total 15 clock cycles to shift the codeword in to the
series to parallel shifter.

Serial to Parallel Shifter:

The output of the encoder_LFSR module is fed to series to parallel shifter. As its name
indicates this shifter shift the series input to the parallel output at every positive edge of
the clock. The hld signal of the series to parallel shifter is remain low initially. At every
clock pulse the shifter shifts the incoming serial bits to parallel output. At the 17 th clock
pulse codeword- all 15 bits are shifted at the output and the hld signal is assert high, to
make sure that no extra bit will be added to the message bits. The above waveform shows
the input and output signals used for encoder_LFSR block. The signals used in the
waveform are given as:
Input signals:

5 bits message msgs

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Clock clk

Reset reset

Start signal for the encoder_LFSR active_encoder_LFSR

Counter cntrl

Initialize init

Ld signal for Parallel to Serial shifter ld

Hld signal for serial to parallel shifter hld

Switch signal for encoder_LFSR block switch

15 bits codeword out

Cntrl Signals:

Output signals:

The shown waveform is the simulation result of Encoder_LFSR module, the input to the
encoder_LFSR circuit is 5 bits message bits msgs, and the output is 15 bits codeword
called out.
5 bit Message msgs 00001
15 bit Codeword out 000010100110111

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