THE

GEORGE WASHINGTON UNIVERSITY

SCHOOL OF ENGINEERING AND APPLIED SCIENCE
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING






ECE 4925
Final Design Report

EEG Alarm Clock

Presented to Dr. Matthew Kay

by

Zahin Hasan
Alexander Magnano

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Abstract

The proposed system, EEG Alarm Clock, (henceforth referred to as the EAC) is a system that
will allow patients to record their electroencephalogram signals as they sleep, distinguish between the
varying stages of sleep, and trigger an alarm to awake the patient at an optimal stage of sleep. The EAC
can be set to wake the subject up at an optimal, preventing grogginess and fatigue upon waking up.

For the proposed system to function, electrical activity under the skin is measured and
processed to distinguish the different characteristics of electrical activity during the varying sleep stages.
Each signal category is interpreted by the microcontroller to determine at what stage of sleep the user is
currently in. The microcontroller then triggers an alarm when the ideal moment for the user to wake up
arises.
The EEG Alarm Clock can be used by anybody with a flexible morning schedule and the desire to
wake up feeling the most refreshed. Another group that would find the alarm clock viable are people
who have personal issues of oversleeping.

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Table of Contents

List of Sections
I. Project Description (ZH 50%/AM 50%) ........................................................................................... 4

a. Introduction ...................................................................................................................... 4

b. Technical Information ....................................................................................................... 4

c. The EEG Alarm Clock Market ............................................................................................. 5

d. Electroencephalogram ...................................................................................................... 5

e. Sleep explanation .............................................................................................................. 6

f. Signal Processing ............................................................................................................... 9

g. Microprocessor ................................................................................................................. 9

h. Hardware .......................................................................................................................... 10

i. Overview of the Proposed Device ...................................................................................... 11

j. Intellectual Contributions .................................................................................................. 12
II. Approach to Overall Design (ZH 50%/AM 50%) ............................................................................. 12

a. Current Design .................................................................................................................. 12

b. Evolution of the Current Design ....................................................................................... 14
III. System Requirements and Specifications (ZH 50%/AM 50%) ....................................................... 14
IV. Overall System Design (ZH 50%/AM 50%) .................................................................................... 15

a. System Level Testing ......................................................................................................... 16

b. Summary ........................................................................................................................... 16
V. Modular Level Requirements and Specifications (EEG) (ZH 100%) ............................................ 16
VI. Individual Module Design (EEG) (ZH 100%) .................................................................................. 16

a. Stage 1: First-Stage Amplifier ............................................................................................ 17

b. Stage 2: Passive High-Pass Filter ....................................................................................... 17

c. Stage 3: Main-Stage Amplifier ........................................................................................... 18

d. Stage 4: Active Low-Pass Filter ......................................................................................... 18

e. EEG Module Testing .......................................................................................................... 18
VII. Modular Level Requirements and Specifications (Microprocessor) (AM 100%) ...................... 19
VIII. Individual Module Design (Microprocessor) (AM 100%) ............................................................ 20

a. Frequency measurement .................................................................................................. 22

b. Logic processing ................................................................................................................ 23

c. Sounding the alarm ........................................................................................................... 24

d. Microprocessor Module Testing ....................................................................................... 26
IX. Modular Level Requirements and Specifications (Hardware) (ZH 50%/AM 50%) ..................... 28
X. Implementation Plan (ZH 100%) .................................................................................................... 28
XI. Timeline Estimation and Milestones (ZH 15%/AM 85%) .............................................................. 29
XII. Labor Costs Graph (ZH 85%/AM 15%) ......................................................................................... 30
XIII. Economic Analysis (AM 100%) .................................................................................................... 31
XIV. Applicable Engineering Standards (ZH 50%/AM 50%) ................................................................ 31
XV. Parts List (ZH 50%/AM 50%) ........................................................................................................ 32
XVI. Module Matrix (ZH 50%/AM 50%) .............................................................................................. 32
XVII. Summary and Conclusions (ZH 50%/AM 50%) .......................................................................... 32
XVIII. Qualifications of Key Personnel (ZH 50%/AM 50%) .................................................................. 33
XIX. Teaming Arrangements (ZH 50%/AM 50%) ................................................................................ 33
XX. Works Cited (ZH 50%/AM 50%) ................................................................................................... 33


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List of Figures
Figure 1 Sample EEG Block Diagram ............................................................................................... 7
Figure 2 Standard human hypnogram ............................................................................................ 7
Figure 3 Chart of sleep stages and associated wave types ............................................................. 8
Figure 4 Image of beta wave activity .............................................................................................. 8
Figure 5 Image of alpha wave activity ............................................................................................. 8
Figure 6 Image of theta wave activity ............................................................................................. 9
Figure 7 Image of K-complexes and sleep spindles ......................................................................... 9
Figure 8 Image of delta wave activity ............................................................................................. 9
Figure 9 Top view of container ....................................................................................................... 11
Figure 10 Front and side view ......................................................................................................... 12
Figure 11 Overall flow diagram for EAC .......................................................................................... 12
Figure 12 Overall signal flow diagram ............................................................................................. 14
Figure 13 Table of inputs and outputs per module ......................................................................... 16
Figure 14 Circuit Diagram of INA 128P ............................................................................................ 18
Figure 15 Passive high-pass filter .................................................................................................... 18
Figure 16 Operational Amplifier with Inverting Feedback Loop ..................................................... 19
Figure 17 1st Order Butterworth Low-pass Filter ............................................................................ 19
Figure 18 Microprocessor block diagram ........................................................................................ 21
Figure 19 Sampling the frequency of a wave .................................................................................. 22
Figure 20 AD converter communication ......................................................................................... 22
Figure 21 Circuit diagram of AD Converter ..................................................................................... 23
Figure 22 Wave graph ..................................................................................................................... 26
Figure 23 Pulse-width modulator ................................................................................................... 26
Figure 24 Xilinx Spartan 3AN ........................................................................................................... 27
Figure 25 Gantt Chart for EAC ......................................................................................................... 29
Figure 26 Labor Costs Graph ........................................................................................................... 30
Figure 27 Module Matrix ................................................................................................................ 32

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I.

Project Description

Introduction

Electroencephalography (EEG) is the recording of electrical activity along the scalp produced by
firing neurons within the brain. The purpose of our Senior Design Project is to utilize the EEG to identify
an appropriate point in a persons sleep cycle at which an alarm will trigger, waking the person. To do
this, a little more information is needed in regards to the sleep cycle, and how EEGs can be used to
measure a sleep cycle.

As we sleep, our brains undergo differing levels of electrical activity. An EEG measures this
electrical activity. Through the use of EEGs, it has been discovered that when a person is wide-awake
and is fully active, his/her brain emits a signal characterized as a Beta Wave. When that person is
relaxing, he/she emits Alpha Waves. As the person enters deep levels of sleep, he/she emits Delta
Waves. The differences between these waves are their frequencies, with Beta Waves consisting of a 12-
30 Hz range, Alpha Waves consisting of an 8-12 Hz range, and Delta Waves consisting of a >0-4 Hz range.

For EEGs to be used as inputs, electrodes are used as sensors and are placed on the scalp. As
the brain fires action potentials down neurons, waves of ions are sent toward the surface of the scalp,
pushing and pulling on the electrons of the electrodes. These pushes and pulls are recorded over time,
giving a signal. Depending on the frequency of this signal, the stage of sleep/alert can be determined.

While it is necessary to track the stage of the sleep cycle for the user, it is also necessary to set
an alarm for the device. A typical sleep cycle fluctuates between varying stages, typically Stages 1-4 and
REM (Rapid Eye Movement) sleep. An optimal sleep results in the user waking up when the cycle has
returned to an early stage of sleep, preferably Stage 1. The alarm would be set to trigger when the user
has returned to Stage 1 sleep, with differences being how many cycles of sleep the user would prefer
(this amount will then determine how long the sleep will be).

Technical Information
There are two outputs for the device. A seven segment LED display and sound. The seven-
segment LED display will show the time information. There will be 4 seven segment displays to show
the hours and minutes of the time. The standard red color for alarm clocks will be used, which requires
a voltage drop between 1.63 and 2.03 volts for each LED display. The sound will have a frequency range
of 40Hz - 20kHz. Some of the lower frequencies (20-39 Hz) are cut out for a higher pitched sound is
needed to properly wake someone up therefore the low frequencies are unnecessary. For volume of
the sound, a range of 64dB to 84dB will be used. This range is around standard alarm clock sound levels.
The lower end is quieter, but loud enough to wake up some people, while the higher end is somewhat
on the louder side of alarm clocks. Lower or higher than this range is outside of what most people
would feel comfortable using.

To effectively measure the electrical activity of the brain along the scalp, it is imperative to
amplify to better quantify the voltage measurements. The reading from the scalp is so minute, that it is
far more difficult to distinguish smaller differences in voltages. Therefore, many of the electrodes that
are placed on the scalp are thereby connected into an input of a differential amplifier, while the other
input would come from the reference electrode. Amplification of the signal is on the scale of


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approximately 10,000 to 100,000 times the original signal. The signal is essentially the difference
between the measured voltage at the electrode against the voltage at the reference electrode.
Afterwards, the signal is filtered to acquire and present the specific sequences of electrical activity and
then is digitized through an analog-to-digital converter (sampling in the range of 256-512 Hz).
Ultimately, a typical adult human EEG signal would be in the range of 10V to 100V.

The output of the EEG would be an amplified version of the measured. Since the four bands of
the most importance to this project are the delta, theta, alpha and beta waves, it is crucial to
differentiate the frequencies at which each band is seen. The ranges of the frequency at which the
voltages occur are: up to 4 Hz, 4-7 Hz, 8-12 Hz, and 12-30 Hz for delta, theta, alpha, and beta waves,
respectively. For example, Welchs method to estimate the power of a signal vs. frequency, as used by
the software EEGLAB and MATLAB, would be one method to extract desired frequency bands from the
voltage measurements. Ultimately, using the pwelch command in MATLAB, or Welchs method in
EEGLAB would be an ideal way to use spectral method technique to obtain and differentiate the
different EEG bands. These different EEG bands would be the final output of the EEG, and these wave
measurements can be used to complete the tasks required for the project.

The EEG Alarm Clock Market

As our society shifts to a productivity-based society, increasing amounts of people are working
longer hours. Between work and family life, there is very little time for sleep. However, sleep is a
biological necessity, as it is the process in which growth occurs, energy is replenished, and memories are
accumulated. Often times, people limit their sleep based on how many hours they can allot for sleep,
without regard to the stage of sleep during which they plan to awake. For the most efficient sleep
possible, without the user waking up at an inconvenient stage during sleep, this device is necessary, as it
not only wakes up the user, but it wakes up the user at a point where he/she will wake up refreshed.


Many people would be more-than-willing to sacrifice an extra 20 minutes of their day if it meant
starting their day without all of the grogginess that can normally come with waking up early. The
extreme difference of tiredness compared to a small change in time is an idea that would be quite
appealing to a lot of people with busy days. A product that allows someone to sleep for only 3 hours in
the day but feel rested is a productive product.


The efficiency of peoples work when using the EEG Alarm Clock as opposed to a regular alarm
clock will show significant differences. The EEG alarm clock could easily replace todays regular alarm
clocks for people who have a care for their health and their state of mind.

Electroencephalogram (EEG)

The electroencephalogram is a method in which electrical impulses are recorded from the brain
and are visualized. These electrical impulses change depending on the brains activity. The EEG Alarm
Clock utilizes the EEG as the brain goes through varying stages of sleep (which will be further discussed
in the Sleep explanation section).


To acquire an EEG signal, electrodes that are covered with silver chloride (or other conductors,
like silver, tin, steel, or gold) are attached to the skin of the area where impulses are to be read. The
signals amplitude must go through thousand-fold amplifying before it can be easily read. In addition to
increasing the ability for the system to record data, the signal must also overcome atmospheric and


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thermal noise. A standard building will have a 60 Hz hum, requiring amplification to overcome the noise
(Griffiths).


After amplification, EEG signals are passed through a low-pass filter to minimize aliasing and
distortion as the signal undergoes analog-to-digital conversion. Below is the block diagram for a sample
EEG, which utilizes amplifiers and low-pass filters (Griffiths).

Figure 1 Sample EEG Block Diagram

Sleep explanation

The EEG Alarm Clock utilizes patterns found in typical sleep cycles for operation. To understand
sleep, understanding the underlying electrical activity is most important. A typical sleep cycle can be
split into six phases: Awake/Early Sleep, Stage 1, Stage 2, Stage 3, Stage 4, and REM (Cherry). The entire
sleep cycle can be summed with the following hypnogram:

Figure 2 Standard human hypnogram

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The four sleep stages are all part of NREM sleep, also known as non-rapid eye movement sleep.
In NREM sleep, four different types of waves are noted when describing and distinguishing the various
phases:

Sleep Stage
Dominant Wave Type
Frequency
Other Present Types
Stage 1
Alpha Waves
8 12 Hz
Beta, Theta
Stage 2
Theta Waves (with
4 7 Hz
Alpha
Sleep Spindles)
Stage 3
Delta Waves
>0 4 Hz
Theta
Stage 4
Delta Waves
>0 4 Hz
None
REM
Beta Waves
12 30 Hz
None
Figure 3 Chart of sleep stages and associated wave types

Figure 4 Image of beta wave activity

Beta waves (which range from 12 to 30 Hz) are the waves observed when the subject is awake
and alert. This electrical activity is produced when muscle contractions occur in isotonic movements.
Beta waves are most notable for being low in amplitude and high in frequency.

Figure 5 Image of alpha wave activity

Alpha waves (which range from 8 to 12 Hz) are the waves observed as the subject slowly
approaches Stage 1 of sleep. At this point, the subject is still conscious, but is nearing a loss of
consciousness. Alpha wave activity is significantly lower in frequency than beta wave activity, indicating
lower amounts of muscle contractions.

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Figure 6 Image of theta wave activity

Theta waves (which range from 4 to 7 Hz) are the waves observed in Stage 1 sleep. In this stage,
the subject starts to enter unconsciousness. Theta waves are lower than alpha waves in frequency.
However, this stage of sleep lasts for a short amount of time.

Figure 7 Image of K-complexes and sleep spindles


K complexes and sleep spindles are seen during Stage 2 sleep. As the brain goes deeper into
sleep, it produces bursts of rapid wave activity.

Figure 8 Image of delta wave activity

Delta waves (which range from 0 to 4 Hz) are the waves observed in Stages 3 and 4 of sleep. In
these stages, the subject enters unconsciousness. When compared to all of the previous stages, delta
waves can be qualified as more stable and with lower frequency, mostly as a result of the relaxed
muscles and lower brain activity associated with sleep.


In REM sleep, the subjects eyes are observed to be moving in rapid rates (hence why it is called
rapid eye movement). It is during REM sleep that most people have vivid dreams that can be recalled.


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Because of the increased brain activity, and the appearance of beta waves, REM sleep is also known as
paradoxical sleep, as the brain wave activity implies alertness.


To prevent aliasing, the filter cutoff that will be observed in the EEG module is set to 35 Hz. The
cutoff is set to 35 Hz as the highest observed frequency from natural brainwave activity is seen in beta
waves, which ranges from 12 35 Hz. As a result, the sampling rate in the Microprocessor will be set to
the Nyquist Frequency, 70 Hz, which is double the maximum observed frequency.

Signal Processing

The signal processing of the EEG Alarm Clock will be done in C++ code. The signal processing will
receive a digital signal and determine with it the frequency and amplitude of the signal. This will be
done using the Discrete Fourier Transform method. The DFT is ideal for digital signal processing and is
the most optimal for a microprocessor. The DFT translates an incoming function into its frequency
domain representation. The general equation for conversion is the formula

The program will take the incoming digital signal and cut it into segments. Each segment will
then be converted into its frequency values and then sent on to be read by the rest of the program. This
segmentation of the incoming signal as opposed to a continuous conversion is what makes DFT's much
easier to understand and use in a microprocessor.


In C++ there are available signal processing libraries and tools available to help build a functional
code. The one to be used will be the SPUC (Signal Processing Using C++) library. The SPUC library is
designed for helping communication systems designers build proper signal processing programs. The
library includes basic building blocks such as complex data types and fixed-bit width integer classes,
which will be useful for storing data in EEPROM and do other calculations.


There are no specific limitations on the signal processing using C++. Based on the
microprocessor, however, the signal processing will be working with a 10-bit digital signal and will
output 8-bit frequency recordings.

Microprocessor

The second module within the EEG Alarm clock will be the central processing unit for the
project. The microprocessor will receive the EEG signals, conduct the signal processing of the EEG, and
determine when the alarm clock will sound.


The microprocessor will first read the EEG signals using the analog-to-digital converter. The ADC
will take the analog signal of the EEG waves and will sample the EEG waves into a digital translation that
is readable by the microprocessor. The ADC has a 10-bit resolution with 2LSB accuracy. The range of
voltage it can accept is the range of 0-(Vcc-1LSB) where Vcc is a voltage determined by the designer
depending on what is inserted into the AREF pin. The signal can be sampled at up to 200k Hz, but
considering how low the frequency of the incoming EEG waves will be, a much smaller sample rate will
be used. All of these variables are defined when the chip is programmed.



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Next the microprocessor will go through the steps of taking the digital signal and calculate the
proper outcome. It will begin with signal processing calculations to determine the type of wave that the
sleeper is experiencing. Since the sleep cycle does not specifically have a certain wave for each stage of
sleep, the algorithm for determining when to wake up the user will have more complex. The algorithm
will follow the box diagram in figure X. The coding language in which all of these calculations will be
done and is utilized by the microprocessor is C.

The last part to this process is outputting the signal to the speaker to create the alarm sound.
This uses the built-in pulse width modulator. The fast PWM mode will be used. This mode generates a
high frequency analog signal. The fast pulse width modulation mode generates the signal with a single-
slope operation. The single slope operation works by using the variables defined in the C code by the
designer. There is the low value, which is zero by default, and then the high value that determines the
frequency of the signal. The output voltage starts at the low value and increases in value until the
comparator within the microprocessor recognizes that the high value set by the designer and the
current value are the same. It then sets the voltage back to low and the voltage starts the climb again.

Hardware

The system circuits and FPGA board will all be contained within a small wooden box. The
dimensions of the box are mostly limited by the FPGA board, due to its width and length. The
dimensions of the FPGA board are 17.5 x 17.5 cm's, so a 21x21 cm box will work well for the box. The
extra centimeters on each side leave room for the thickness of the box and extra wiggle room for any
wires that may need to pass through. The circuitry should be able to fit into these dimensions without
too much issue. The other dimension to determine is the depth. The board is 3 cm thick, and the
circuitry is about 5cm thick. This adds up to 8cm, which we then need to include the alarm speaker
which will be about 5cm. We then need to include wiggle room and box thickness, so the final
dimensions of the box will be 21x21x16 cm's. Here are some diagrams of what this will look like:

Figure 9 Top view of container

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In the top view, there are two holes, one for the screen to fit in for the FPGA board, and the
other for the buttons and dial for the user to interact with.

Figure 10 Front and side view

The front hole is for the speaker to not produce a muffled sound. The side hole is for the wires
that will be connected from the headband to the circuitry within the box. The back view also looks very
similar to the side view, with a hole for the batteries to fit.

Overview of the Proposed Device

Figure 11 Overall flow diagram for EAC

In use by a user, the proposed EEG Alarm Clock will consist of:
A central electronics box
Five electrodes (using conducting gel)
Five wires to connect the electrodes to the electronics box
Adjustable alarm controls

The purpose of the EAC is to measure and record EEG signals as a person sleeps, distinguish the
various types of waves found in the recorded signal, and trigger an alarm based on the wave and length
of time the person has slept. The EAC can be set to wake the subject up at an optimal time, which will
prevent grogginess and fatigue upon waking up.


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The EEG Monitor measures the electrical activity under the skin when attached to the subject's
head. The electrical activity is expected to comply with typical sleep activity (i.e. alpha, beta, delta, and
theta waves). These waves are characterized by varying frequencies, wavelengths, and amplitudes.
Once the electrical activity is recorded, it is then to be processed. Through amplification and filtering,
we can isolate the desired signal, which will then be used to distinguish alpha, beta, delta, and theta
waves.

Each of these waves corresponds to a different level of awake/alertness. When the signals are
separated into their respective categories based on characteristics, the microcontroller will be coded to
decide between triggering the alarm and continuing the sleep. The microcontroller will be able to
recognize when a full sleep cycle is complete, triggering the alarm. Typically, the command will be to
trigger an alarm during alpha waves, allowing the subject to wake with ease. This trigger will be sent to
the speaker, which will play a given sound.

Intellectual Contributions
The proposed system requires several major components. Some of the components will be
designed and created by the authors while others will be simply bought from 3rd party sources. The
different intellectual contributions are as follows:
ElectrodesBought commercially
Connecting wiresBought commercially
MicrocontrollerBought commercially but the authors will program the
microcontroller.
Electric circuitryDesigned and built by the user other than the smaller components of
the circuit, such as resistors and capacitors.
Integration of signal processingDesigned by the authors

II.

APPROACH TO OVERALL DESIGN

Current Design

The EEG Alarm Clock functions with three main modules: the EEG module, the Microprocessor
module, and the Hardware module. The EEG module consists of stages in which the EEG signals of the
brain is amplified and filtered. The resulting signal is then sent to the Microprocessor to be converted
from an analog signal into a digital signal, and is then put through an algorithm to determine the
characteristic wave type of the EEG signal. The algorithm also determines when to trigger the alarm to
awaken the user. The FPGA for the Microprocessor and the circuit board for the EEG are both encased in
one half of the hardware module: the case, which allows for protection of the circuits as well as
exposing the necessary components of the FPGA to allow calibration and time viewing. The second half
of the hardware module is the headband, which is used by the user to send EEG signals, via electrodes
attached to the headband, from the head to the EEG circuit.

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Figure 12 Overall signal flow diagram

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Evolution of the Current Design

At its initial conception, the EEG Alarm Clock was split into three modules: EEG, Signal
Processing, and Microcontroller. The team responsible for the EAC also consisted of three members, one
for each module. Shortly after being given the assignment, one of the members was removed from the
group. The Signal Processing module was then merged with the Microcontroller module.

To prove that the EAC was a feasible task to complete, a proof-of-principle project was set up
using BIOPAC. In the project, one group member was connected to BIOPAC via electrodes and fell asleep
in lab, while the other member recorded the EEG signals. The resulting signals were then used to prove
that theres a very apparent difference between wave types, and that an algorithm could be used to
distinguish between them by separating wave-types by frequency ranges.

The next semester, each member made a prototype based on his module. The EEG prototype
was made for one lead, implementing a variety of filters and amplifiers to adjust incoming EEG signals
enough to be read by the microprocessor.

The Microprocessor module was changed from using a standard Microcontroller to an FPGA.
The microprocessor originally used was an Adruino microcontroller. This turned out to be a poor choice
because while it is easier to read in an analog signal with an Adruino microcontroller, signal processing is
near impossible and incredibly inefficient. Also, it is much easier to read such low frequencies needed to
properly read an EEG signal with the format of an FPGA board over a microcontroller.

Upon discussion with the group mentor, a third module was created for hardware. For the final
design, the two existing modules, as well as the newest hardware module, will be integrated and
synergized to create the final EEG Alarm Clock.

III.
SYSTEM REQUIREMENTS AND SPECIFICATIONS

System Requirements Detailed Product Functional Requirements
1. The EEG Alarm Clock will be able to recognize in which sleep the user is and displays it on an LED
display. The stages of sleep for the device to recognize are: Awake, REM sleep, and Stages 1-4 of
non-REM sleep.
2. The EEG Alarm Clock will wake up the user during the optimal time in sleep to awake.
3. The device will have an alarm with volume control that provides a wide enough range to suit the
needs of most users.
4. The device will display the time on an LED screen, which will also be editable by the user. The time
on the clock will display minutes and hours.
5. The device will be powered by batteries and should not power off until the user shuts down the
device.
6. The device should cause no harm, temporary or long term, and should provide complete safety.

System Specifications Detailed Product Functional Specifications
1. The input of the device consists of two EEG signals acquired with electrodes attached to the
device via wires. The two signals should suffice in producing enough signal for the
microcontroller to determine the stage of sleep as well as not intrude on the users comfort.
2. The EEG signals will be amplified and filtered to produce a sufficient signal for the microcontroller


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to read and analyze. The amplification and filtering levels will be determined through trial-and-
error.
3. The device will be able to read a frequency range of 1-40 Hz.
4. The dynamic range of the alarm will be about 80 dB.
5. The allowed frequency error in the amplified, filtered signal should be 1.76 dB.
6. The EEG Alarm Clock should awaken the user within 60 seconds of the time determined to be
most ideal for the user to be awoken.
7. There will be 4 digits displayed on the alarm screen, each 3.5 tall and 0.6 wide. There will also
be Led lights that display if the alarm is on and if the time is AM or PM.
8. The device will run on a 12V battery or eight AA batteries.

IV.
Overall System Design
The EEG alarm clock (herein referred to as the EAC) will measure and record EEG signals as a
person sleeps, distinguish the various types of waves found in the recorded signal, and trigger an alarm
based on an algorithm that determines when the user has finished a full cycle of sleep. The EAC can be
set to wake the subject up at an optimal time, which will prevent grogginess and fatigue that is often
felt, even if a person gets a what may be deemed as a sufficient amount of sleep. The EEG alarm clock
can be broken down into two main subsystems: the EEG monitor and the microprocessor.
The EEG monitor measures the electrical activity under the skin when attached to the subject's
head. The electrical activity that the head emits is expected to comply with typical sleep activity. The
normal waves the EEG can read from the brain are alpha, beta, delta, and theta waves. These waves are
characterized by varying frequencies, wavelengths, and amplitudes. Once the electrical activity is being
properly read, the monitor then processes the signal. Through amplification and filtering, the monitor
isolates the desired signal and makes it readable by the microprocessor, which will then be used to
distinguish alpha, beta, delta, and theta waves. Each of these waves corresponds to a different level of
awake/alertness and is used in the process to determine when the user should be awoken.
When the signals are separated into their respective categories based on characteristics, the
microprocessor will record the history of the sleep and determine when the appropriate time to wake
up the user is. Using a programmed algorithm, the microprocessor will be able to recognize when a full
sleep cycle is complete, triggering the alarm. There will also be another setting for the user to provide a
time by which they will need to be awoken. The microprocessor will then use a different algorithm that
will determine when the optimal time near the provided time it should awaken the user. Typically, the
command will be to trigger an alarm during alpha waves, allowing the subject to wake with ease. This
trigger will be sent to the speaker, which will play a given sound. The modules that this microprocessor
system breaks down into are the analog-to-digital conversion, signal processing, signal categorization,
logic processing, and pulse-width modulation. The divided inputs and outputs of each subsystem are
provided in the table below:

Subsystem

Inputs

Outputs

Overall

EEG waves

Time-triggered alarm sound

EEG monitor

EEG waves
Source voltage

Amplified and filtered signal

Microprocessor

Amplified and filtered signal

Source voltage

Time-triggered alarm sound

Figure 13 Table of inputs and outputs per module

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The EEG monitor takes in the EEG waves, filters and amplifies them, then sends the new signal
to the microprocessor. The microprocessor then reads the frequencies to determine what type of wave
it is, and then triggers an alarm when it is the optimal time for the user to be awakened.

System Level Testing

The system level testing will assure that the microprocessor will work as wanted in the project.
The AVR Studio program will be used to simulate the code of the microprocessor on a virtual
microprocessor. The input to the simulated microprocessor will be a properly amplified and filtered EEG
signal to represent the EEG module's signal. The frequency and amplitude of the simulated signal will be
set to simulate that of a typical sleep pattern except that the length of each sleep cycle will be reduced
to allow for reasonable simulation time. The code being simulated will then be tested through AVR
Studio to display that the signal is properly read and that an outputting signal is sent to the speaker to
awake the user. The outputting signal will be monitored as well to assure that the microprocessor sends
the correct signal with accurate timing.

Summary

The EEG Alarm clock measures the electrical impulses of the brain of a user as he/she sleeps,
and triggers an alarm based on the stage of sleep. To do this, the device has three main modules: the
EEG module, the Signal Processing module, and the Microcontroller module. Together, these modules
accomplish all of the desired requirements and specifications.

V.
Modular Level Requirements and Specifications (EEG)

Requirements Detailed Module Functional Requirements
1. The EEG module will be able to record signals emitted from the users forehead and/or scalp.
2. The EEG module will be able to amplify the signals to ease the analysis process of the
Microcontroller module.
3. The EEG module will be able to filter the amplified signals to ensure the signals range is within the
range as specified in the Detailed Product Functional Specifications.

Specifications Detailed Module Functional Specifications
1. The EEG module will have two signal inputs, enough to obtain sufficient signal for processing in
the Microcontroller module, but few enough to maintain comfort for the user.
2. The input of the device will be powered by a 12V battery, or eight AA batteries.
3. The electrodes used for the input will be attached to the user via a Protection Circuit.
4. The combined total Gain from the amplifiers is 72 dB
5. The amplified signal will go through a 40 Hz Lowpass filter to ensure all signal is within the
prescribed range as defined in the Detailed Product Functional Specifications.

VI.
Individual Module Design (EEG)


Electrical signals from the scalp have very low amplitudes, ranging from 5 to 500 V. In addition to
low amplitudes, there may be a DC offset that interferes with the signal. To ensure the Microcontroller
Module will be able to read, convert, and analyze the EEG electrical input, proper amplification and
filtering is required.


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Stage 1: First-Stage Amplifier (INA 128P)

The purpose of this first stage is to amplify the signal a sufficient amount for DC Offset filtering.
Because of the nature of Instrumentation Amplifiers, which allow for the manipulation of the circuits
Gain by means of changing one resistor value, the Gain is set to a relatively low value to ensure the DC
Offset is not over-amplified. In this instance, the Gain Resistor (RG) is set to 2k, giving a total gain of 26.

Figure 14 Circuit Diagram of INA 128P

Stage 2: Passive High-Pass Filter

Once the signal has been amplified, a passive high-pass filter, composed of one resistor and one
capacitor, is implemented to remove any potential DC Offset. The cut-off frequency for the filter is
calculated with the following formula:

For the purposes of this project, R = 1M and C = 3.3F, giving a cut-off frequency of 0.05 Hz. A
typical high-pass filter circuit looks as follows:

Figure 15 Passive high-pass filter

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Stage 3: Main-Stage Amplifier (LM 741)

After the passive high-pass filter removes the DC Offset, the signal goes through the Main-stage
Amplifier, in which it is amplified with a high Gain value. The main-stage amplifier is an operational
amplifier (the LM 741, specifically) with an inverting feedback loop. The two resistors involved in this
feedback loop determine the gain, with the gain equation being Gain = 1+ (R2/R1). For this project, R2 =
51k and R1 = 1k, giving a gain of 52 dB.

Figure 16 Operational Amplifier with Inverting Feedback Loop

Stage 4: Active Low-Pass Filter (LM 741)

Now that the signal has been sufficiently amplified for reading by the Microprocessor Module, it
must be filtered to include only wanted frequencies before passing onto the next module for processing
and analysis. For the sake of removing any 60 Hz hum, a filter was designed with a cutoff frequency of
59 Hz. This filter is designed with attributes from both a butterworth and Bessel filter, earning the
nickname besselworth. It also provides a gain of 16 to further amplify the signal.

Figure 17 Low-pass Filter

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EEG Module Testing

To test the EEG Module, a prototype for one EEG lead was built. This prototype implements
all four stages of the EEG circuit. The prototype was connected to a function generator and an
oscilloscope to test the amplifying and filtering capabilities of each stage. The function generators
output was placed at the input of each individual stage to ensure no stage was dysfunctional when the
circuit is put together. Below is an output for the first stage, which was set to have a gain of 26 dB.
Experimentally, the stage provided a gain of 21.7 dB.

Important Design Changes

From the initial design, a Right Leg Driver was added to the circuit to help remove the 60 Hz
noise that gets picked up from the surrounding environment. In addition, the 1st stage butterworth filter
was exchanged with what is called a besselworth low pass filter, and the entire circuit was redesigned
with bypass capacitors to further reduce noise.
VII.
Modular Level Requirements and Specifications (Microprocessor)
Requirements Detailed Module Functional Requirements
Analog-to-Digital Converter
1. The converter will be able to read an amplified and filtered EEG signal.
2. The converter will be able to sample the signal at appropriate rates to properly convert the signal.
3. The converter will output the digital signal to the signal processing module.
Signal Processing
1. The signal processing code will be able to read the digital signal from the converter.
2. The code will analyze the signal and determine its current frequency.
3. The resulting frequency from the code will be sent to the signal categorization sub-module.
Signal Categorization
1. The code will read the incoming frequency.
2. The code will output a single binary number that designates the frequencys category.
Logic Processing
1. The device will be able to read a binary input.
2. The logic code will have data stored from previous inputs for comparison.
3. The logic code will contain state tables to determine when the sleep cycles end.
4. The logic code will initiate the pulse-width modulator at the appropriate time.
Pulse-Width Modulator
1. The pulse-width modulator will read incoming variables.
2. The pulse-width modulator will output a modulating signal depending on the input variable.
Specifications Detailed Module Functional Specifications
Analog-to-Digital Converter
1. The converter will be able to read within a range of 1-40 Hz.
2. The sampling rate of the converter will be 80 Hz.
Signal Processing
1. The signal processing code will be able to read and interpret a frequency range of 0-40 Hz.
2. The code will be able to output the current frequency in an int format.
Signal Categorization
1. The format of the input will be an int.
2. The output of this sub-module will be a small binary number.
Logic Processing

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1. The logic code will be able to read a small 2-bit binary number.
2. The logic code will output a variable that will initiate the pulse-width modulator, and then halt it
after a specified period of time.
Pulse-Width Modulator
1. The incoming variable will be an int.
2. The outputting signal will be between 14-18 kHz.

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VIII.
Individual Module Design (Microprocessor)


The overall purpose of the microprocessor is to read the amplified and filtered analog EEG wave
from the EEG module and, using signal processing, it determines when to sound the alarm. The
microprocessor used for the alarm clock will be the Xilinx Spartan 3AN. The Xilinx Spartan 3AN is an
FPGA board that, once programmed, does not require a computer to use. The function block diagram for
the system is as follows:

Figure 18 Microprocessor block diagram

This process is broken down into five main modules: analog-to-digital conversion, signal processing,
signal categorization, logic processing, and pulse-width modulation.


The analog-to-digital converter is an on board function in the Spartan 3AN. What is to be done
here is to specify at what rate the converter should sample the incoming signal. In this case, since the
maximum frequency it will read is 40Hz, the sample must be double that to properly read the signal, and
so being 80Hz. Here is an example of what the computer will be sampling from the wave:

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Figure 19 Sampling the frequency of a wave

The analog-to-digital converter will then sample 80 times a second and output each value into a variable
provided by the code. This variable will constantly be changing, so it will be up to the signal processing
to keep track and properly read the incoming data. There will have to be communcation between the
microprocessor and the analog-to-digital converter. This looks like as follows:
















Figure 20 AD converter communication


The AD_CONV and SPI_SCK signals are sent out to the analog-to-digital converter that then
takes a sample of a signal and returns the digital value of that signal through ADC_OUT. The AD_CONV
signal tells at what rate the analog-to-digital converter should sample the input, while the SPI_SCK signal
tells the converter at what rate it should serially return the bits to the microprocessor. The overall circuit
diagram of the converter looks as follows:

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Figure 21 Circuit diagram of AD Converter

The pseudo code for the analog-to-digital converter which follows what was explained above
looks like:
always@positive edge of the clock

increment timer

if(timer == value according to sample frequency)


send signal AD_CONV


while(x<14)



add 1 to x



store serial bit ADC_OUT in storage location array[x]



always@positive edge of the clock

reverse SPI_CLK signal //this is to create a matching clock of the AD_CONV

The processor will take in the data from the converter and store it into an array using a for loop. From
here, the data is passed off to the FFT signal processing core which is provided by an outside library.

Frequency Measurement

The signal processing part of the system will use specific libraries provided in Verilog(the coding
language used on the Spartan 3AN) to interpret the data provided by the analog-to-digital converter.
The library used in this case will be the Pipelined FFT 128 points processor created by Unicore Systems.
This library acts like a core, which is a feature with Verilog that lets you set up the parameters and
incoming data, and then it outputs data to a specified variable. Cores are generated in the ISE program,


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which then automatically generates the code and attaches this code as a sub-unit of your main code.
Since it is pipelined, it will take in the data at every clock and output the fourier transform data at every
clock in the form of a integer. The 128 points version is used because it can take in between 8 to 16 bits
of data. Since we are taking in 13 bits of data from the AD converter, this fits perfectly.

The following step is to determine from the data what wave is being produced. As explained
above, there are 5 main stages of sleep, stages 1-4 and REM. With the frequency now calculated, the
FPGA board must interpret it and categorize it appropriately. This will be done by taking the average
frequency over about 30 seconds and analyzing that average. This will eliminate any error that could
occur from spikes in the EEG wave that would be caused from noise or imperfect sleeping. Since every
level of sleep has a range of frequency, unpredicted variations in the EEG wave will not cause the
frequency average to leave its appropriate value range. There will also be checks in the code to ensure
that if it reads any outrageous changes in the sleep pattern, to throw away that data and reevaluate the
next 30 seconds to ensure accuracy. The pseudo code for this will look like the following:
Loop at every second:
take in data from AD array[]
put through FFT Core
for(x=0, x < 30, x++)

int frequency = frequency + FFT output
frequency = frequency/30 //taking the average of the frequency over the past 30 seconds
if(frequency > 40)

Output error
else if(frequency > 12)

Output awake
else if(frequency > 4)

Output stage 1
else

Output stage 34
This information is then sent out to the logic processing for interpretation.

Logic processing

For the logic processing to do its job, it must first have knowledge of what stages occur at what
time. This is where the signal categorization module comes into play. It reads the constantly changing
frequencies that the signal processing module sends to it, and then interprets them to determine what
stage of sleep the user is in and at what time the user changes stages of sleep. The module goes about
this by noticing a general trend in change of frequency. When this trend in frequency hits a different
stage range, the signal categorization sends out what new stage the sleep is now in and at about what
time this happened at.

The information produced by the signal categorization is sent to the logic processing. The logic
processor is the central part of the subsystem. It is what reads the changing stages and determines
when to wake up the user. It will use a specific code to follow that will make this decision. The pseudo
code below demonstrates the logic this module will use:

Initialize program
While(input claims awake or else that does not fit into sleep)

Do nothing
While(user not awake)


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Every 20 seconds sample the incoming frequency

if(requested waking time not approaching)


if(stage X of sleep)



record that the sleep stage has occurred


if(stage 4 has happened twice)



if(stage 2 has happened 9 times)




if(stage 1 sleep)





wait 20 minutes





wake up user

if(requested waking time approaching)


if(user is progressing to lighter sleep)


case(stage of sleep)



1: Wait 5 minutes and then wake up the user



2: Wait 10 minutes



3: Wait 20 minutes



4: Wait 30 minutes


if(use is falling into deeper sleep)



Wake up immediately

The user will have an option to set an absolute time he or she must be up by. If that time is not close,
the program will follow the standard sleep cycle of a human being and wake up the user when the full
cycle has occurred. If at any point in this process the waking time of the user is approaching(say, within
the next 45 minutes) the logic unit will determine the best time within the next 45 minutes to wake up
the user from their sleep. A concept of how it will do this is demonstrated within the pseudo code. Once
the program decides when to wake up the user, it will send an alert to the pulse-width modulator.

Sounding the alarm

The pulse-width modulator is the alarm itself. When it is notified to trigger by the logic
processor, it will output an amplified frequency to the speaker within a range that the user can hear.
How the pulse-width modulator works is by producing an increasing in voltage, analog signal. During this
process it constantly compares the voltage value to a predetermined variable. When the variable and
the voltage value equal each other, the voltage drops back down to zero, thus creating a wave. This
wave looks like the graph below:

Figure 22 Wave graph

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As demonstrated by the graph, this process, thus creating a wave that will produce a sound to
the speaker, produces a wave of an amplitude equal to the variable. The length and variation of the
sound will be given by code within the program. The user will be able to adjust and determine how long
and what sound they would like to hear as an alarm. This feature will be implemented with the switches
and buttons available on the FPGA board. The circuit diagram for the pulse-width modulator that will be
creating an analog signal, looks as follows:

Figure 23 Pulse-width modulator

The only real component of this module is the microprocessor itself. After much comparison, it
was concluded that the Xilinx Spartan 3AN is the best for the project. The board looks as follows:

Figure 24 Xilinx Spartan 3AN


First, an FPGA board was chosen over other types of microprocessors and their boards. This is
because FPGA's are much more compatible with signal processing and reading such low frequencies that
the EEG will be producing. Most other type of boards cannot read that low of frequency, and the Verilog
language that this microprocessor is programmed by has libraries that can handle signals and produce
frequency values.


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Once narrowed down to FPGA boards, a specific model had to be selected. Major reasons for
picking the the Xilinx Spartan 3AN compared to other FPGA boards can be seen in the above image. This
board has a LCD screen and switches that are what allow the EEG alarm clock to be a standalone project.
The LCD screen provides a display that will be able to display the time and other functions so that the
user can see what setting the board is on and what time it is. With the switches to the right of the
screen, this allows the user to directly interact with the board to change the settings on the LCD screen.
Most FPGA boards do not have both of these components which would make it much more difficult to
have the module not require a computer to interact with it. The Xilinx Spartan 3AN also has an on board
analog-to-digital converter, two analog inputs, and four pulse-width modulators, all necessary
components to properly fulfill the subsystem requirements.

Microprocessor Module Testing

First, a test is to be done for the analog-to-digital converter. A signal will be inputed into the
FPGA board and a code will be used to output the digital data the converter is sending to the
microprocessor which then be sent out to an oscillator to show it's accuracy.

There will also be a test for the pulse-width modulator. This will be done by writing a code that
produces a simple signal to a speaker, which will produce sound at a given frequency to show
understanding and functionality of the modulator.

Once these are working, a sample filtered and amplified EEG signal will be sent into the FPGA
board and the board will output a frequency to the speaker at the appropriate time signified by the
sample data.

To test a board, there is no quantitative data to be recorded to show proof of functionality.
Either the code works, and the board will perform appropriately, or it wont.
Displaying results here in text or diagram form that the EEG clock works is not possible. In the
demonstration it is shown that the two subsections of the clock properly communicate with each other
and if the right progression of EEG signals were to be sent into the board, it would wake up the user
with speakers.
Important Design Changes

Instead of using a provided library online for the signal processing of the incoming digital signal,
a newly created signal processing technique was used for the sake of having a more compact and
simpler code. The signal processing technique works as following:










Figure 31: Signal Processing Method


In the code, there were two boundaries set which are represented by the two red lines above.
When a sample would be read above the top red line it would increment a variable and then set a
counter to high to prevent the variable from being incremented more than once for when the waveform


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went high. When a sample would be read as below the bottom red line, the counter would be set back
to low so that the variable would be incremented again next time the signal went high.
Every second, the value of the variable would be stored as the frequency and the variable would
then be set back to zero. Since the variable is read every second, it thus counts the number of high
points of a wave within a second which is equal to the frequency of a wave.

The gap between the high red line and the low red line exist to count for any noise that may
occur. If noise accidentally bumps the wave bellow or above a certain line it cannot mess up the count.

The other thing changed for the FPGA board was the outputting alarm signal. Instead of using a
function generator, the FPGA board came with an audio jack which is simply controlled by a high-low
waveform. Any set of computer speakers or headphones can easily be hooked up to the device and used
for the alarm.

IX.
Module Level Requirements and Specifications (Hardware)
Requirements Detailed Module Functional Requirements
1. The headband that will be fitted onto the user should have an adjustable strap to fit the range of
head sizes that a potential user may have. The headband should also be comfortable enough to
allow the user to sleep.
2. The device should be large enough for to provide ease of interaction with the buttons with the
use of a small-sized index finger. The device should be small enough that it only takes a small
amount of space on any given surface.
Specifications Detailed Module Functional Specifications
1. The desktop unit will be no longer than 45.7 centimeters, no thicker than 25 centimeters, and no
taller than 20 centimeters.
2. The headband will be adjustable with a range of 48-63.5 centimeters in circumference.

X.
Implementation Plan

To integrate all of the modules into one device, a number of implementation decisions must be
considered. Most of these implementation decisions will be made in conjunction with the designing of
the hardware module. The main implementation decision is the size of the enclosure, which must hold
multiple EEG circuits (one for each lead) as well as the FPGA board. The enclosure must also have holes
for inputs for the electrodes to the EEG circuits, as well as holes for the FPGAs knobs and LED display.
To make the best use of the space given in an enclosure, the EEG circuits will be stacked (with a small
gap between each board to prevent electrical issues).

As the modules are ready to be synthesized with one another, a number of issues are likely to
arise. The implementation issue most likely to be addressed is the enclosures use of space, and whether
or not it is possible to keep the entire device in a small box. To solve this issue, different conformations
of the circuits and FPGA will be made to see which one makes the smallest overall device.

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XI.

Timeline Estimation and Milestones

Figure 25 Gantt Chart for EAC

Prototype Plan
The prototype plan simply requires a design engineer to develop what exactly should be made for the
prototype.
Design Engineer: $57/hr for 10 hours = $570

Prototype Code and Debugging
This requires a hardware engineer to take what the design engineer created and implement it on an
actual board.
Hardware engineer: $48/hr for 20 hours = $960

Prototype Board Assembly and Troubleshooting
A hardware engineer must implement the circuit planned by the Design Engineer and troubleshoot any
errors that may arise.
Hardware engineer: $48/hr for 20 hours = $960

CDR Documentation:
Technical Writer: $30/hour for 10 hours = $300

FPGA Clock Code:
Hardware engineer: $48/hr for 8 hours = $384

FPGA Clock Debugging:
Hardware Engineer: $48/hr for 4 hours: $192



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FDR Documentation:
Technical Writer: $30/hr for 10 hours = $300

FPGA Algorithm Code:
This is the largerpart of the code and is the heart at what the hardware engineer must figure out to
implement. Thus the creation of the code and debugging it will consume the most time for the engineer
to create.
Hardware Engineer: $48/hr for 40 hours = $1920
FPGA Alarm Code:
Hardware Engineer: $48/hr for 8 hours = $384
FPGA Overall Debugging:
Hardware Engineer: $48/hr for 40 hours = $1920
Tweaking and Testing:
Test Engineer: $36/hr for 20 hours = $720
FPR Documentation:
Technical Writer: $30/hr for 20 hours: $600
Demo Preparation and Documentation:
Hardware Engineer: $48/hr for 10 hours = $480
Technical Writer: $30/hr for 5 hours = $150
Total: $630
XII.

Labor Costs Graph

Cost ($)

Phase in Project
Figure 26 Labor Costs Graph


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XIII.

Economic Analysis

For the prototype, the labor cost of the hardware engineer and the design engineer were added
up, along with the 200 for the FPGA board. It has been estimated that if we buy the parts in stalk, it will
add up to 100$ per unit, thus giving us the cost for production which is shown below. We then have to
take packaging and distribution into consideration. 14$ for packaging because the device needs to be
safely packaged for travel since it it a fairly fragile device. Also, instructions and details on the device
have to be printed out and placed in with every product as well. The wholesale price and retail price are
based off the overall cost per device assuming 1000 are sold. This produces the results as follows:

Cost to develop prototype: $7250 (labor of 7050 + 200 for hardware)
Cost for production of 1000 units: $100/part * 1000 units = $100,000
Packaging costs: $10 *1.4 = $14
Distribution Costs: $5
Estimated wholesale price: (Total cost per unit= $126.50) x 1.2 = $151.8
Estimated retail price: (Wholesale price) x 1.5 = $227.7
XIV.

Applicable Engineering Standards

IEC60601-2-5 201.8.1 is an international standard in which electrical stimulating equipment

must protect from electrical hazards. AAMI ES60601-1 4.6 is a similar standard for system parts that
contact patients. The EEG portion of the EEG Alarm Clock connects directly to the user, allowing an
electrical current to pass through the body. Thus, it is necessary for the user to be protected from
electrical hazards as defined in the aforementioned standards.

The EAC is powered by two AA batteries, supplying the device with 3V. Because the EAC is
considered a medical device, it must comply with AAMI ES60601-1 4.10.1, which defines the conditions
for proper powering of such devices. The standard calls for an internal electrical power source, which is
fulfilled by the two AA batteries inside the enclosure. The power input must also comply with the
standard set forth by AAMI ES60601-1 4.11, which lists a number of tests that define the compliance of
the input.


All standards for the FPGA board come from IEEE. The standard included for the Xilinx FPGA
board is the IEEE standard 1532. This standard has multiple sections. First, it states that a programmable
logic device must have: architectural components for configuration, algorithm description framework,
and a configuration data file. Its next section is a standard on files on the device, and that they require
initialization, the body, and termination. Standard 1532 also provides many predefined functions that
must be on an FPGA board but will not be listed here. To summarize, IEEE standard 1532 places
standards on the configuration architecture, the algorithm extensions, and the data file formatting for
the FPGA board.
Reference: http://www.xilinx.com/support/documentation/application_notes/xapp500.pdf,
AAMI and IEC standards listed on Blackboard

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XV.
Parts List
INA128P
Part number: INA 128P
Descrption: Instrumentation amplifier used to amplify biopotential signals
Manufacturer's Name: Texas Instruments
Manufactuer's Part Number: SBOS051B
Cost- Volume quantities: $0 per unit/8 units
LM741
Part number: LM741
Descrption: Operational amplifier used to amplify signals
Manufacturer's Name: National Semiconductor
Manufactuer's Part Number: LM741
Cost- Volume quantities: $0 per unit/16 units
Spartan 3AN
Part number: 3AN
Descrption: FPGA board that can be programmed to run a specific function.
Manufacturer's Name: Xilinx
Manufactuer's Part Number: XC3S50AN
Supplier's Name: Xilinx
Supplier's Catalog Number: DS557
Cost- Volume quantities: $200 per unit

XVI.

Module Matrix

XVII.

Summary and Conclusions

EEG Module

Microprocessor
Hardware Module
Module
Design
90% (20 hours/5 hours) 80% (30 hours/6 hours) 65% (1 hour/15 hours)
Implementation
80% (10 hours/15
75% (30 hours/60
15% (0 hours/15 hours)
hours)
hours)
Testing
70% (5 hours/12 hours) 80% (10 hours/30
0% (0 hours/15 hours)
hours)
Documentation
75% (20 hours/20
75% (20 hours/20
0% (0 hours/5 hours)
hours)
hours)
Figure 27 Module Matrix displaying progress of modules with (actual hours spent/predicted hours
remaining)

Since beginning the project in Spring of 2010, the EAC has gone from a theory presented in the
PDR, to a mini-project presented in the Proof-of-Principle, to a semi-functional unit presented in two
different prototypes based on the modules. Steady progress has been made, with new discoveries made
regularly that would help make the EAC more efficient and cost-effective. Now that the prototypes have
been made, they must be refined and integrated with each other to create the final EEG Alarm Clock.



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The EEG design proved to be prone to many hardware glitches, including the interference of
noise. A simple prototyping breadboard also adds to the probability of hardware error when detecting
and analyzing signals. This has proven to be a hindrance to the interfacing between the EEG circuit and
the FPGA.
Learning how to properly use the board for the purposes necessary in the EEG alarm clock
turned out to be an arduous task. The Spartan 3AN FPGA board is not usually used for the purposes of
reading analog signals and then conducting the signal processing on them. The analog-to-digital
converter on the board is not very user friendly and is designed for much higher sampling rates than
what is needed for an EEG signal. This, as well as the FPGA chip itself, which is best designed for
simulations and testing, required a lot of creativity to engineer a way around it. The LCD screen also had
a high learning curve to properly use. In the end, the board does everything required of it to properly
read an amplified EEG signal and wake up the user at the right time.

Historical Perspective
Initially, the EEG circuit was to be completed with relative ease, as the prototype was able to
handle sinusoids without error. However, it was soon discovered that the circuit was prone to picking up
noise, and that certain portions of the circuit diagram did not function properly. Design changes were
made, reimplmented, and retested for functionality.
The FPGA board had a slow start since finding the right board to do the task at hand took a good
amount of research and some time was even spent on a board that wouldn't work. An Adruino board
was first used for multiple months. When the Spartan 3AN was finally picked out online, it was not clear
whether or not it could really work for reading and processing EEG signals. A lot of research and trial and
error went into attempting to get the Spartan 3AN to work properly with reading analog signals.
Eventually, when progress was made on the front of analog-to-digital conversion, the approach for the
rest of the project fell into place. The rest of the project was not easy nor take little time, but the goals
and the milestones that were to be reached were finally established. The rest of the coding of the board
was a slow steady climb from there.

XVIII.

User Manual
Initially, the EEG circuit was to be completed with relative ease, as the prototype was able to
handle sinusoids without error. However, it was soon discovered that the circuit was prone to picking up
noise, and that certain portions of the circuit diagram did not function properly. Design changes were
made, reimplmented, and retested for functionality.
The FPGA board had a slow start since finding the right board to do the task at hand took a good
amount of research and some time was even spent on a board that wouldn't work. An Adruino board
was first used for multiple months. When the Spartan 3AN was finally picked out online, it was not clear
whether or not it could really work for reading and processing EEG signals. A lot of research and trial and
error went into attempting to get the Spartan 3AN to work properly with reading analog signals.
Eventually, when progress was made on the front of analog-to-digital conversion, the approach for the
rest of the project fell into place. The rest of the project was not easy nor take little time, but the goals
and the milestones that were to be reached were finally established. The rest of the coding of the board
was a slow steady climb from there.

XVIV.

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XVV.

Qualifications of Key Personnel

The EEG Alarm Clock is being designed and built by two rising senior engineering majors. Zahin
Hasan, a Biomedical Engineering major, has taken multiple circuitry classes, as well as the Biomedical
Engineering Practices & Principles course in which applications of EEGs are explored. Alex Magnano, a
Computer Engineering major, has taken many different computer engineering and computer science
courses, including an Embedded Systems course, which explores the applications of microcontrollers.
Both members have a fundamental understanding for circuitry and digital signal processing.
XVVI.

Teaming Arrangements
The EAC is split into three components: the EEG component, the Signal Processing component,
and the Microcontroller component. Zahins responsibility is the EEG component, as he has had the
most experience with building circuits and applying EEGs. Alexs responsibility is the Microcontroller
component, as he is the only one who understands the necessary code and has utilized microcontrollers
in the past.

XVVII. Works Cited

Cherry, Kendra. "Stages of Sleep - The Five Stages of Sleep." Psychology - Complete Guide to
Psychology for Students, Educators & Enthusiasts. About.com. Web. 29 Apr. 2011.
<http://psychology.about.com/od/statesofconsciousness/a/SleepStages.htm>.
Griffiths, Dan, Nelo, Andreas Robinson, Jack Spaar, and Yaniv Vilnai. "The ModularEEG
Design." The OpenEEG Project. 2003. Web. 29 Apr. 2011.
<http://openeeg.sourceforge.net/doc/modeeg/modeeg_design.html>.
"LM741 Operational Amplifier." National Semiconductor | High-performance Analog. National
Semiconductor, Aug. 2000. Web. 21 Nov. 2011.
<http://www.national.com/pf/LM/LM741.html>.
"Precision, Low Power INSTRUMENTATION AMPLIFIERS." Texas Instruments. Texas
Instruments, Feb. 2005. Web. 21 Nov. 2011. <http://www.ti.com/litv/pdf/sbos051b>.
"Sallen-Key Low Pass Filter Design Equations." Electronics, PCB Design and PCB Layout.
Daycounter, Inc. Web. 21 Nov. 2011. <http://www.daycounter.com/Filters/SallenKeyLP/Sallen-
Key-LP-Filter-Design-Equations.phtml>.

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Spring 2012