Huong Dan Thao Tac Zen Phan 1 - Tran Ngoc Binh PDF

Vn phng i din OMRON ti Vit nam
Hng dn thao tc vi ZEN
Mc lc
1 La chn ngn ng hin th ............................................................................................... 3
2 t thi gian ngy thng ................................................................................................... 3
3 Lp chng trnh bc thang: ............................................................................................. 4
3.1 Ni dy u vo/ra v hot ng bn trong:............................................................ 5
3.2- Xo chng trnh ...................................................................................................... 5
3.3- Vit chng trnh bc thang ..................................................................................... 6
V cc u vo...................................................................................................................... 8
V u ra............................................................................................................................... 9
4 Kim tra hot ng ca chng trnh bc thang ............................................................. 11
Cc th tc kim tra hot ng ........................................................................................... 12
Kim tra hot ng .............................................................................................................. 12
5 Sa chng trnh bc thang: ........................................................................................... 13
5.1 Thay i u vo.................................................................................................... 13
5.2 Sa i cc chc nng ph khc cho u ra bit .................................................... 14
5.3 Xo cc u vo, u ra v cc ng ni............................................................ 14
5.4 Chn cc dng ....................................................................................................... 14
5.5 Xo cc dng trng ................................................................................................ 15
6 S dng Timer (T) v Timer c lu (Holding Timer) (#).................................................. 16
6.1 Cc dng Timer thng (T0 n T7)...................................................................... 16
6.2 Dng Holding Timer (#0 n #3)............................................................................ 17
6.3 Thit lp trong mn hnh sa chng trnh bc thang............................................ 17
6.4 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 17
6.5 Trang theo di thng s (Parameter Monitor)........................................................ 18
7 S dng b m (Counter) ............................................................................................. 18
Hot ng............................................................................................................................ 18
7.1 Thit lp thng s trong mn hnh sa chng trnh bc thang............................. 19
8 Weekly timer (k hiu @)................................................................................................ 20
9 Calendar Timer (k hiu * ) ............................................................................................. 22
Hot ng............................................................................................................................ 22
10 u vo tng t (analog input) v b so snh tng t (analog comparator).......... 24
Hot ng............................................................................................................................ 24
11 So snh gi tr hin ti (PV) ca counter v timer dng b so snh kiu P: .............. 26
Hot ng............................................................................................................................ 26
12 Cc bit thng bo hin th (Display bit)....................................................................... 28
13 Dng cc bit nt bm (B)............................................................................................ 30
S dng bit nt bm ............................................................................................................ 31
Trang 2
1 La chn ngn ng hin th

C th la chn ti 6 ngn ng hin th trn mt hin th LCD ca ZEN l
Anh, Php, Italia, c, Ty Ban Nha v Nht. Mc nh l ting Anh.
Ch : Khng nn thay i ngn ng hin th v vic i tr li sang ting Anh
c th kh khn khi hin th mt ngn ng khc.
Bt in
Bm OK chuyn sang trang Menu
Bm 4 ln chuyn con tr ti
LANGUAGE
Bm OK hin th ngn ng hin ti, Ch

cui ca ngn ng s nhp nhy (ch H
trong hnh)
Bm OK lm cho c t nhp nhy. By

gi ta c th la chn ngn ng khc dng
ph m /.
2 t thi gian ngy thng
Thi gian ngy thng khng c t khi xut xng. C th t thi gian
ngy thng cho cc model ca ZEN c h tr t nh nng ngy thng
PROGRAM
RUN
Sau khi bt in, bm OK hin th thit lp
PARAMETER
SET CLOCK
cho ng h. Chn SET CLOCK
SET CLOCK
SUMMER TIME
Bm OK vo trang hin th thi gian v
ngy thng hin ti. Ch s bn phi ca
ngy thng s nhp nhy
SET CLOCK
YY/MM/DD
00/01/01
00:03 (SA)
Trang 3
t thi gian v ngy thng

SET CLOCK Dng cc ph m mi tn ln/ xung thay
YY/MM/DD
00/04/01 i
11:35 (SU)
Dng cc ph m mi tn tri/phi thay i
v tr con nhy
Khi ngy thng c thay i, ngy th
cng t ng thay i theo. K hiu ca th
trong tun nh bng di y:
SET CLOCK SU: Sunday

SET ? MO: Monday
OK/ESC TU: Tuesday
11:35 (SU) WE: Wednesday
TH: Thursday
FR: Friday
SA: Saturday
Bm OK hin th trang xc nhn thay i. Bm tip OK chp nhn thay

i
Ch :
- Nu tt in trong 1 thi gian di (2 ngy hoc hn 250C), thi gian
ngy thng s b t li (reset) v gi tr mc nh l 00/1/1; 00:00 (SA)
- Nm c th c t trong khong t 2000 n 2099
SET CLOCK S - Vi cc nc c phn bit gi theo ma, nu chn
YY/MM/DD
01/05/01
gi ma h (Summertime) th S s c hin th
11:35 (SU) bn phi trn cng trong thi gian ma h.
- Nm c hin th v t theo th t sau: nm/thng/ngy
3 Lp chng trnh bc thang:

Chng trnh mu
on sau y hng dn cch nhp 1 chng trnh bc thang: theo nh

chng trnh mu trn.
Trang 4
3.1 Ni dy u vo/ra v hot ng bn trong:
u ni ngun cp
Ni cc cng tc SW1 v SW2 vo

cc u ni input I0 v I1
Khi cng tc SW1 bt hay tt, Bit I0

(s (1) trn chng trnh bc thang)
cng bt hoc tt. Tng t vi cng
Chng tc SW2 v bit I1
trnh bc
thang Khi chng trnh chy ch RUN
v cng tc SW1 bt, Bit I0 bt ln
v cng lm bit u ra Q0 bt. Khi
tip im u ra (output contact)
cng bt theo (ch th bi s (3) trong
chng trnh)
Khi tip im u ra (output
contact) bt ln (ch th bi s (3)
trong chng trnh), ti ni vi u
Ti ni u ra Q0 cng c bt
3.2- Xo chng trnh
Cn phi xo chng trnh trong b nh ca ZEN trc khi vit 1 chng trnh
mi. Khi dng lnh DELETE PROG xo, ch c phn chng trnh l b
xo, cn cc phn khc nh ngn ng hin th , thi gian ngy thng v cc
thit lp khc khng b nh hng.
Cn phi chuyn ZEN v ch STOP (ch dng) mi xo c chng
trnh.
PROGRAM Bm OK chuyn v mn hnh Menu v

RUN
PARAMETER chn PROGRAM
SET CLOCK
EDIT PROG Chn DELETE PROG

DELETE PROG
DELETE PROG
DELETE ?
OK/ESC
Bm OK hin th trang xc nhn thay
i.
EDIT PROG Bm tip OK chp nhn thay i

DELETE PROG Sau mn hnh s quay li hin th mn
hnh trc ca Menu
Trang 5
3.3- Vit chng trnh bc thang
Cn phi chuyn ZEN v ch STOP mi vit hay thay i c chng

trnh.
PROGRAM Bm OK chuyn v mn hnh Menu v

RUN
PARAMETER chn PROGRAM
SET CLOCK
EDIT PROG
DELETE PROG
Chn EDIT PROGRAM
Sau mn hnh hin th nh sau:

Hin th s ca dng trong chng trnh ti v tr con tr
Con tr nhp nhy trng thi o
Bm OK chuyn sang trang sa chng trnh bc thang
Cc hot ng khi trang sa i chng trnh bc thang:
Ti 1 thi im ch c th hin th c 2 dng trong mch ca chng trnh

bc thang trong mn hnh Edit Screen.
Mi b ZEN c th cha ti 96 dng, mi dng c th gm 3 input

condition l cc tip im u vo v 1 output.
Chng trnh v d mu
Cc chc nng ph thm cho u ra

Hin th s ca dng trong chng trnh ti v tr con tr
Hin th khi c nhiu dng chng trnh di. Dng ph m mi tn xung hin th tip
Hin th khi c nhiu dng chng trnh trn. Dng ph m mi tn ln hin th tip
Trang 6
Trong hnh trn, y:

- Bit Type: l loi a ch bit ang c dng. Xem bng cc a ch trong
PLC
- Bit Address: l a ch bit ang c dng
- Connection Line: ng ni gia cc tip im
- N.O v N.C input: cc u vo tip im thng m v thng ng
Cc v tr cho vic vit cc u vo, u ra v ng ni
a- Vit u vo cho I0
Bm OK hin th v tr vit ban u (u

vo NO a ch I0) v chuyn con tr nhp
nhy v v tr Bit type. Dng cc ph m mi
tn ln xung la chn loi ca bit (Bit
type). Dng ph m mi tn chuyn
sang v tr a ch bit v bm cc ph m mi
tn ln xung thay i a ch bit
Bm nt OK hai ln hon tt vic nhp
a ch I0. Con tr gi y chuyn sang v tr
nhp tip theo.
b- Vit tip u vo I1 ni tip vi I0
Bm OK hin th li tip im u vo NO
v a ch I0
Bm ALT chuyn sang loi tip im l

NC (Bm ALT chuyn v loi tip im l
NO)
Bm ph m mi tn phi chuyn con tr

nhy sang v tr a ch bit v dng ph m mi
tn ln UP chuyn thnh 1
Bm OK chuyn con tr sang v tr nhp tip

theo. ng ni (connection line) s t ng
c ni gia tip im I0 v tip im I1
Trang 7
V cc u vo
K hiu cc u vo
Cc vng nh (cc loi a ch)
K hiu M t Loi a ch bit v s

I Cc bit u vo ca module c CPU I0 --> I5 (6 u)
Q Cc bit u ra ca module c CPU Q0 --> Q3 (4 u)
X Cc bit u vo ca module m rng X0 --> XB (12 u) (1)
Y Cc bit u ra ca module m rng Y0 --> YB (12 u)(1)
M Cc bit t do dng trong chng trnh M0 --> QF (16 bit)
(work bit)
H Cc bit t do dng trong chng trnh c H0 --> HF (16 bit)
lu trng thi (holding bit)
B Cc bit bo trng thi cc nt bm B0 --> B7 (8 bit) (2)
Ghi ch (1) Ch dng c khi ni cc module m rng vi module CPU

(2) Ch dng c vi model c mn hnh LCD
Cc timer, counter v b so snh gi tr (analog comparator)
K hiu M t Loi a ch bit v s

T Timer tr thng thng T0 --> T7 (8 timer)
# Timer c lu trng thi khi mt in #0 --> #3 (4 timer)
(Holding Timer)
@ Timer tun (Weekly Timer) @0 --> @7 (8 timer) (1)
* Timer ngy thng (Calendar Timer) *0 --> *7 (8 timer) (1)
C Counter C0 --> C7 (8 counter)
A B so snh tng t (Analog A0-A3 (4 b so snh) (2)
Comparator)
P B so snh thng P0-PF (16 b so snh)
Ghi ch (1) Ch dng c khi dng vi module CPU c chc nng l ch

v ng h thi gian thc
(2) Ch dng c vi model CPU c ngun DC
Bm nt ALT chuyn sang ch ghi

ng ni. Con tr hnh mi tn ch sang tri
s nhp nhy
Bm nt v 1 ng ni vi u ra
Trang 8
V u ra
Cc chc nng ph thm khc
Cc vng nh cho u ra
K hiu 3.1.1.1.1.1 M t Loi a ch bit v s

Q Cc bit u ra ca module c CPU Q0 --> Q3 (4 u)
Y Cc bit u ra ca module m rng Y0 --> YB (12 u)(1)
M Cc bit t do dng trong chng trnh M0 --> MF (16 bit)
(work bit)
H Cc bit t do dng trong chng trnh c H0 --> HF (16 bit)
lu trng thi (holding bit)
Cc chc nng ph thm khc cho cc bit u ra
K hiu M t
[ Hot ng ca u ra output s nh bnh thng
S Khi c bt bi lnh output kiu S (Set) ny, bit u ra s gi
nguyn trng thi bt k c sau khi cc bit i trc l OFF v ch b
tt vi lnh output kiu R
R Khi c tt bi lnh output kiu R (Reset) ny, bit u ra s gi
nguyn trng thi tt k c sau khi cc bit i trc l OFF v ch
c bt vi lnh output kiu S
A Mi khi lnh output kiu A (Alternate) c thc hin bit output s
chuyn sang trng thi ngc li, v d khi ang ON s chuyn
sang OFF v ngc li
Gin ca cc lnh output
Q0 bt v tt Q1 bt v vn Q2 tt khi I2 bt Q3 chuyn
khi I0 bt v tt ON khi I1 bt ri trng thi gia
tt ON v OFF mi
khi I3 bt
Trang 9
Timers, Holding Timers, Counters, v Display Output
K hiu M t Loi a ch bit v s Loi u ra

T Timer T0 --> T7 (8 timer) T: u vo k ch
# Timer c lu trng #0 --> #3 (4 timer) hot timer
thi khi mt in R: u vo
(Holding Timer) Reset cho timer
C Counter C0 --> C7 (8 counter) C: u vo m
cho counter
D: Chiu m
cho counter
R: u vo
reset cho
counter
D Bit hin th (Display D0-D7 (8 bit) D
bit) (ch cho model c mn
hnh)
c- Vit u ra cho bit Q0
Bm ln na v mt ng ni vi u ra
v chuyn con tr v v tr ghi u ra
Bm OK hin th gi tr ban u cho u ra

(u ra bnh thng/Q0) v chuyn con tr nhy
v v tr loi bit Q.
Dng cc ph m mi tn ln /xung / la
chn loi bit. Dng cc ph m v di
chuyn con tr v dng v chn cc chc
nng khc hay chn a ch bit.
Bm nt OK hai ln hon tt vic nhp a

ch Q. Con tr gi y chuyn sang v tr nhp
input u dng tip theo.
d- Vit 1 tip im Q0 song song vi I0
Bm OK hin th I0 ri chuyn con tr v v tr

la chn loi bit
Bm la chn loi bit l Q
Bm nt OK hai ln hon tt vic nhp a

ch I0. Con tr gi y chuyn sang v tr nhp
tip theo.
Trang 10
e- V cc ng ni cho mch song song (mch OR)
Bm ALT khi con tr ang im gia 2 v tr cn ni, con tr s chuyn sang

hnh v cho ph p v cc ng ni. Bm cc ph m , , , v cc
ng ni ngang v thng ng.
Ch v cc ng ni s c thot ra khi n u hay cui mi dng
hoc khi ph m OK hay ESC c nhn.
Bm ALT chuyn sang ch v cc ng

ni
Bm ng thi v c ng ni thng ng
v ngang. Du cng (+) biu th giao im.
Bm OK hon tt vic v ng ni v
chuyn sang con tr nhp nhy.
Bm ESC kt thc hot ng v.
Bm tip ESC tr v mn hnh Menu
Ch :
- Khng vit chng trnh vi cc ng ni to thnh vng k n. Chng trnh

c th hot ng khng ng nu v nh vy
- Lun lun bm ESC quay tr v mn hnh Menu. Nu khng quay tr v
mn hnh Menu trc khi tt in, cc thit lp v chng trnh s b mt.
4 Kim tra hot ng ca chng trnh bc thang

Hy lun kim tra hot ng ca chng trnh bc thang trc khi a ZEN
vo hot ng tht.
Ch :
- Trc khi bt in, hy kim tra dy ngun, dy u vo v mch u

ra u c ni ng v tt
- Nn tho b dy ni vi ti ca u ra trc khi hot ng th trnh
cc s c c th xy ra
- Lun lun m bo an ton vng xung quanh trc khi bt in
ngun
Trang 11
Cc th tc kim tra hot ng
Kim tra trc khi bt ngun
1. Kim tra rng ZEN c lp v u dy ng

2. Kim tra nu c s c g c th xy ra khi ZEN hot ng
3. Bt ngun cho ZEN. Chuyn ZEN sang ch RUN
Kim tra hot ng
4. Bt mi u vo ln ON hoc v OFF v xem chng trnh c hot

ng ng khng
5. iu chnh li khi c vn
Phng php kim tra hot ng
Vi loi c mn hnh LCD Kim tra bng cc hin th u vo v

u ra nhp nhy
Vi loi khng c mn hnh LCD (loi Ni ZEN vi phn mm ZEN Support
ch th bng n LED) Software v kim tra bng chc nng
monitor.
Kim tra hot ng
Thay i ch hot ng
Bm OK hin th mn hnh Menu v bm

chuyn con tr n RUN
PROGRAM
RUN Bm OK chuyn t STOP sang RUN
PARAMETER
SET CLOCK
MONITOR
STOP
PARAMETER
SET CLOCK
Trang 12
Kim tra hot ng Kim tra hot ng dng chc nng

mn hnh ch nh theo di chng trnh bc thang
PROGRAM Chn Monitor

Bm ESC STOP
chuyn sang PARAMETER ch RUN
SET CLOCK
mn hnh ch nh
Bm ph m OK
chuyn sang mn
hnh theo di
chng trnh bc
thang
Q0 s ON khi
I0 ln ON
Q0 s ON khi I0
ln ON. Khi bit
ny ON, cc
ng ni ng
v ngang s
Q0 s vn ON m ln
k c khi I0 v
OFF
Q0 s v OFF
khi I1 bt ln
ON
5 Sa chng trnh bc thang:

5.1 Thay i u vo
Di chuyn con tr v v tr cn thay i u

vo
Bm OK i con tr sang dng nhp

nhy v chuyn con tr sang v tr nhp loi
bit.
Bm ph m / la chn M
Bm chuyn sang v tr nhp loi bit.
Dng ph m / thay i i ch bit t 0
ln 1.
Bm OK hon tt
Trang 13
5.2 Sa i cc chc nng ph khc cho u ra bit
By gi ta s thay i chc nng u ra bit sang S (tc SET)
Di chuyn con tr v v tr cn thay i u

ra
Bm OK i con tr sang dng nhp

nhy
Bm chuyn con tr sang v tr thay i
chc nng u ra.
Bm ph m hai ln chuyn chc nng
u ra t [ thnh S
Bm OK hon tt
5.3 Xo cc u vo, u ra v cc ng ni
Di chuyn con tr ti v tr ca u vo, u ra hay ng ni cn xo v bm

DEL.
V d: Xo u vo ni tip M3
Bm DEL xo u vo v xo lun
ng ni i cng
V d: Xo cc ng ni thng ng
Di chuyn con tr ti v tr ca u vo bn
phi ca ng ni ny. Bm ALT
chuyn sang ch v ng ni. Con tr
chuyn sang hnh mi tn
Bm DEL xo
5.4 Chn cc dng
chn 1 dng trng, chuyn con tr v u dng cn chn thm 1

dng trng v n ALT
Trang 14
Mt dng mi s c chn ti y
Bm ALT chn ti y
Dng trng
chn mch song song (mch OR), cc u vo c th c thm

vo gia cc u vo song song.
Chuyn con tr v u dng cn chn thm 1 dng trng v n ALT
Mt dng mi s c chn ti y
Bm ALT chn thm khong

trng rng 1 dng gia cc u vo
song song.
Cc ng ni thng ng s c
t ng k o di
5.5 Xo cc dng trng
xo 1 dng trng, chuyn con tr v v tr u ca dng cn xo v n

DEL.
Dng ny s c xo
Bm ALT xo dng trng

Cc dng ph a di s c t ng
chuyn ln
Trang 15
6 S dng Timer (T) v Timer c lu (Holding Timer)

(#)
ZEN c sn 8 timer thng (T) v 4 holding timer (#):
Timer Gi tr hin hnh (PV) s b xo (reset) khi timer chuyn t

RUN sang STOP hoc khi ngt in
C 4 dng timer thng c th s dng
Holding timer Gi tr hin hnh (PV) s vn c lu khi timer chuyn t
RUN sang STOP hoc khi ngt in. Timer li tip tc khi u
vo k ch (trigger) ln ON. Bit u ra ca timer cng c gi
nguyn trng thi khi timer m xong.
C 1 dng holding timer
6.1 Cc dng Timer thng (T0 n T7)
Loi timer Hot ng Loi ng

K hiu dng
ch nh
X On Bt sau 1 Tr thi
DELAY khong thi gian
timer gian t trc
sau khi u
vo trigger ln
ON
J OFF Vn ON t thi
DELAY trong khi u gian cho
timer vo trigger ON chiu sng
v tt sau 1 v qut
khong thi thng gi
gian t trc
sau khi u
vo trigger v
OFF
O One-shot Vn ON
pulse trong 1 khong
timer thi gian t
trc khi u
vo trigger bt
ln ON
F Flashing Bt v tt lp i Mch bo
pulse lp li trong ng bo
timer khong chu k ci v n
t trc trong nhp nhy
khi u vo
trigger ON
Trang 16
6.2 Dng Holding Timer (#0 n #3)
Loi timer Hot ng Loi ng

dng
ch nh
X On Bt sau 1 Tr thi
DELAY khong gian c
timer thi gian yu cu
t trc tip tc
sau khi tr li sau
u vo khi mt
trigger ln in
ON
6.3 Thit lp trong mn hnh sa chng trnh bc thang
Cc u vo trigger, u ra reset v cc thng s ca timer c v mn

hnh Sa chng trnh bc thang.
Timer address T0 n T7 hoc #0 n #3

( a ch timer)
Trigger input T (TRG) iu khin u vo trigger ca timer.
S k ch hot timer khi u vo trigger
bt ln ON
Reset input R (RES) iu khin u ra reset ca timer. Khi
u vo reset bt ln ON, gi tr hin ti
ca timer (PV) b xo v 0. Trng thi
u vo trigger s b b qua trong khi
u vo reset input ON
Timer bit S bt tu theo loi timer
6.4 t thng s trong trang thit lp thng s (Parameter Settings)
Trang 17
Timer Type
Time Unit (n v thi gian)
S 00,01 n 99,99s (theo n v 0,01 giy) Sai s: 0 n 10ms

M:S 00 pht 01s n 99 pht 59s (theo n v Sai s: 0 n 1s
pht giy)
H:M 00 gi 01 pht n 99h 59 pht (theo n v Sai s: 0 n 1 pht
gi pht )
Monitor Enabled/Disabled
A Cc thng s c th c theo di v thay i

D Cc thng s khng c ph p theo di v thay i
6.5 Trang theo di thng s (Parameter Monitor)
Trng thi ca cc thng s v u vo ra ca timer c th c theo di

trong trang ny.
7 S dng b m (Counter)
C th s dng ti 8 b m ch m tng hay m gim. Gi tr hin
hnh ca counter (Present Value - PV) v trng thi ca u ra counter c
lu c khi ch hot ng ca ZEN thay i hay khi mt in.
Hot ng
Bit u ra ca counter (counter bit) bt ln ON khi gi tr m (hay gi tr hin

hnh Present Value PV) vt qu gi tr t (set value - SV) (PVSV). Gi tr
m s quay v 0 v bit u ra tt khi u vo reset bt ln ON. Cc u vo
m b b qua trong khi u vo reset ON.
Trang 18
7.1 Thit lp thng s trong mn hnh sa chng trnh bc thang
Cc u ra cho u vo ca counter, chiu m (counter direction) v u

vo reset c vit trong mn hnh sa chng trnh. Cc thng s thit lp
cho counter c t trang thit lp thng s (Parameter Setting)
Counter address C0 n C7
( a ch counter)
Counter input C (CNT) S tng hay gim gi tr m PV mi khi u
(u vo m) vo ny bt ln ON
Counter direction D (DIR) Chuyn gia ch m tng hay gim:
input OFF: m tng
(Xc nh chiu ON: m gim
m)
Reset input R (RES) iu khin u ra reset ca counter. Khi u
(Reset) vo reset bt ln ON, gi tr hin ti ca
counter (PV) b xo v 0 v bit u ra
counter v OFF. Trng thi u vo m s
b b qua trong khi u vo reset input ON
Timer bit S bt khi b m m n gi tr t (PVSV)
Trang 19
Set Value 0001 n 9999 ln

A Cc thng s c th c theo di v thay
Monitor i
enabled/disabled D Cc thng s khng c ph p theo di v
thay i
Trng thi ca cc thng s v u vo ra ca counter c th c theo di

trong trang ny.
Ch :
1. xo gi tr hin ti ca counter (PV) v bit u ra ca counter
(counter bit) khi ngt in hay khi thay i ch hot ng,
hy to 1 mch xo (reset) lc bt u thc hin chng trnh.
Sau y l 1 v d:
2. Nu u vo m v u vo xc nh chiu (direction) cng

c a vo counter cng lc, hy t u vo xc nh chiu
trc u vo m trong chng trnh.
8 Weekly timer (k hiu @)

Weekly timer s bt ln ON gia cc thi gian bt v tt (start /stop time) inh
trc trong nhng ngy xc nh. C 8 Weekly timer nh s t @0 n @7.
Ngy trong tun
Thi
gian
Trong v d trn, Weekly timer s bt ln ON mi ngy t

th Ba n th Su gia 8:15 v 17:30
Trang 20
Cc u vo ca timer c v mn hnh Sa chng trnh bc thang.
Weekly timer address: @0 n @7 (8 timer)
Set Value 0001 n 9999 ln

Day Start day T Ch Nht n Th By
(ngy) (Sun/Mon/Tues/Wed/Thurs/Fri/Sat)
Stop day T Ch Nht n Th By
(Sun/Mon/Tues/Wed/Thurs/Fri/Sat)
Time Start time 00:00 n 23:59
(thi gian) Stop time 00:00 n 23:59
A Cc thng s c th c theo di v
Monitor thay i
enabled/disabled D Cc thng s khng c ph p theo
di v thay i
Ch : Khi con tr nm start day (ngy bt), bm ri bm / t

ngy tt (stop day). Nu stop day khng c t, timer s ch hot ng theo
thi gian t.
Quan h gia thi gian v ngy bt v tt (Start-Stop Day/Time)
Thng s t V d Hot ng
Khi Start day trc MO-FR Hot ng t Th Hai n
Stop day Th Su hng tun
Khi Start day sau FR-MO Hot ng t Th Su hng
Start-Stop
Stop day tun n Th Hai tun sau
Day
Khi Start day trng MO-MO Hot ng bt k ngy
(ngy)
vi Stop day trong tun
Khi Stop day khng FR- Hot ng ch vo Th Su
c t hng tun
Trang 21
Time Khi Start time trc ON: 08:00 Hot ng t 08:00 n

(thi gian) Stop time OFF: 17:00 17:00 hng ngy
Khi Start time sau ON: 18:00 Hot ng t 18:00 n
Stop time OFF: 07:00 07:00 ngy hm sau
Khi Start time trng ON: 18:00 Hot ng bt k thi gian
vi Stop time OFF: 18:00

trong trang ny.
Ngy hin ti
Thi gian hin ti
9 Calendar Timer (k hiu * )

Calendar Timer (Timer theo ngy trong thng) bt ln ON trong cc ngy nh
trc. C 8 Calendar Timer k hiu t *0 n *7.
Hot ng
Calendar Timer bt ln ON trong cc ngy t 1/4 n

31/8 (1 April 31 August)
Cc u vo ca timer c v mn hnh Sa chng trnh bc thang.
Calendar timer address: *0 n *7 (8 timer)
Trang 22
Start Date T 1/1 n 31/12

(ngy bt)
Stop Date T 1/1 n 31/12
(ngy tt)
Monitor i
thay i
Ch : Ngy thng trong ZEN c hin th theo th t nh sau:

nm/thng/ngy
V d: 4/5 l ngy 5 thng 4
Quan h gia ngy bt v tt (Start-Stop Date)
Thng s t V d Hot ng
Khi Start ON: 04/01 Hot ng t 1/4 n 1/9
date trc OFF: 09/01
Stop date
Khi Start ON: 04/01 Hot ng t 1/4 n 1/2
Start-Stop Day date sau OFF: 02/01 nm sau
(ngy) Stop date
Khi Start ON: 02/01 Hot ng khng k ngy
date trng OFF: 02/01 thng
vi Stop
date
Ch : dng hot ng vo v d ngy 1/4, hy t stop date l ngy sau

ngy tc ngy 2/4

trong trang ny.
Ngy hin ti
Trang 23
10 u vo tng t (analog input) v b so snh

tng t (analog comparator)
C th ni 2 u vo tng t 0-10V vo module CPU ca ZEN (vi model
dng ngun DC). Hai u vo ny l I4 v I5 nh hnh di.
T n hiu tng t c chuyn i thnh dng dng s BCD t 00.0 n 10.0.
Kt qu c th c dng vi 1 trong 4 b so snh tng t (analog
comparator) k hiu A0 n A3. Kt qu ca vic so snh ny c th c
dng lm u vo trong chng trnh.
Thit b cho
t n hiu
analog
Hot ng
V d 1 V d 2
Khi u vo analog I4 5.2V Khi u vo analog I5 I4
u ra ca b comparator s bt ln u ra ca b comparator s bt ln ON
ON khi in p u vo 1 t n khi in p u vo 2 cao hn u vo 1
5,2V hoc cao hn
Ch :
Khng c a t n hiu in p m vo cc u vo I4 v I5. Lm nh
vy c th lm hng cc mch bn trong ZEN.
Trang 24
Cc u vo ca b so snh analog c v mn hnh Sa chng trnh

bc thang.
Analog Comparator address: A0 n A3 (4 comparator)
V d 1 V d 2
Khi so snh u vo analog vi 1 Khi so snh cc u vo analog ( v
hng s (v d I4 hng s) d I5 I4)
D liu so snh 1
D liu so snh 1
Ton t so snh
Ton t so snh
D liu so snh 2 D liu so snh 2
Analog Comparator T A0 n A3
address
D liu so snh 1 I4: u vo analog 1
I5: u vo analog 2
2 I5: u vo analog 2
Hng s: t 00.0 n 10.5
Ton t so snh u ra ca b so snh (analog
comparator bit) s bt khi d liu so snh
1 d liu so snh 2
u ra ca b so snh (analog
comparator bit) s bt khi d liu so snh
1 d liu so snh 2
A Cc thng s c th c theo di v
Monitor thay i
enabled/disabled D Cc thng s khng c ph p theo di
v thay i
Trng thi ca cc thng s v u vo ra ca b so snh v u vo analog

c th c theo di trong trang ny.
Di y l mn hnh khi theo di hai dng so snh.
Trang 25
11 So snh gi tr hin ti (PV) ca counter v timer

dng b so snh kiu P:
Gi tr hin ti (PV) ca counter, holding timer (#) v timer (T) c th c so

snh dng b so snh loi P. C th so snh gi tr hin ti ca 2 counter v
timer thuc cng 1 loi hay so snh vi 1 hng s.
Hot ng
V d 1 V d 2
Khi so snh holding timer #0 Khi so snh counter C1 counter C2

12min34s
Cc u vo ca b so snh analog c v mn hnh Sa chng trnh

bc thang.
Comparator address: A0 n A3 (4 comparator)
Trang 26
V d 1 V d 2
Khi so snh vo analog vi 1 hng s Khi so snh cc u vo analog ( v d

(v d I4 hng s) I5 I4)
Loi so snh Loi so snh

Ton t so snh Ton t so snh
Loi so snh T: Timer

#: Holding timer
C: Counter
D liu so snh 1 T: T0 T7
#: #0 #7
C: C0 C7
2 T: T0 T7
#: #0 #7
C: C0 C7
Hng s:
- t 00.0 n 99.99 khi loi so snh l T hoc
#
- t 0000 n 9999 khi loi so snh l C
Ton t so snh u ra ca b so snh (comparator bit) s bt khi
d liu so snh 1 d liu so snh 2
u ra ca b so snh (comparator bit) s bt khi
d liu so snh 1 d liu so snh 2
A Cc thng s c th c theo di v thay i
Monitor D Cc thng s khng c ph p theo di v thay
enabled/disabled i
Trng thi ca cc thng s v u vo ra ca b so snh c th c theo

di trong trang ny.
Di y l mn hnh khi theo di hai dng so snh.
Trang 27
Ghi ch:
- Bm ALT chuyn d liu so snh gia a ch timer/counter v hng
s
- n v thi gian c xc nh nh sau khi loi so snh l Timer hay
Holding timer:
o Khi hng s c t cho d liu so snh 2, n v thi gian
c t ng nh ph hp vi n v thi gian ca timer trong
d liu so snh 1
o Cc n v thi gian c t ng chnh nh ph hp khi cc
n v thi gian l khc nhau gia timer trong trong d liu so
snh 1 v 2.
12 Cc bit hin th thng bo (Display bit)

Chng trnh trong ZEN c th hin th ln trn mn hnh LCD cc thng bo
t t, thi gian, gi tr hin hnh ca timer/counter hay gi tr ca b so snh
analog. C th hin th nhiu d liu trn cng mn hnh.
V d 1 V d 2
Theo di tnh trng h thng Hin th ngy v thi gian li h thng xut
hin
Thit lp Thit lp
iu kin thc hin cho Display bit
Cc u vo ca bit hin th c v mn hnh Theo di thng s

(Parameter Settings).
Display address: D0 n D7 (8 bit)
Trang 28
Backlight/Display L0 Khng c chiu sng nn. Khng t chuyn

sang mn hnh hin th thng bo (1)
L1 C chiu sng nn. Khng t chuyn sang
mn hnh hin th thng bo (1)
L2 Khng c chiu sng nn. T chuyn sang
mn hnh hin th thng bo (2)
L3 C chiu sng nn. T chuyn sang mn
hnh hin th thng bo (2)
Display start X (v tr ch s): 00 n 11
position Y: (dng): 0 n 3
(V tr bt u
hin th )
CHR Cc k t (ti a 13 k t ch s v k hiu)

DAT Thng/Ngy (5 k t: / )
CLK Gi/pht (5 k t: : )
Display object I4-I5 Gi tr analog (4 k t: . )
T0-T7 Gi tr hin ti ca timer (5 k t: . )
#0-#3 Gi tr hin ti ca timer (5 k t: . )
C0-C7 Gi tr hin ti ca counter (4 k t: )
Monitor i
thay i
Ch :
(1) Khi L0 hay L1 c chn tt chc nng hin th trang thng
bo, trang hin th thng bo s khng c hin th t ng.
Dng cc ph m chuyn ti trang hin th hot ng.
(2) Khi L2 hay L3 c chn bt chc nng hin th trang thng
bo, trang hin th thng bo s c hin th t ng hin th
d liu t. Mn hnh ch nh s khng c hin th . hin
th mn hnh ch nh, phi chuyn CPU v ch STOP.
Trang 29
Thit lp khi hin th ch (khi chn CHR)
Ni hin th cc k t (ti a:12)

Cc k t c th la chn hin th
V tr con tr hin th
V tr bn trong chui hin th

Nhy sng ng thi khi ang t
K t s oc chn
K t trc v sau k t s oc chn
Dng / cun qua cc k t c th la chn

cho hin th
K t c la s nhp nhy v ni bt
Dng ph m chuyn v tr t k t hin th

sang phi. Dng ph m chuyn v tr t k t
hin th sang tri
13 Dng cc bit nt bm (B)

Vi model c mn hnh LCD, mi khi bm 1 nt trn ZEN, bit nt bm tng
ng (Button switch) s thay i trng thi. C 8 bit nt bm, k hiu v a ch
t B0 n B7.
Trang 30
S dng bit nt bm
Cc nt bm c th c dng nh cc ph m n xo gi tr hin hnh ca

counter hay holding bit.
V d:
Bm DEL+ALT ng thi trong khi ang chy reset
counter C2 v 0 v bit H5 v OFF chng trnh bn.
Ch :
- Cc nt bm c th c dng nh l nt hot ng cho mi mn hnh.
Khi dng cc nt nh l cc bit nt bm, hy thc hin cc la chn tu
theo tnh trng ca mn hnh
- Cc nt c th c dng cho cc hot ng h thng ca ZEN nh
la chn menu, bt k bit nt bm c ang c s dng khng.
Khi 1 nt bm c nhn cho cc hot ng h thng ca ZEN, bit
tng ng cng bt. Hy m bo l h thng khng b nh hng
trc khi bm cc nt ny
Trang 31
Cat No: ZEN-MAN-VN-1
OMRON, 2001
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form, or by any means, mechanical, electronic, photocopying,
recording, or otherwise, without the prior written permission of OMRON.
No patent liability is assumed with respect to the use of the information contained herein.
Moreover, because OMRON is constantly striving to improve its high-quality products, the
information contained in this manual is subject to change without notice. Every precaution
has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting
from the use of the information contained in this publication.
Vn phng i din:
Cng ty OMRON ASIA PACIFIC PTE. LTD.
H ni:
2 Lng H, tng 6 (To nh VINACONEX)
Tel : 8313 121 / 8313 122 Fax : 8313 122
E-mail : OMRONHN@FPT.VN
TP H Ch Minh:
99 Nguyn Th Minh Khai, Q1
Tel : 830 1105 / 839 6666 Fax : 830 1279.
E-mail : OMRONHCM@HCM.VNN.VN
Revision: 1 7/01
Produced: TNBINH
Trang 32

Huong Dan Thao Tac Zen Phan 1 - Tran Ngoc Binh PDF

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Vn phng i din OMRON ti Vit nam

Hng dn thao tc vi ZEN

1 La chn ngn ng hin th

Bm OK chuyn sang trang Menu

Bm OK hin th ngn ng hin ti, Ch

Bm OK lm cho c t nhp nhy. By

2 t thi gian ngy thng

t thi gian v ngy thng

SET CLOCK SU: Sunday

Bm OK hin th trang xc nhn thay i. Bm tip OK chp nhn thay

- Nm c hin th v t theo th t sau: nm/thng/ngy

3 Lp chng trnh bc thang:

on sau y hng dn cch nhp 1 chng trnh bc thang: theo nh

3.1 Ni dy u vo/ra v hot ng bn trong:

Ni cc cng tc SW1 v SW2 vo

Khi cng tc SW1 bt hay tt, Bit I0

3.2- Xo chng trnh

PROGRAM Bm OK chuyn v mn hnh Menu v

EDIT PROG Chn DELETE PROG

EDIT PROG Bm tip OK chp nhn thay i

3.3- Vit chng trnh bc thang

Cn phi chuyn ZEN v ch STOP mi vit hay thay i c chng

PROGRAM Bm OK chuyn v mn hnh Menu v

Sau mn hnh hin th nh sau:

Con tr nhp nhy trng thi o

Bm OK chuyn sang trang sa chng trnh bc thang

Cc hot ng khi trang sa i chng trnh bc thang:

Ti 1 thi im ch c th hin th c 2 dng trong mch ca chng trnh

Mi b ZEN c th cha ti 96 dng, mi dng c th gm 3 input

Cc chc nng ph thm cho u ra

Trong hnh trn, y:

Cc v tr cho vic vit cc u vo, u ra v ng ni

Bm OK hin th v tr vit ban u (u

b- Vit tip u vo I1 ni tip vi I0

Bm ALT chuyn sang loi tip im l

Bm ph m mi tn phi chuyn con tr

Bm OK chuyn con tr sang v tr nhp tip

Cc vng nh (cc loi a ch)

K hiu M t Loi a ch bit v s

Ghi ch (1) Ch dng c khi ni cc module m rng vi module CPU

Cc timer, counter v b so snh gi tr (analog comparator)

K hiu M t Loi a ch bit v s

Ghi ch (1) Ch dng c khi dng vi module CPU c chc nng l ch

Bm nt ALT chuyn sang ch ghi

Cc chc nng ph thm khc

K hiu 3.1.1.1.1.1 M t Loi a ch bit v s

Cc chc nng ph thm khc cho cc bit u ra

Gin ca cc lnh output

Timers, Holding Timers, Counters, v Display Output

K hiu M t Loi a ch bit v s Loi u ra

c- Vit u ra cho bit Q0

Bm OK hin th gi tr ban u cho u ra

Bm nt OK hai ln hon tt vic nhp a

d- Vit 1 tip im Q0 song song vi I0

Bm OK hin th I0 ri chuyn con tr v v tr

Bm la chn loi bit l Q

Bm nt OK hai ln hon tt vic nhp a

e- V cc ng ni cho mch song song (mch OR)

Bm ALT khi con tr ang im gia 2 v tr cn ni, con tr s chuyn sang

Bm ALT chuyn sang ch v cc ng

Bm ESC kt thc hot ng v.

Bm tip ESC tr v mn hnh Menu

- Khng vit chng trnh vi cc ng ni to thnh vng k n. Chng trnh

Calendar timer address: 0 n 7 (8 timer)