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A Abar
Bbar B
0
Fig.34 Circuit of XOR gate
VDD
Pull-up
Load
f
nFET
Logic
Array
In the truth table of XOR gate, there are equal number of input
combinations that produce 0s and 1s. Output 0s imply that an nFET chain
is conducting to ground, while an output 1 means that a pFET group
provides support from the power supply. A mirror circuit uses the same FET
topology for the nFET and pFETs. Applying this to the XOR function yields
the circuit in fig.34. The input combinations are shown for each branch. The
mirror effect can be understood by placing a mirror along the output line,
facing either up or down. The mirror image seen in the mirror will be the
other side of the circuit. The advantage of the mirror circuit are more
symmetric layouts and shorter rise and fall times.
9.2 Pseudo-nMOS
Adding a single pFET to otherwise nFET-only circuit produces a
logic family alled Pseudo-nMOS. It uses fewer FETs because only the nFET
logic block is needed to reate the logic. For N inputs, a pseudo-nMOS logic
1
gate requires (N + 1) FETs. In conventional CMOS, the pFET group
is added to reduce the DC power dissipation, but the logic is superfluous.
Standard N-input CMOS gates use 2N FETs.
The basic topology of a pseudo-nMOS gate is shown in Fig.35. The
single pFET is biased active since the grounded gate gives VSGp = VDD. It
acts as a pull-up that tries to pull the output f to the power supply voltage
VDD. If the switch is open , the pFET pulls up the output to a voltage V OH =
VDD. If the nFET switch is closed, then the array acts as a pull-down device
that tries to pull f down to ground.
The disadvantage is that, as pFET is always biased ON, V OL can never
achieve the ideal value of 0V. This can be overcome by adjusting the size of
pFET. The calculation of the size of pFET is done as follows: Consider a
simple inverter. If the input is VDD, output is VOL. If VOL is assumed to be
small, then the pFET will be saturated while the nFET operates in the non-
saturation region. The KCL equation thus assumes the form
n
2
2VDD VTn VOL VOL
2 p
2
VDD / VTp / 2
Which is a quadratic equation for VOL. Solving, we get,
VOL V DD VTn
p
V DD VTn 2 n V DD VTp 2
n
Thus the value of VOL depends on the ratio . With the increase in the
p
device ratio, VOL will decrease.
General pseudo-nMOS logic gates are designed using the same nFET
arrays as in standard CMOS. NOR2 and NAND2 is shown in fig.37
respectively. The NOR2 gate is based on the same -values since the worst-
case pull-down situation is when only a single nFET is active. The same
argument holds for n-input NOR gate. The NAND2 gate in Fig.37 (b) is
complicated by the series nFETs.
VDD
a b
0 0
2
To obtain the same pull-down characteristics of the inverter, the logic
FETs must be increased t 2n to provide the same total nFET resistance from
the output to ground. This is a general problem with pseudo-nMOS gates that
require series logic FETs. A basic AOI circuit is shown in Fig.37 (c)
VDD
VDD
0 out
0
a c
a
b b d
0 0 0
Boolean Expressions:
a+b a . b
a.b + c.d
3
VDD
Enb
En
En
1 2
Data
Data f
0
Fig.38 (a) Symbol of Tri-state inverter Fig.38 (b) CMOS circuit of
Tri-state inverter
9.4 Clocked CMOS(C2MOS)
1
f
T
_
Fig 39 wave form of clock (t) and its complement t
4
If (t) is defined to have a minimum value of 0 V and a amximum of VDD,
_
then t VDD (t ), so that the clocks overlap slightly deuring a
transition. It may be advantageous to create a set of clocks that are truly non-
overlapping for all times.
The general structure of aC2MOS gate is shown in fig.40. It is
composed of a static logic circuit with tri-state output network made up of
_
FETs M1 and M2 that is controlled by and . When = 1, both M1 and
M2 are active. Since both the pFET and nFET logic blocks are connected to
the output node, the circuit degenerates to a standard static logic gate. The
output f(a,b,c) is valid during this time, establishing the voltage V out on the
output capacitance Cout. When the clock changes to a value = 0, both M1
and M2 are in cutoff, so that the output is in high-impedance statte Hi-Z.
During this interval, the FET logic arrays are not connected to the output, so
the inputs have no effect. Instead, the output voltage is held on Cout until the
clock returns to a value = 1.
Fig.40 Structure of C2MOS gate
VDD VDD
a
b
c pFETs
d a
M1 b
f(a,b,c)
0 Cout
M2
M1
a
b
c nFETs 0
Cout
d M2
0
b
VDD
b
a 0 0
0 Cout
M2
5
The transistor arrays are designed using the same technique as for
standard logic gates. The circuits of a NAND2 and NOR2 are shown fig.41
and fig.42 respectively. The presence of the series-connected clocking FETs
automatically lengthens both the rise and fall times of the circuit.
Advantages:
1. The Clock controls the entire operation of the logic gate.
2. New group of data bits enter the network during every clock cycle.
Disadvantages:
1. Output node cannot hold the charge on Vout for a very long time due to
phenomenon called charge leakage.
2. Lower limit on the clock frequency will be laid by the phenomenon of
charge leakage. This makes the operation of the logic to be done at lower
frequency range only.
6
A dynamic NAND3 circuit is shown in fig.43. Logic formulation is
achieved using the three series-connected FETs. The output F= a.b.c is
VDD
a
nFETs
b
c
phi
VDD
VDD
phi
0
0
valid only during the evaluation period when = 1. Since the evaluation
nFET is in series with the logic block, Cout must discharge through four
transistors. Increasing the sizes of the nFETs will reduce the fall time. Charge
leakage reduces the voltages held on the output node when f = 1. Another
problem called CHARGE SHARING can occur when the clock makes a
transition to 1. It has the effect of reducing the output voltage even
before charge leakage effects become noticeable.
The origin of the charge sharing problem is the parasitic node
capacitance C1 and C2 between FETs as shown in Fig.44. The clock has
been set at = 1 so that Mp is off, isolating the output node from the power
supply. The initial voltage on Cout at the start of the evaluation interval is
Vout = VDD as shown. Assuming that the capacitor voltages V1 and V2 are
both 0 V at this time, the total charge on the circuit is
Q = Cout VDD.
7
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
The worst case charge sharing condition for this circuit is when the
inputs are (a,b,c) = (1,1,0). With c = 0, there is no discharge path to ground,
so that the output voltage should remain high. However, since the a- and b-
input FETs are on, Cout is electrically connected to C1 and C2 as indicated by
the darkened lines. The current I flows because Vout is initially larger than
V1 or V2. This corresponds to the transfer of charge from Cout to both C1 an
dC2. Using the relationship Q = CV shows that Vout decreases while V1 and
V2 increase. The current flow ceases when the voltages are equal with a final
value Vout = V1 = V2 = Vf. The total charge on the circuit is then distributed
according to
Q = Cout Vf + C1 Vf + C2 Vf = (Cout + C1 + C2) Vf
Applying the principle of conservation of chrge, this must be equal to
the initial charge in the system:
Q = (Cout + C1 + C2) Vf = Cout VDD
Solving for the final voltages gives
C out
V f V DD
C out C1 C 2
C out
Since 1
C out C1 C 2
8
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
VDD
Mp
a
a
Cx
0
+
Vx
Vout
VDD
b
c nFETs
0
M1
Mn 1 2
Phi
0 a a . b
Fig.45 Example for Domino M2
Phi
0
VDD
1 2
a + b
a b
Phi
0
Fig.47 OR gate
9
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
1 2 1 2 1 2
C1 C2 C3
0
f1 0
V2 f2 0
f3
V1 V3
Phi
0 0 0
10
This is because C2 has discharged and since f1 =1 has turned on the
nFET in the discharge chain. Applying the same logic t the first stage, f1 can
switch to 1 only if C1 has discharged. extending this argument, we see that f3
= 1 occurs only if both stage 1 and stage 2 have made the same transitionThe
domino effect is portrayed in fig.49 and it helps to visualize the process.
Fig.49 (a) represents the precharge event by domino standing on end.
Evaluation for the chain is shown in fig.49 (b). A discharge event that gives
an output of f tending to 1 is indicated by a falling domino. This can topple
the next stage, but other inputs may keep the discharge from taking place. In
the drawing, stages 1 and 2 have undergone a discharge, but stage 3 remain
high (in its precharge state). Note that the operation indicates that domino
logic gates are only useful in cascades.
The domino cascade must have an evaluation interval that is long
enough to allow every stage time to discharge. This means that charge
sharing and charge leakage processes that reduce the interval voltage Vx
combat this problem as shown in fig.50. In fig.50 (a), a pFET MK is biased
active to allow a small current to replenish charge on Cx. The aspect ratio of
the charge-keeper FET must be small so that it does not interfere with a
discharge event in any significant manner; this is called a weak device.
Another approach is shown in fig.50 (b). Here, an inverter controls the gate
of the weak pFET. If an internal discharge of Cx does occur, then the output
voltage Vout increases. Feeding this through the inverter shuts the pFET off
and allows the discharge to continue.
Multiple output domino logic (MODL): This allows two or more outputs
from a single logic gate, making it quite unique. The structure of a 2-output
MODL stage is shown in fig.51. The logic array has been split into two
separate blocks denoted as F and G, which creates an additional output node.
Adding an inverter and a precharge transistor results in the two outputs
f1 = G and f2 = F. G
VDD
Mp
MK
0
1 2
Cx + Vout
Vx
a 0
b
c nFETs
Mn
Phi
0
(a) Single-FET charge keeper
11
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
VDD
Mp
2 1
MK
1 2
Cx + Vout
Vx
a 0
b
c nFETs
Mn
Phi
0
(b) Feedback controlled charge keeper
Fig.50 Charge keeper circuits
If the G-logic block acts like a closed switch, then it produces an output of f1
= G. If this occurs, then it is possible for the second logic block F to induce a
discharge by also acting as a closed switch. This dependence produces the
ANDing relation between the two outputs. While this is quite restrictive, the
nesting of the AND operation does appear in several important computational
algorithms such as the carry look-ahead adder.
12
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
So that the rate of change of fx is approximately twice that of a single input.
Translated into logic terms, this means that the switching speed is almost
twice as fast as can be obtained in a single-rail circuit.
Disadvantage:
1) Increase of circuit complexity and wiring overhead.
2) As every input and output is now a doublet consisting of the input and
its complement, Circuits are more complicated.
13
VDD
a.b (a.b)bar
a
abar bbar
0
b
0 0
F
Fig.51 The Basic structure of CVSL logic gate Fig.52 Illustration of
CVSL gate by AND/NAND
x y P Q
VDD
b b
x y bbar bbar
abar a
abar a
(a+b)bar a+b
x.abar + y.a
(a) Simple nFET pair (b) Stacked Pairs
abar f = 0
(XNOR) f = 1
a (XOR)
b bbar
b b
0 bbar
bbar F 1 0 0 1
b 0 1 0 1 abar a
a 0 0 1 1
0 0 a 0 0 0 0
0
14
Fig.53 Illustration of CVSL gate by OR/NOR
Fig.54 (C) Example of a logic tree using nFET pairs
Fbar
'0'
F
'1' - + + c F 0 0 1 1 0 1 1 0
c 0 1 0 1 0 1 0 1
-+ - + b
b 0 0 1 1 0 0 1 1
a 0 0 0 0 1 1 1 1
- +
a
Phi
0
Fig.55 Dynamic CVSL circuit with 3-level logic tree
A Dynamic CVSL circuit is shown in fig. 55. This replaces the static
latch with clocked-controlled pFETs that are used to precharge the output
nodes. An nFET is used at the bottom of the tree for the evaluation.
Simplified notation has been used in the schematic. Each - +box
corresponds to an nFET pair with the variable applied to the + side, and the
complement to the -side. Two reductions have been made translating the
function table to the logic tree. This is because the left entries for f have the
sequence 00 11, which allows both c-level pairs to be eliminated.
15
9.6.2 Complimentary Pass Transistor Logic (CPL)
It is an interesting dual-rail technique that is
based on nFET logic Equations. Let us examine the nFET pair in Fig.56. The
output is given by
f a.b a. a
b a
a abar
a.b + abar b
b a abar bbar
a
0 0
abar
0 0
2 1 1 2
(a.b)bar a.b
(a.b)bar
a.b
Fig.56 AND gate Fig.57 AND/NAND array
Logically, this reduces to the AND operation f = a.b since a .a 0. The right
transistor is added to insure that the output f = 0 when a =0 is a well defined
hardware voltage (from the input a). This is the basis of pas transistor logic.
To create CPL, we must add the NAND function. This is done in the
AND/NAND pair shown in fig.57. The nAND operation is obtained from the
simplification
a. b a a b a.b
since nFETs suffer from threshold losses, static output inverters have been
added to restore the voltages to full-rtail values. These are not necessary until
the full power supply is required, but they also help to speed up the circuit.
A unique feature of CPL, is htat several 2-input gates can be created
by using the same transistor topology with different input sequences. Fig.58
shows an OR/NOR array. Comparing this with the AND/NAND shows that
b a abar bbar
bbar b bbar b
abar
a
0 0
0 0
a abar
0 0
0 0
16
we have simply switched a and a on the FET inputs. An xor/xnor pair is
shown in fig.59. This is achieved by changing the top(drain) inputs. CPL also
allows for 3-input logic gates with similar properties.
CPL is an interesting approach because it provides compact logic
gates and the cell layout is reusable. The main drawbacks are the threshold
loss and the fact that an input variable may have to drive more than one FET
terminal.
17