1

Li gii thiu
Khai thc, nghin cu c bn cng ngh mi l bc khng th thiu trong
vic ci tin, nng cao, cng nh ch to mi cc trang thit b qun s v dn s
nhm p ng vic hin i ho cng nghip ho ca t nc. Cng vi s pht
trin vt bc ca nghnh cng ngh thng tin, cc cng ngh mi v cc mch tch
hp vi in t, cc mch t hp logic lp trnh c ra i lm cho cc sn phm
qun s cng nh dn s ngy cng hon thin v u vit hn. tin mt bc xa
hn trong vic ci tin, ch to kh ti qun s nhm p ng chin tranh in t
hin i vi tc x l cc k cao, i hi phi c cng ngh tin tin ph hp vi
tnh hnh chung ca th gii.
Trn c s pht trin t cc chp PLA, hin nay cng ngh na n c a
vo ch to cc mch tch hp lp trnh c FPGA v CPLD, n lm cho
mch tch hp logic ln n hng chc triu cng, tc ng h ln n 500 MHz.
ng dng cng ngh mi vo trong thit k ch to cc thit b in t lp trnh
PLIC l mt bc cn thit cho tng lai vi mt nc ang pht trin nh Vit
Nam. p ng c tnh bo mt trong qun s cng nh tnh phn ng nhanh
trong chin tranh hin i cng vi nhu cu chuyn dng ho, ti u ho (thi gian,
khng gian, gi thnh ), tnh ch ng trong cng vic... ngy cng i hi kht
khe. Vic a ra cng ngh mi trong lnh vc ch to mch in t p ng
nhng yu cu trn l hon ton cp thit mang tnh thc t cao. Cng ngh FPGA
(Field Programmable Gate Array) v CPLD (Complex Programmable Logic
Device) c cc hng ln tp trung nghin cu v ch to, in hnh l Xilinx v
Altera. lm ch cng ngh mi v t chc thit k sn xut cng ngh FPGA
ca Xilinx cho php chng ta t thit k nhng vi mch ring, nhng b x l s
ring dnh cho ng dng ca chng ta. c bit trong lnh vc x l tn hiu s, cc
mch tch hp dng nhn dng m thanh, hnh nh, cm bin ... vi tnh mm do
cao v gi thnh thp.
Mc d cng ngh FPGA xut hin t nm 1985, xong i vi nc ta th
n vn cn rt mi. Do vy tm hiu, lm ch v cng ngh FPGA l vic lm hon
ton cn thit. N khng ch c ngha i vi cc lnh vc in t - Vin thng,
 2

cng ngh thng tin... m n c ngha c bit quan trng trong lnh vc an ninh
quc phng.
Xut pht t thc t i hi cp bch , b mn T ng v K thut tnh
Khoa K thut iu khin Hc Vin K thut qun s cho xut bn cun sch
Thit k thit b in t lp trnh s dng cng ngh FPGA v CPLD, ti liu ny
nm trong lot cc ti liu c b mn n hnh, bao gm Cu trc my tnh,
Cu trc v lp trnh cho cc h x l tn hiu s, cu trc v lp trnh h vi iu
khin.
Ti kiu gii thiu phng php thit k CPLD, FPGA cng nh ngn ng lp
trnh, t i su nghin cu cc gii php c lin quan cng nh cc cng c h
tr thit k, sau p dng thit k, tch hp vo loi CPLD v FPGA c th . Ti
liu c chia thnh 4 chng:
- Chng 1: Gii thiu tng quan t chc phn cng ca ASIC. Gii thiu
tng quan t chc cc h thit b cng nh cu trc ca chng (ti liu gii thiu cu
trc ASIC ca hng Xilinx).
- Chng 2: Gii php v t chc phn mm m bo. Gii thiu cc phn
mm h tr thit k, ngn ng lp trnh.
- Chng 3: Ngn ng lp trnh VHDL
- Chng 4: Thit k ng dng c bn. Chng ny c thc hin vi vic
tch hp cc mch in t trn c s s dng ngn ng VHDL, thit k b iu
khin ng c bc trn hai h thit b CPLD v FPGA.
Cun sch c dng lm gio trnh ging dy bc i hc v sau i hc
chuyn ngnh in, in t hoc lm ti liu tham kho cho cc nghin cu sinh v
cho nhng ai quan tm n cu trc v lp trnh ASIC.
Cun sch c bin son bi PGS. TS. Nguyn Tng Cng v TS. Phan
Quc Thng, ThS. Phm Tun Hi, KS L Trng Ngha, do PGS. TS. Nguyn Tng
Cng ch bin.
Nhn dp ny, tp th tc gi xin by t li cm n chn thnh nht n nhng
ngi c nhiu ng gp trong qu trnh hon thnh ti liu, n cc anh ch em
B mn T ng v K thut tnh thuc Khoa K thut iu khin, Hc vin K
thut Qun s, c bit phi k n s h tr hiu qu ca TS. nh Ngha.
Do kinh nghim v thi gian hn ch, ti liu ny chc chn khng th trnh
 3

khi nhng thiu st. Rt mong nhn c cc kin ng gp v xy dng ca bn

c gn xa. kin ng gp xin gi v a ch: B mn T ng v K thut tnh,
Khoa K thut iu khin, Hc vin K thut Qun s, 100 Hong Quc Vit, H
ni; in thoi (04)7542281, email: tcuong@hn.vnn.vn.
H Ni, Ngy 1 thng 10 nm 2005
Tp th tc gi
 4

Chng 1 : Gii thiu tng quan

t chc phn cng ca FPGA v CPLD
1.1 Gii thiu cng ngh v gii php ca Xilinx
Vo cui nhng nm 70, cc bng mch c thit k sn cng vi cc thit b
chun logic c a chung v thnh hnh . Sau mt s cu hi c a ra rng
" iu g s xy ra nu chng ta a cho nhng ngi thit k kh nng thc hin
kt ni gia cc thit b chun logic khc nhau trong mt thit b ln hn ? ". iu
ny cho php nhng ngi thit k tch hp c nhiu thit b chun logic hn vo
trong mt thit b. c c s linh hot trong thit k, Ron Cline ngi ca hng
SigneticsTM a ra tng bao gm hai s cho php ngi thit k c th lp
trnh c.
Hai s ny cung cp bt k t hp logic no ca cc cng "AND" v "OR"
m chng c th c dng chung vi mt s gii hn cng "AND " thng qua cc
cng "OR". Cu trc ny tr nn rt mm do, nhng ti thi im lp m
hnh hc 10 m to ra s gi chm gia u vo v u ra rt ln, chnh iu ny
lm cho thit b hot ng tng i chm. V cu trc ny c gi l cu trc
ca PLA (Programmable Logic Array).

Hnh 1.1. Cu trc ca PLA (Programmable Logic Array)

Hng MMI (Sau b mua bi hng AMD TM) hp tc vi hng SigneticsTM
v l ni cung cp ngun ti liu th hai cho h thng mng logic lp trnh PLA
(Programmable Logic Array). Nhng sau khi sn xut, cu trc ny b thay i
v tr thnh cu trc logic mng lp trnh c PAL (Programmable Array Logic),
 5

bi vic c nh mt mng v ch cho php lp trnh trn mt mng cn li. Cu trc

PAL mi ny rt khc vi cu trc ca PLA ch l mt mng lp trnh c b
gn c nh - mng cc cng OR . Tuy nhin, cu trc PAL (Programmable Array
Logic) ny cng c li l thi gian gi chm ng truyn t u vo n u ra
ngn hn v phn mm t phc tp hn. Tuy nhin chng khng mm do bng cu
trc PLA (Programmable Logic Array) . Cc cu trc khc cng c a ra, chng
hn nh PLD (Programmable Logic Device) - thit b logic lp trnh c. Loi thit
b ny thng c gi l thit b logic lp trnh c n gin SPLD ( Simple
Programmable Logic Device) v tn ny c gi chung cho tt c cc thit b logic
lp trnh c nh : PALs, CPLDs, FPGAs. Cu trc ca PAL (Programmable Array
Logic) .

Hnh 1.2. Cu trc ca PAL (Programmable Array Logic)

Cu trc ny c cc mt li ca cc ng ni theo chiu ngang v chiu
ng. Ti mi im giao nhau, chng c ni vi nhau bng mt cu tr. Vi s tr
gip ca cc cng c phn mm, ngi thit k c th la chn mi ni, mi no
khng c ni th cu tr ti im s b hu i (B nung nng v thi t). iu
ny c thc hin bi mt b np chng trnh.
Theo hnh 1.2 cc chn u vo c ni vo cc ng theo chiu ng, cc
ng nm ngang c ni vi cc cng AND - OR, ln lt cc ng ny c
ni vi cc Flip-Flop chuyn dng (Chng hn nh Flip-Flop loi D, T, RS). Cc
PLDs (Programmable Logic Device) trong mt IC ng gi n c s cng nhiu
hn 50 ln cc thit b logic chuyn bit. iu ny n th hin mt s tin b r
rt, y l cha cp n mt s thit b cn phi c gin lc ho c tin
 6

cy cao hn cc thit b chun logic .

Cng ngh PLD pht trin t nhng ngy cn rt sm, chng hn nh cng
ty Xilinx, h a ra sn phm CMOS vi ngun tiu th siu thp da trn cng
ngh b nh flash. Cc PLD flash cho php kh nng lp trnh v xo bng in cho
thit b nhiu ln tr nn thch hp hn so vi cc chp th h c, cc loi chip m
vi thi gian xo chng trnh hn 20 pht bng tia cc tm .
1.1.1. Complex Programmable Logic Devices (CPLDs)
Tm dch l cc thit b logic cho php lp trnh phc hp, h thit b ny l
kt qu ca vic tng mt ca h SPLDs (Programmable Logic Device) ln nhiu
ln. Khi nim ny c hiu nh sau : tng mt s khi PLD hoc cc macrocell
(xin c nguyn ngha v gii thch phn cu trc ca CPLD) trong mt
thit b n cng vi cc ng ni lin a nng gia chng. Cc ng ni ca cc
n v logic n c th c thc thi trong mt khi n ( a single block ). Nhiu
logic phc tp yu cu cn nhiu khi v s dng cc ng ni a nng gia chng
to nn cc kt ni phc tp hn.

Hnh 1.3. Cu trc ca CPLD

Cc CPLDs rt thch hp trong vic din t cc cng logic phc tp vi tc
lm vic ln hn 200 Mhz ( tng ng 5 ns ). Khun mu thi gian cho CPLD rt
d tnh ton, bi th trc khi bt u thit k bn c th tnh ton cc tc t u
vo n u ra ca mnh da trn khun mu ny. CPLDs a ra cch n gin nht
thc hin mt thit k, mt thit k c th c m t bi cc s nguyn l
 7

hoc nhp vo mt HDL ( Hardware Description Language - Ngn ng m t phn

cng). n gin khi s dng cc cng c pht trin ti u ho, np v m phng
thit k. Cc cng c thit k s to ra mt file m file ny (chnh l mt file chng
trnh) c dng a thm cc chun logic vo trong mt chip CPLD cng vi
chc nng mong mun. Chnh v vy n cung cp mt chun phn cng m cho
php cc qu trnh x l, g ri c th thc hin ngay t khi bt u cng vic thit
k. Gi s nu bn cn c mt mt s thay i v thit k, bn c th a s thay
i thit k vo trong cng c pht trin CPLD v thc thi trn n, sau bn c
th kim tra c tc th ngay sau bng mt phn mm m phng. CPLD c mc
tch hp rt cao (c ngha l mt s lng ln cc cng trn mt din tch) v c
ng gi trong mt khun dng rt nh. iu ny a ra mt gii php tuyt vi
cho nhng ngi thit k cn sn phm ca mnh c ng gi nh gn vi din
tch bo mch b gii hn v khng gian. H Xilinx CoolRunner CPLDs lun c mt
trong cc ng gi cng vi cc chip i mi. Chng hn nh chip CP56 CPLD c
khong cch cc chn l 0,5 mm v vi kch thc bao nh khng ng k 6x6mm
v iu ny cho php a ra mt sn phm nh gn cng vi mc tiu th ngun
thp .
1.1.2. Field Programmable Gate Arrays ( FPGAs)
Mng cng cho php lp trnh c. Nm 1985, cng ty Xilinx a ra mt
tng mi : l s kt hp gia nhng iu khin ngi dng, thi gian a sn
phm PLD (Programmable Logic Device) ra th trng cng vi mt tch hp,
gi ca cc ma trn cng. iu ny cho ra i thit b FPGA v cho n nay
Xilinx vn l nh phn phi s 1 trn ton th gii v h thit b ny. Mt FPGA c
cu trc ca cc Logic Cell hoc cc Module v cc ng ni (Xem hnh 1.4), cc
ng ni ny nm di s iu khin ca ngi thit k. C ngha l bn c th
thit k, lp trnh v thay i mch ca bn bt c khi no bn mun . Vi h FPGA
ngy nay kh nng tch hp ca n vt qua gii hn 10 triu cng ( H Xilinx
VirtexTM- II v VirtexTM- 4 FPGA hin ang gi k lc).Vi s gii thiu ca h sn
phm Spartan FPGA hin nay, Xilinx c th cnh tranh v ma trn cng mi kha
cnh nh gi c, s lng cng, s lng vo ra cng nh hiu qu v gi thnh. Gi
 8

s ly Spartan - IIE FPGA vi s lng 300.000 cng lm chun ca gi thnh, n

c th cho php thay th cc sn phm ng dng theo chun chuyn dng.
C hai loi FPGA c bn : Loi SRAM (Static Random Access Memory) c
th lp trnh li nhiu ln v loi OTP (One - Time Programmable) lp trnh mt ln.

Hnh 1.4. Cu trc ca FPGA

Hai loi ny khc nhau ch thc hin ca cc logic cell v k thut to s
kt ni gia chng trong thit b. Loi hay c dng hn c l loi SRAM, v n c
th lp trnh c nhiu ln. Thc t th SRAM FPGA c np cu hnh li mi khi
bt ngun, bi v FPGA loi ny thc cht l mt chp nh theo mun. C mt cu
hi t ra l " Ti sao li cn mt chip PROM ni tip hoc b nh h thng? "
cng vi mi SRAM FPGA . Xem cu trc ca hai loi vi hnh v 1.5 v 1.6:

Hnh 1.5. Cu trc SRAM FPGA ( SRAM Logic Cell)

 9

- Loi SRAM c th lp trnh li :

+ SRAM xc nh cc ng kt ni.
+ SRAM xc nh n v logic trong bng LUT ( Look Up Table )
( Mi mt LUT l mt b to chc nng hay b to hm vi N u vo v mt
u ra, c th thc hin bt c chc nng logic no vi N u vo ca n. N thng
nm gia 2 v 6, thng thng cc LUT c 4 u vo ).

Hnh 1.6 . Cu trc ca OTP FPGA (OTP Logic Cell)

- Loi OTP cho php lp trnh mt ln :
+ Cc ng ni khng c php ni nh dng cu ch ( Ni c nh ).
+ Logic l cc cng truyn thng .
Trong SRAM Logic Cell, thay v cc cng thng thng, mt LUT ( b to
hm ) s xc nh cc u ra da vo gi tr cu cc u vo. Nh hnh 1.5 ta thy
su t hp khc nhau ca bn bt vo xc nh cc gi tr ca u ra, cc bit ny
cng c dng thc thi cc kt ni. Trong OTP FPGAs s dng kt ni gia
cc ng theo dng ni ngc ( C ngha ngc vi cu tr, s kt ni c to ra
v khng b nng chy trong sut thi gian np chng trnh), nhm to ra cc kt
ni c nh trong chip. Hn na, OTP FPGA khng cn SPROM no khc, iu
c ngha l np cu hnh vo thng FPGA. Tuy nhin mi ln thay i mt thit k
bn phi vt b i mt chip. Loi OTP Logic Cell c cu trc tng t nh h PLD
(Programmable Logic Device), bao gm cc cng v flip - flop chuyn dng nh
Flip-Flop loi D , T , hay RS .
 10

1.2. Gii thiu cc h thit b ca Xilinx

Xilinx chia sn phm ca mnh ra rt nhiu h nhng ti liu s tp trung
chnh vo vic gii thiu hai loi FPGA v CPLD c bn, xem hnh v (Hnh2.1).
l lai thit b CoolRunner - XPLA3 CPLD, v Spartan 3 FPGA.

Hnh1.7. S lc cc h thit b ca Xilinx

1.2.1. H Platform FPGAs
Hnh 1.7 cho ta thy c tng quan cc h sn phm chnh cu Xilinx. y
xin ch gii thiu tng quan v a ra cc a ch cn tra cu v chi tit k thut ca
chng trn trang Web ca hng Xilinx.
H Virtex FPGAs : Sn phm Virtex-II l hin thn u tin ca Platform
FPGA. N to ra mt im du mi trong s thc thi, cng thm hng lot cc
tnh nng mi ca thit b m t trc cha c. y l thi k m Xilinx m rng
tm chin lc ca mnh bng vic kt hp vi cc hng IBM, Wind River,
Conexant, RocketChipsTM, The MathWorks, v cc nh ng u cng ngh khc
 11

trn th gii. Platform FPGA a ra cc c tnh sau :

- Cc giao tip vo ra h thng lm gim nh bt cc tiu chun khng cn
thit khc.
- XtremeDSPTM da trn FPGA, gii php cho s thc hin DSP cha tng c
(Nhanh gp 100 ln b x l DSP hng u).
- Empower ! K thut x l dnh cho x l h thng i hi s thc hin cao
v mm do.
Vi di mt t 40.000 n 10 triu cng h thng , Virtex-II a ra b nh
h thng c m rng v b DSP flash thng qua kt cu nhng IP (Li s hu tr
tu). H Xilinx Virtex l h u tin ca FPGA m n a ra mt triu cng h
thng v c gii thiu vo nm 1998. Dng sn phm Virtex v c bn c
nh ngha li tt c cc n v logic lp trnh bi vic m rng cc kh nng ca
FPGA truyn thng c c tnh mnh hn, n c dng cho cc thit k h
thng thc thi cao. Cc thit b mi nht c a ra vi h sn phm Virtex-E v
c cng b nm 1999 vi hn ba triu cng h thng. Virtex-EM gii thiu nm
2000 v l h FPGA u tin c sn xut vi qui trnh m ng c ci tin
v thm vo b nh trong chip dng trong cc ng dng chuyn mch mng.
H Spartan FPGAs :
H Spartan FPGA l tng dng cho cc ng dng vi s lng ln, gi
thnh thp, chng c a vo cc thit b ch nhm thay th cc chip logic c
nh v cc sn phm chuyn dng, chng hn nh cc chip giao tip bus. Nm
thnh vin ca h ny l Spartan-3 (1.2v), Spartan-IIE (1.8 v), Spartan-II (2.5 v) v
SpartanXL (3.3v), Spartan(5v). ti liu ny xin gii thiu h sn phm Spartan-3.
- Spartan-3 FPGAs (1.2v, 90nm) : Vi h ny, n khng ch c gi thnh thp
m cn oc tch hp vi mt s tnh cht mi v cu trc, cc tnh cht ny c
kt hp vi cc n v logic cho php lp trnh. S kt hp gia gi thnh thp vi
cc tnh cht mi to ra s thay th cc chip ASIC v cc thit b chuyn dng
khc. V d mt chip Spartan-3 FPGA trong h thng a phng tin truyn thng
trong xe hi c th tp hp c rt nhiu chc nng ca h thng, bao gm cc li
IP nhng, giao tip h thng khch hng, DSP v cc n v logic khc. N bao gm
 12

cc thnh phn chnh sau:

+/ Cc khi SRL16 ( thanhghi dch 16 bit) :
* Mi khi Logic nh cu hnh c (CLB LUT- Configurable Logic Block LookUp
Table) lm vic nh mt thanh ghi dch nhanh 16 bit. (Mi CLB c cha 2 hoc 4
LUT v 2 hoc 4 Flip Flop ).
* Ni tng cc LUT ( B to chc nng ) to nn thanh ghi dch di hn .
* S dng cc thanh ghi ng ng cho cc b m dnh cho Video v cc kt ni
khng dy.
+/ B nh RAM chn c th c cp ti 520Kb
* Mi LUT lm vic nh b RAM/ROM n cng hoc lng cng.
* Ni tng cc LUT to b nh ln hn .
* Cc ng dng c th thay i kch thc b nh mt cch mm do, FIFO, v cc
b m.
+/ Khi RAM nhng ti 1.87Mb
* Nhng ti 104 khi RAM ng b bng vic ni tng cc khi RAM 18Kb.
* Mi khi RAM 18Kb coi nh mt RAM n cng hoc lng cng .
* Cung cp cc bi s ca t s tng quan, chuyn i rng d liu, tnh chn
l.
* Cung cp cho cc ng dng gm: b m d liu, FIFO, v cc b m khc.
+/ Giao tip b nh
* Cho php giao tip in vi cc chun nh HSTL, SSTL, cho php thc hin kt
ni vi b nh thng thng.
+/ Cc b nhn
* Cho php cc php tnh ton hc v s hc n gin cng nh cc chc nng nng
cao ca DSP.
* Cung cp 104 b nhn 18x18 vi cc php nhn18 bit du hoc 17 bit khng du,
cho php ni tng tng rng s bit.
* Cc b nhn h s hng : B nh on - Chip v cc Logic Cell lm vic cht ch vi
nhau xy dng cc b nhn vi cc ton hng l hng s.
* B nhn Logic cell : Thc hin thut ton thng thng chng hn nh Baugh
 13

Wooly, Booth, cy Wallance ...

* Cc b DCM (Digital Clock Manager - B qun l ng h s) thc hin vic
qun l ng h s phc tp m khng b nh hng ca cc tc nhn kch thch
mang tnh h thng nh, nhit , s bin thin in p, v cc vn khc m v d
in hnh l thng xy ra vi cc b PLL (Phase Lock Loop - cc vng kho pha)
c tch hp trong FPGA.
* B to tn s mm do t 25 MHz n 325 MHz.
* iu khin dch pha cc gc 1/4.
*To cc chu k chnh xc 50/50.
* B nhit.
+/ K thut tr khng iu khin c XCITE
(Xilinx Controlled Impedance Technology)
*Cc u cui I/O cn bo ton tnh nguyn dng cu tn hiu, vi hng trm u
I/O v vi cc k thut ng gi ci tin, cc in tr u cui m rng khng cn
b bin i.
* Cc u cui I/O b loi tr s thay i theo qu trnh nh nhit , dao ng ca
in p .
Bng 1.1. Tng quan h Spartan-3 FPGA
 14

Cc c tnh v cng dng ca chng c nu trong bng 1.2 :

Bng 1.2. Cc c tnh chnh ca Spartan-3
Cc c tnh ca Spartan -3 Cng dng
Kt cu v nh tuyn FPGA ln ti - Cho php thc hin cc khi chc nng
5.000.000 cng h thng. mc h thng, kt ni on - chip cao, a
vo cc cu hnh h thng cao .
Khi RAM - c cc Block 18K - Cho php thc hin cc b m ln,
cc FIFO, cc b m kt ni.
Ch thanh ghi dch ( SRL 16 ) - tng thanh ghi dch 16 bit dnh
cho cc ng dng tc cao, hoc d
liu c dng th c lu tr trong DSP
v cc ng dng m ho, x l ng
ng nhanh .
Cc khi nhn 18x18 . - Dng cho vic x l DSP tc cao;
S s dng cc b nhn kt hp vi kt
cu khung d liu cho php thc hin
DSP song song siu nhanh.
Tn hiu u cui (ln ti 622 Mbps) - Cho php kt ni cc chp ang dng
nh dng theo cc chun LVTTL, vi cc chip, b nh khc, v t cc chip
LVCMOS, GTL, GTL+, PCI, HSTL-I, II, ang dng ti cc chun tn hiu mch
III, SSTL- I, II . phn hi, loi bt s cn nhiu IC
chuyn i .
B qun l ng h s ( DCM ) - Loi tr s gi chm ng h mc
board v on-chip, nhn chia tc th, c
th gim c tc ng h ph hp
mc board, gim s b ng h trn bo
mch. C th iu chnh pha ng h
m bo chnh xc cao .
C cc ti nguyn c nh tuyn ton - S phn phi cc clock v cc tn hiu
cc. khc cng vi cc h s phn chia u ra
 15

cao trn ton thit b.

iu khin u ra cho php lp trnh . - Nng cao tnh ton vn ca thit b

1.2.2. H Xilinx CPLDs

Hin nay Xilinx a ra cc sn phm CPLD hai loi thit b : XC9500 v
CoolRunner. chn CPLD ph hp, bn cn xem qua cc c tnh cu n nhn
dng h sn phm m n ph hp vi ng dng ca bn.
- Vi h XC9500 : l h cc thit b cho php lp trnh phc tp vi s thc thi
cao, cc c tnh mi, linh hot. H thit b ny a ra tc dn u trong nn
cng nghip, n cung cp s linh hot trong cu trc kho chn vi ngi dng. H
sn phm ny c dng cho cc thit k cn tc cao, gi thnh thp.
- H CoolRunner : H thit b tiu th ngun cc k thp, to ra s dn u
trong th trng cc thit b xch tay. Hot ng trong ch ch mc Micro
ampe, tiu th ngun nh nht khi lm vic, v vy n ph hp vi cc ng dng m
cn quan tm ngun, chng hn nh ngun c qui, cc ng dng xch tay. quyt
nh chn lai thit b no ph hp vi tiu chun thit k, cn phi xem thm cc
thng tin chi tit v loi thit b m bn cn, chng hn nh : Mt cng, s thanh
ghi, s chn vo ra, tc yu cu, ng gi chn, tiu th ngun, chc nng mc
h thng...
H XC9500 ISP ( H ny cho php lp trnh mc h thng )
H XC9500 vi s thc thi cao, gi thnh thp l mc tiu cho cc ng dng
c nhu cu pht trin, nng cp thit k. H XC9500 c di mt t 36 n 288
Macrocell (Xin gii thch phn cu trc CPLD v FPGA mc 1.3 chng I), lm
 16

vic in p 2.5 Volt (XC9500 XV), 3.3 Volt (XC9500 XL), 5 Volt (XC9500 ).
Cc thit b ny cho php lp trnh mc h thng ISP, iu ny cho php s
dng li cc thit k trong sut thi gian th mu, g ri h thng, nng cp, test
trc khi xut xng.
Da vo cc k thut x l tin tin, h XC9500 a ra s bo hnh nhanh
(Ch cn file chng trnh c ng gi v np li), cho php kho chn ngi
dng, giao tip c vi chun JTAG. Tt c cc h XC9500 c c tnh tin cy
tuyt vi vi 10.000 ln np xo v lu tr d liu trong vng 20 nm.
- H XC9500 5 V : L mt trong s 6 thit b di t 36 n 288 Macrocell vi
cc kiu ng gi chn a dng. Cc chn vo ra cho php giao tip trc tip vi h
thng 3V v 5 V (VccIO - chn giao tip ngi dng), vi cc phin bn mi n tr
nn rt d s dng vi cc ng gi theo kiu CSP (Chip Scale Package), BGA (Ball
Grid Array) v cho php truy cp n 192 tn hiu.
* Cu trc kho chn linh hot :
Cng vi phn mm fitter a ra kh nng nh tuyn ln nht, mm do
trong thc thi. Vi cu trc c giu c tnh, cho php a ra nhiu tch s nhn
ring bit, c ba b ng h ton cc, c nhiu tch s nhn trn u ra hn cc loi
CPLD khc.
Cc tnh nng v cu trc ca loi ny rt thch nghi vi vic sa i thit k
trong qu trnh thit k.
* Tr gip g ri v pht trin giao tip vi JTAG IEEE 1149.1: Giao tip
JTAG ca h XC9500 thng minh hn bt c h CPLD no c mt trn th trng.
N c cc c tnh chun h tr k thut hi vng, ly mu, kim tra m rng.
Hn na n gm c cc ch dn qut bin m cc loi CPLD khc khng c,
n bao gm INTEST (dng cho kim tra chc nng ca thit b ), HIGHZ ( dng
cho k thut hi vng ).
H XC9500 5V ny a ra nhiu chun cng nghip pht trin th h th ba,
cc cng c g ri nh Corelis , JTAG, Assert Intertech.
Cc cng c ny cho php bn pht trin cc vc t test vng bin phn tch
s nh hng ln nhau, test, g ri li h thng.
 17

Bng 1.3. Tng quan h XC9500 5V

- H XC9500XL 3.3 V: H XC9500 XL c ng dng trong cc h thng mi

nhn cn s pht trin tip theo v kh nng nng cp thit k. H ny a ra s
thc thi cha tng c vi tin cy lp trnh cao nht, gi thnh thp nht. H
XC9500 XL b sung mt cao hn Xilinx FPGA a ra gii php logic tng
th trong mi trng pht trin tch hp . Cc c tnh chnh ca h ny nh sau :
* im mnh chnh :
+/ Gi thnh thp nht trn mi Macrocell.
+/ Cu trc kho chn tin tin nht hin c .
+/ Kh nng lp trnh cao nht, gim s ri ro h thng
+/ B sung cho h Xilinx 3.3 V FPGA.
* S thc thi :
+/ Tc truyn tn hiu gia chn ti chn 5ns .
+/ Tn s h thng 222 MHz .
* Tnh nng cu trc mnh:
+/ C cc khi chc nng ln ti 54 u vo .
+/ C ti 90 tch s nhn trn mi Macrocell.
+/ Cho php nh tuyn nhanh thng qua ma trn chuyn mch
CONNECTTM II.
+/ C ba b ng h ton cc v cho php chuyn i v tr gia chng.
 18

+/ C ng OE (Output Enable) trn mi u ra ring bit, cho php

chuyn i v tr .
* tin cy cao nht
+/ Kh nng chu c 10.000 chu k np xo
+/ Lu d liu c 20 nm
+/ Cho php b qua ch li m kho ISP .

Bng 1.4. Cc h XC9500 XV v XC9500 XL:

H CoolRunner Low - Power CPLD:

C hai thnh vin chnh trong h CoolRunner l CoolRunner XPLA3(3.3v) v
CoolRunner II (1.8V). ti liu ny gii thiu CoolRunner XPLA (3.3 v).
H CoolRunner CPLD l s kt hp ca s tiu th ngun thp v tc cao,
 19

mt cao, s ng vo ra cao trong mt chip n. H CoolRunner 3.3v c mt

t 32 n 512 Macrocell. CoolRunner CPLD c nt c bit ca k thut ngun
khng, cho php thit b khng tiu th ngun ch Standby. c tnh ny rt
ph hp vi cc thit b in t xch tay, nh Laptop PCs, in thoi di ng, cc
thit b c nhn s ... H CPLD ny s dng ngun ng t hn nhiu khi hot ng
so vi CPLD truyn thng. Mt iu quan trng hn c l chng dng cho ng dng
cn s thc thi vi tc cao, nhy cm v nhit, chng hn nh chuyn mch ca
tng i, h thng m phng ....
Mi thnh vin ca h CoolRunner XPLA3 c cha k thut thit k ngun
khng m n l s kt hp ngun nng lng thp v tc cao. Vi k thut thit
k ny h CoolRunner XPLA3 a ra tc truyn t chn ti chn l 5ns. Khi
c cp ngun vi dng nh hn 100 A ( ch standby) khng cn bit
"Powerdown" v bit ny c th nh hng xu n s thc hin ca thit b. Bng
vic thay th cc phng php khuych i truyn thng, phng php cc tch s
nhn vi mt lot s ni tng ca cc cng CMOS thun tu. Ngun ng cng
c thay th bng ngun thp hn bt k loi CPLD no khc. H CoolRunner
hon ton l loi PLD CMOS, v vy chng s dng k thut x l CMOS v k
thut thit k ngun khng CMOS .
Bng 1.5. Cc c tnh ca h CoolRunner:
c tnh Cng dng
Cu trc hon ton CMOS cng vi k - Dng tiu th tng v dng ch
thut thit k ngun khng FZP STANBY thp nht trong s h CPLD, v
vy tui th ca c qui s cao hn, tin
cy tng, to nhit t hn.
C th chn thit b c cha 32 n 512 - Ph hp vi nhiu thit k v cc ng
Macrocell. dng, c th chuyn mt ln hoc
xung tu thuc vo pht trin thit k
ln hay rt bt.
Chun vo ra thay i ( C th dao dng - n gin trong thit k, c nhiu mc
t 3.3 n 5V). in p v d chuyn i mc.
 20

H thng Bus vo ra thun tin. - C in tr treo u cui .

S chn la clock a nng. - Mm do trong thit k .
C cc thanh ghi u vo tc ng nhanh - Giao tip trc tip vi bus tc cao
c.
VFM (Variable Function Mux) b chn - Qu trnh ti u ho mnh hn v d
knh chc nng cho php thay i. iu chnh thit k, chi ph thp hn khi
dng vo cc ng dng nh.
ng gi nh gn vi cc khong cch - Cc chn nh nht, tit kim khong
chn l 0,8 mm v 0,5 mm. mch in, ph hp vi cc thit b cm
tay.
Di nhit chun theo cng nghip v - C th s dng trong cc ng dng
thng mi . cc lnh vc khc nhau, nh y hc...
Bng 1.6. Tng quan h CoolRunner :

Gii thch k hiu CoolRunner CPLD:

 21

1.2.3. H Xilinx ng dng trong hng khng v v tr

Xilinx l nh cung cp hng u cc h PLD vi tin cy cao cho th trng
hng khng v tr v qun s . Cc thit b ny, chng c s dng rng ri trong
cc ng dng nh chin tranh in t, tn la dn ng, tn la hnh trnh, Radar,
truyn thng siu m, x l tn hiu, khoa hc in t hng khng v v tinh. H
QproTM vi cc sn phm QML gm, plastic a ra cc gii php lp trnh logic
nng cao cho cc thit k th h tip theo. H QproTM cng c cc sn phm chn,
chu nhit s dng trong v tinh v cc ng dng khng gian khc. Chng hn
nh h XQ4000E/EX thuc h FPGA, QPro - XC1700D - PROM , XQ17V6 -
PROM, XQ18V04 - Flash PROM c s dng trong lnh vc qun s .
a ch tham kho : ( http://www.dscc.dla.mis/v/va/smd/smdsrch.html ).
1.3. Cu trc ca FPGA v CPLD Xilinx
Vi mi h khc nhau cu trc cu chng khc nhau, tuy nhin chng vn c
nhng im chung, ti liu ny xin gii thiu mt h c th. Vi h ca FPGA tc
gi xin gii thiu cu trc ca Spartan-IIE FPGA, vi h CPLD xin gi thiu h
CoolRunner XPLA3.
1.3.1. Cu trc ca Spartan-IIE ( 1.8V) FPGA
H Spartan-IIE (Li 1.8V) ca FPGA a ra cc k thut FPGA pht trin nht
ngy nay, bao gm cho php lp trnh vi nhiu chun vo ra nh LVDS, LVPECL,
HSTL, cc khi RAM on-chip, cc vng kho gi chm cho php qun l clock
mc board v mc chip. Hn na h Spartan-IIE c mt ngha gi tr khc l
n loi b s cn thit cc sn phm tiu chun chuyn dng ( ASSP ) vi cc ng
 22

dng n gin, chng hn nh vng kho pha, FIFO, cc b chuyn i vo ra, iu

khin Bus h thng, cc thnh phn ny khng th thiu hon thin mt thit
k m n c dng trc y.
- H Spartan-IIE l n by c bn cho cc tnh nng v cu trc ca Virtex-E
a ra nhng tnh nng ni tri hn. Cu trc CLB (Configurable Logic Block -
Khi logic cho php nh cu hnh) c cha RAM c phn phi thc hin cc
chc nng logic c bn.
- Bn DLL ( Delay Locked Loop ) vng kho gi chm c s dng cho
b qun l ng h v c th thc hin clock i xng lch v cc php nhn clock,
chia clock. Clock i xng lch c th c thc hin bn ngoi (Mc board) hoc
bn trong chip ( Mc c bn ).
- Cc khi Block RAM gm 4Kb cho mi khi c th c sp xp rng t
1 n 16 bit.
- c tnh Select I/O cho php giao tip vi nhiu chun khc nhau thc thi
trong cc vng kt ni vi cc chip c chun IO khc nhau, kt ni chip vi b nh,
kt ni chip vi cc giao tip n.

Hnh 1.8. Cu trc ca Spartan - IIE

- H Spartan-IIE FPGA c thc thi vi cu trc CLB cho php lp trnh linh
 23

hot, thng dng, m cc CLB ny c bao bi mt vng cc khi I/O lp trnh

c, cc ng ni c kt ni bi cc ngun ti nguyn nh tuyn a nng. Cu
trc ny cng a ra cc chc nng c nng cao chng hn nh khi RAM v cc
khi iu khin clock.

Hnh 1.9. S khi ca Spartan -IIE

Hnh 1.10. Khi Input/Output Spartan -IIE (I/OB)

I/O Block:
 24

- Cc c tnh I/OB ca cc u vo v u ra c h tr ti 19 cc chun tn

hiu khc nhau, bao gm LVDS, BLVDS, LVPECL, LVCMOS, HSTL, SSTL v
GTL .
- Cc u vo ra tc cao ny c kh nng h tr vi tt c cc b nh hin
i v giao tip bus khc. Chng gm ba thanh ghi chc nng hoc l cc flip - flop
loi D c kch hot bng sn hoc l cc b cht nhy mc Hnh 1.10.
- Mi mt IOB c mt ng CLK c a ti ba thanh ghi theo mt ng
dng chung v cc ng CE cho mi thanh ghi hon ton c lp xem Hnh 1.10.
Ngoi cc ng CLK, CE, mi thanh ghi u c chung mt ng
SET/RESET. Vi mi thanh ghi bn c th t tn hiu Set/Reset ny nh tn hiu
Set ng b, Reset ng b, Preset khng ng b hoc mt tn hiu xo (Clear)
khng ng b.
- Trong mt s cc chun I/O yu cu in p Vcco hoc Vref, cc in p ny
chng c ni ti cc chn ca thit b khi thit k, cc chn ny chng to thnh
tng nhm ca cc khi vo ra v chng c gi l Bank.
- Chnh v vy, s hn ch v cc chun vo ca mt thit b s do cc Bank
quyt nh. Tm Bank vo ra c tch theo mi cnh ca FPGA v c chia thnh
hai Bank chnh (hnh 1.11). Mi Bank c nhiu chn in p Vcco v tt c chng
u c ni ti cng mt ng in p. in p ny c xc nh bi cc chun
u ra ngi dng.

Hnh 1.11. Cc Bank chun vo ra I/O ca Spartan -IIE

- Mt s chun u vo mong mun mt in p ngng no m n c
 25

cung cp bi ngi dng chng hn nh Vref. Trng hp ny, cc chn I/O ngi
dng c xp t t ng nh cc u vo cho in p ly mu Vref. Khong mt
trong 6 cc chn vo ra ca cc Bank ng vai tr ny.
- Cc chn Vref trong mt bank c ni bn trong v v vy ch mt in p
Vref c th c s dng trong mi bank .Tt c cc chn Vref trong cc bank cn
phi c ni vi ngun in p bn ngoi chng hot ng ng.
c s trao i nhanh gia cc tn hiu, cc chn tn hiu u vo cn phi
c cung cp trc khi ngun cp vo chn Vccint v chn Vcco v phi m bo
khng c ng dn dng ngc t cc chn I/O quay v in p ngun cung cp
Vccint v Vcco (C ngha l m bo cho thit b c th hot ng mt in p v
giao tip mt in p, hai in p ny c th khc nhau ).
Configurable Logic Blok v Logic Cell:
- Cc n v c bn ca CLB (Khi logc cho php nh cu hnh) thuc h
thit b Spartan-IIE chnh l cc Logic Cell ( LC - Xem hnh 1.5 v hnh 1.6 mc 1.1
chng I ). Mi mt Logic Cell bao gm mt b to chc nng (Hay b to hm)
gm 4 u vo, phn t logic nh v phn t lu tr (Flip-Flop loi D).
- u ra ca b to chc nng ca mi Logic Cell iu khin c u ra CLB
hoc u vo D ca Flip-Flop.
- Mi mt CLB c cha bn Logic Cell v c t chc thnh hai Slice tng
t nhau, mt slice n c dng nh (hnh 1.12).
- Thm vo bn b LC c bn, cc CLB ca Spartan-IIE c cha phn t logic
m n kt hp vi cc b to chc nng a ra cc chc nng 5 hoc 6 u vo .
Look-Up tables (LUT):
- Cc b to chc nng ca Spartan -IIE thc hin nh LUT c bn u vo.
hot ng nh mt b to chc nng, mi mt LUT c th cung cp mt RAM
16x1bit ng b.
- Hn na hai LUT trong mt Slice c th c kt hp to mt RAM 16x2
bit hoc 32x1 bit ng b .
Storage Element:
 26

Hnh 1.12 .Cu trc Logic Cell hay mt Slice n trong Spartan -IIE
- Cc phn t lu tr trong slice ca Spartan-IIE c th c xem nh mt
Flip-Flop loi D kch hot bng sn, hoc nh mt b cht nhy mc. Cc u vo
D c th c iu khin hoc bi b to chc nng trong slice hoc trc tip t u
vo cc slice (b qua b to chc nng). Thm vo cc ng Clock (CLK) v Clock
Enable (CE) (hnh 1.12), mi Slice c cc tn hiu set v reset ng b (SR v BY).
ng SR p cc phn t lu tr v trng thi khi to, c bit trong trng hp
nhi cu hnh. ng BY p phn t lu tr v trng thi ngc li. C th la chn
hai ng ny chng hot ng khng ng b.
Tt c cc tn hiu iu khin c th o ngc mt cch hon ton c lp v
chng c chia s bi hai Flip-Flop trong mt Slice.
Arithmetic Logic: B dn knh F5IN trong mi Slice c kt hp vi cc
u ra b to chc nng c ch ra hnh 1.13.
 27

Hnh 1.13. B dn knh F5 v F6

S kt hp ny s a ra hoc mt b to hm m n c th thc thi bt k 5
u vo chc nng no, hoc mt b dn knh 4:1 hoc cc chc nng c chn
la ca chn u vo. Tng t, b dn knh F6 kt hp cc u ra ca bn b to
chc nng trong CLB bng vic chn mt trong hai u ra ca b dn knh F5. iu
ny cho php thc thi bt k mt hm 6 u vo no, mt b dn knh 8:1, hoc
chc nng c chn la ln n 19 u vo.
Block RAM: H Spartan-IIE FPGA hp nht mt vi b nh RAM theo khi
thnh khi ln hn (gi l SelectRAM +), c ngha l cn phi b xung thm cc
LUT RAM c dng. Kin trc b nh khng bn vng ny c thc hin
trong cc CLB. Cc khi b nh RAM Block chng c t chc theo cc ct . Hu
ht h Spartan -IIE c cha hai ct nh nhau, mi mt ct c b tr dc theo chiu
ng . H XC2S400E c bn ct RAM khi, mi ct ny c ko di ht chiu cao
ca chip. Mi mt khi nh chnh gm bn CLB cao v v vy mi Spartan-IIE c 8
CLB cao s cha hai khi nh trn mi ct v tng cng c bn khi .
Delay - locked loop (DLL): c kt hp vi mi b m u vo clock ton
cc v l mt vng kho gi chm s DLL m n loi tr c s lch gia b
m u vo clock v cc chn u vo clock bn trong thit b. B DLL gim st
ton b clock u vo v clock c phn phi, t ng iu chnh phn t gi
chm clock. Hn na gi chm c hiu l sn ca clock a ti Flip-Flop
 28

bn trong, vi chnh xc trong mt chu k ng h sau khi chng c a n

u vo. Chu trnh kn ny loi tr nh hng gi chm do phn phi clock bng
vic m bo cc sn ca clock a n cc flip-flop bn trong ng b vi cc
sn clock n ti cc chn vo. loi tr s gi chm do phn chia clock, DLL
a ra tn hiu iu khin hiu chnh cc khong clock khc nhau. DLL cung cp
cc pha vung 900 ca clock ngun m c th nhn i, hoc chia bi cc h s 1.5 ,
2, 2.5 , 3, 4 , 5 , 8 hoc 16 ( Xem hnh di ).

Hnh 1.14. Vng gi chm DLL

Hnh 1.15. Cc c tnh u ra ca DLL

 29

1.3.2. Cu trc ca CoolRunner -XPLA3 CPLD

Cu trc ca XPLA3 mang nt c trng ca mt thanh ghi u vo, nhiu
thnh phn clock, lp trnh qua JTAG, cc ng vo ra dao ng 5V v bao gm
mt cu trc PLA (Programmable Logic Array) y . Vi s phn phi logic linh
hot cng vi cc c tnh m rng ny a ra tc cao gp i, kt qu l n
to ra kh nng thay i thit k m khng cn thay i cc chn u ra. Cu trc
ca n bao gm mt tp hp 48 tch s nhn m c th phn phi ti bt k
Macrocell no trong khi logic. S kt hp ny cho php cc php tnh logic c
phn phi hiu qu trn ton khi logic v h tr nhiu tch s nhn cn thit trn
mi Macrocell. Cu trc tng qut ca mt CPLD c a ra hnh 1.16,1.17.

Hnh 1.16. Cu trc tng qut mc cao ca XPLA3 - CPLD

Hnh 1.17 Cu trc khi ca CoolRunner XPLA3 CPLD

 30

Hnh 1.18. Cu trc chc nng ca CoolRunner XPLA3

Hnh 1.16 ch ra s khi mc cao ca mt thit b 128 macrocell thc
hin cu trc XPLA3. Cu trc XPLA3 bao gm cc khi chc nng (Function
Block) hay khi logic c ni lin vi nhau thng qua ma trn ni ngun khng
(ZIA). Thc cht ZIA l mt chuyn mch im c nh tuyn. Mi khi chc
nng c 36 u vo t khi ZIA v 16 Macrocell (MC). Vi h XPLA3 duy nht ch
l s phn chia logic nm bn trong mi khi chc nng v k thut thit k c s
dng thc hin cc khi chc nng ny.
Theo hnh 1.18 ta thy mi khi chc nng c cha mt ma trn PLA, m n
to ra cc ng iu khin, ng clock v cc logic cell dng cho vic s dng
cc clock khng ng b, reset, preset v Output Enable (Cho php u ra). Mt
PLA rt khc mt PAL (Programmable Array Logic), v vy m PLA c mt ma
trn cc cng AND cho php lp trnh hon ton thng qua lp trnh cc cng OR .
Mt ma trn PAL b c nh bi ma trn cc cng OR ( xem hnh 1.1 v 1.2
Mc 1.1), ma trn PLA nhn cc u vo ca n trc tip t ZIA. C 36 cp u vo
v cc u vo b xung t ZIA, cc u vo ny c cung cp ti 48 tch s nhn
trong ma trn. Bn tm ng tch s nhn ny, th trong c 8 ng iu khin
 31

cc b (LCT [0:7]) c php s dng nh cc tn hiu iu khin ti mi Macrocell

(MC) dng khi s dng cc clock khng ng b, reset, preset v cho php u ra
(OE) Output Enable.
Nu khng dng 8 ng iu khin ny th chng c nhp vi 40 tch s
nhn cn li to ngun logic. Trong mi khi chc nng c 8 ng phn hi
NAND c dng tng hp v tng mt logic, h tr cc hm logic ln hn.
c tnh ny c th c php hoc khng c th do phn mm ngi s dng
qui nh. Cng vi cc tch s nhn, ng iu khin v cc ng phn hi khng
c s dng n, cc ng ny chng li c th gp li v c dng nh mt
ngun ti nguyn logic. Nu c ln hn mt php tnh logic nhn, h s n ti mi
MC th 47 tch s nhn na s c gp li trc to ra VFM ( Variable Function
Multiplexer - B chn knh chc nng bin i ).
B VFM tng s ti u ho logic bng vic thc hin mt vi chc nng logic
u vo trc khi i vo Macrocell xem hnh 1.19.

Hnh 1.19 Cu trc ca mt MacroCell

 32

Hnh 1.20. B dn knh chc nng VFM

Cu trc MacroCell:
Hnh 1.20 ch ra cu trc ca MacroCell (MC) c s dng trong CoolRunner
XPLA3, bt c mt MC no u c th reset hoc preset khi bt ngun.
Mi thanh ghi ca MC c th c xem nh mt flip-flop kiu D, T hoc kiu
cht hoc b qua nu MC c coi l mt hm logic t hp. Mi flip - flop ny c
th nhn ng Clk t bt k mt trong 8 ngun clock hoc phn b xung ca
chng (hnh 1.20).
C hai ng Clk ng b ton cc m chng c ly t 4 chn clk bn
ngoi. Ti y c mt ng CLK chung v cc tn hiu u vo CT [4:7] (Local
Control Terms). C hai ng phn hi ti khi ZIA thng qua b Mux, mt b
Mux s chn hoc u ra ca VFM hoc t u ra ca thanh ghi, mt b Mux cn
li s chn hoc l t u ra ca thanh ghi hoc t ng dn I/O ca MC.
Khi cc chn I/O c s dng nh mt u ra, b m u ra c php chn
v ng phn hi MC c th c s dng lm ng b xung logic trong MC. Khi
chn I/O c s dng lm u vo th cc chn u ra s l ba trng thi v tn hiu
u vo s c a n ZIA thng qua ng phn hi I/O. Cc php Logic b m
c thc hin trong MC c th a n ZIA thng qua ng phn hi ca MC.
Nu mt chn ca MC c t nh mt u vo, th ti c mt ng dn
trc tip ti thanh ghi to thi gian thit lp u vo nhanh. Nu MC c xp
t l mt b cht th u vo clock ca thanh ghi s to chc nng cho php cht v
cht chc chn nht khi tn hiu ny l cao. ng Clock c ni cng s khng
c s dng khi m MC c thc hin nh mt b cht .
 33

I/O Cell :

Hnh 1.21. Cu trc I/O Cell

ng OE ca b chn knh c tm kh nng xy ra ( Xem bng gii m c
ch ra trong hnh trn ). Khi cc I/O cell c t nh mt u vo (hoc u ra ba
trng thi), ng OE ny ko u vo ln cao (thng qua mt b treo mc yu)
nu u vo b th ni v vt ngng. iu ny nhm to ra s bo v u vo vt
khi vng m vng ny chnh l nguyn nhn gy ra vic tiu th ngun ln. Chc
nng nh ca b treo mc yu c th thc hin bng phn mm, chng hn nh n
s lun lun c bt khi I/O cell c xem nh mt u vo. iu ny s lm b
treo t ng bt khi mt chn khng c s dng trong thit k. Cc I/O cell l 5v
(hoc 3.3 V) khi m thit b c cp ngun . Mi u ra c mt b iu khin tc
c lp ( Nhanh hoc chm - cho php t trong phn mm), iu ny s gip
lm gim s pht ra nhiu in t trng. Lu rng mt I/O ca MC khi s
dng mt php logc c thc hin bn trong n th n khng c chn I/O c s
dng cho u vo m n coi chn khng c s dng v cc in tr treo s
c ni. C th ni rng, tt c cc chn ca XPLA3 khng c s dng th
khng c ni. Cc chn u vo m c s dng cho mt mc ch ring no
(CLKx/INx) th khng c in tr treo, v vy cc chn u vo ny cn c u cui
pha ngoi . Nh tt c h CMOS khng cho php cc chn u vo th ni .
Timing Model : " Khun mu xc nh thi gian ", cu trc ny cho php
 34

khun mu thi gian tin nh trong thit k v thit k li .

Hnh 1.22. Cc khun mu thi gian trong CoolRunner XPLA3

C ba khun mu thi gian chnh l TPD, TSU, TCO. Trong cc cu trc khc ta
c th a thit k vo trong CPLD nhng khng m bo c yu cu v thi gian
ca h thng c t c hay khng v c tho mn hay khng cho n khi thit k
c dch v np vo trong thit b . Chnh v vy khun mu xc nh thi gian
ca cc cu trc khc rt phc tp v rt nhiu th cn quan tm, chng hn nh s
ph thuc ca thi gian vo s b m rng song song mn, s b m rng chia s,
s thay i s knh nh tuyn X , Y...
Trong XPLA3 c th bit trc thit k c ph hp vi yu cu thi gian ca
h thng hay khng v n c khun mu xp xp thi gian chun.
1.4. Quy trnh thit k c bn
* Cc bc thit k:
Vi tnh nng ca cc sn phm a ra cu Xilinx, phn mm ISE (Integrated
software Environment) lm cho vic thit k d dng hn vi logic lp trnh
c. Cc thit k c th c m t mt cch d dng v nhanh chng bng vic s
dng ngn ng m t ALBEL, VHDL, VerilogTM, hoc vi mt ng gi t cc s
nguyn l. Vic ly thit k t s nguyn l chnh l phng php truyn
thng m nhng ngi thit k s dng n nh mng cc cng v cc thit b
logic lp trnh c. N l cng c ho v cho php n nh chnh xc cc cng
c yu cu v cch ni chng nh th no.
 35

Di y l bn bc c bn ca mt thit k s dng t s nguyn l :

1. Sau khi la chn cng c to s nguyn l v th vin cc thit b, bt
u xy dng mch bng vic ti cc cng mong mun t th vin c chn. C
th s dng bt k mt t hp cng cn thit no. Lc ny cn phi chn mt th
vin h cc thit b phn phi r rng, nhng c th khng cn phi bit thit b no
trong h . V c bn, ch s dng vi s quan tm v ng gi v tc ca
chng l .
2. Ni cc cng li vi nhau bng vic s dng cc mng v dy ni. Hon tt
vic iu khin ni cc cng theo bt c cu hnh no m cn cho ng dng .
3. a thm v t tn cho cc b m u vo v u ra , cc nhn ny s ch
r cc chn trong ng gi vo ra ca thit b .
4. To danh sch cc mng cc ng ni ca mch.
Hnh 1.23 di y m t lung thit k vi cc PLDs .

Hnh 1.23. Cc bc thit k mt PLD theo s nguyn l

Mt danh sch mng kt ni ( Netlist ) l mt file dng text m t kt ni ca
mt mch. N c to ra bi cc cng c thit k, chng hn nh chng trnh ly
s nguyn l ECS. Netslist l mt file c ng, ngn gn cc chng trnh
khc c th hiu c cng no c ni trong mch v chng c ni vi nhau
nh th no, cc tn ca chn vo ra l g. Trong mt v d di y, Netlist phn
 36

nh mt c php thc t ca mt mch theo dng s . l mt ng ni cho

mi linh kin v mt ng cho mt trong cc mng dy ni. Lu rng chng
trnh my tnh s gn cc tn cho mi linh kin ( G1 n G4 ) v cc ng ni N1
n N8, hnh 1.24 . Khi thc thi thit k ny, n s ng gi cc chn u vo l A,
B, C, D v cc chn u ra l Q, R, S. EDIF ( Electronic Data Interchange Format-
nh dng trao i d liu in t ) theo chun cng nghip cho vic n nh cc
thit k logic dng text v mt dng khc na l XNF ( Xilinx Netlist Format -
nh dng Netlist ca Xilinx). Gi s bn c trong tay mt Netlist, nh vy bn
c tt c nhng g bn cn xc nh ci m mch ca bn nh thit k.

Hnh 1.24. Netlist ca mt thit k

V d trn y l mt v d n gin v r rng. Nh chng ta thy, th m
t mt thit k thc t vi 10.000 cng. Mt trang s nguyn l c cha khong
200 cng, v vy n s cn 50 trang s to ra mt thit k 10.000 cng. Mi
mt trang cn thc hin theo tt c cc bc k trn. iu ny s tiu tn rt nhiu
thi gian, c bit nu mun to mt thit k c 20.000 hoc 50.000 v c th cc
thit k ln hn na. Bn th hnh dung s tiu tn bao nhiu thi gian nu bn to
mt th vin phn phi linh kin v nu cn sa i chng. C mt cch tt hn
thc hin iu ny v n c gi l thit k mc cao (HLD-High Level Design),
hot ng (Behavioral) ca thit k, hoc l ngn ng m t phn cng (HDL).
tng dng ngn ng bc cao m t mch dng file vn bn ny hay hn vic
 37

m t cc cng dng ho rt nhiu. Thut ng hot ng (Behavioral) y

c dng bi v trong ngn ng bc cao chng ta c th m t hm hoc phn
ng ca mch bng li hn l a ra hnh v ca cc cng tng ng m n cn
c to trong ng dng. C hai ngn ng chnh trong ngn ng HDL l : VHDL
v Verilog. Xt mt v d khc, hy thit k mt b nhn 16x16 vi m t bng file
HDL v chng trnh to t s nguyn l ECS. Vi mt b nhn, thng thng l
mt s xp t rt phc tp ca cc b cng, cc thanh ghi v mt s cc cng. V
d ca chng ta cn hai u vo 16 bit ( u vo A v B ) v mt u ra b nhn 32
bit ( Y= AxB ) nh vy tng cng c 64 ng vo ra v tng ng vi khong
gn 6000 cng.Trong vic thc hin bng s nguyn l, s cng yu cu cn phi
c ti vo, t trong trang thit k mch v cn phi c ni vi nhau, cng thm
cc b m vo ra. Cng vic ny chim mt khong ba ngy. Khi thc hin bng
HDL, mt khong 8 dng text v c th hon thnh trong ba pht. File Netlist c
to ra v n c cha tt c cc thng tin cn thit ca mt b nhn 16x16.

Hnh 1.25. Cc thng s ca mt thit k b nhn

* Kim tra thit k : Cc thit k logic lp trnh, c kim tra bng vic s
dng mt b m phng m thc cht n l mt chng trnh phn mm, chng
trnh ny xc nhn tt c cc chc nng hoc thi gian hot ng cu mt mch. Cc
nh dng cng nghip tiu chun c s dng m bo mt iu rng cc thit
k c th c ti s dng. Nu nh c s thay i th vin ca nh phn phi th
 38

thit k ch cn bin dch li qu trnh tng hp nu l cn thit. Li IP (Li s

hu tr tu ) thng cho php khun dng HDL, chng rt d thay i v s dng
vi nh phn phi thit b khc nhau. Sau khi hon tt cc chi tit ca mt thit k,
iu cn phi bit l liu mch thc t c hot ng ng nh mc ch ca thit k
khng. Chnh cu hi ny tr li cho mc ch ca vic kim tra thit k.
B m phng s m phng thit k, v vy cn phi cung cp y thng tin
ca thit k (Thng qua file Netlist sau khi s dng chng trnh ECS hoc thng
qua qu trnh tng hp bng phn mm ) v cc mu u vo c th, hoc thng qua
cc vc t kim tra. B m phng s ly thng tin t xc nh cc u ra ca
mch. Xem hnh sau:

Hnh 1.26. Qu trnh thit k mt PLD

 39

M t tm tt:
- M phng chc nng : Ti giai on ny, s phng chc nng ch kim tra
nhng t hp ng ca khng v mt m mch nguyn l a ra. Ngi thit k s
a ra ch dn s m phng v thi gian ngay sau theo cc bc trong lung thit
k ny. Nu nh c chc nng no khng ng, cn phi quay li s nguyn l
hoc file HDL (Xem hnh 1.26) v sa i li, to li file Netlist v sau cho chy
li b m phng. Nhng ngi thit k thng mt khong 50% thi gian vo vic
sa i i qua bc ny cho n khi thit k t theo yu cu mong mun . Vic
s dng file HDL c rt nhiu thun li khi kim tra thit k : Ngi thit k c th
m phng trc tip t file ngun HDL, iu ny cho php b qua thi gian tiu tn
trong qu trnh tng hp m thi gian ny thng c yu cu mi khi thay i
thit k. Mt thit k khi lm vic ng, chy cng c tng hp to ra file
Netlist cho cc bc tip theo trong qu trnh thit k .
- Thc thi trn thit b : Mt file Netlist cu thit k m t hon ton y
mt thit k m thit k ny s dng th vin cc cng ca nh phn phi ca mt
h thit b no v t nht n cng i qua bc kim tra. n lc a file
ny vo trong mt chip v iu ny c xem nh s thc hin trn thit b.
Bin dch bao s gm nhiu chng trnh s c s dng, cc chng trnh
ny nhp file Netlist ca thit k c dch v dng n b tr, xp xp cc
cng logic. Cc chng trnh ny s khc nhau vi cc nh phn phi th vin khc
nhau.
Cc chng trnh tham gia vo qu trnh bin dch bao gm: Chng trnh ti
u ho, dch cc phn t ca thit b vt l, kim tra cc qui lut thit k vi thit b
c th no (xem n c vt qua s b m Clock cho php trong thit b ny
khng ?... ).
Trong sut giai on thit k, ngi thit k s c hi chn thit b ch,
ng gi, cp v cc chn la khc i vi thit b c n nh . Thng thng
qu trnh bin dch kt thc vi mt bo co kt qu bao hm ton b cc chng
trnh c thc hin. Thm vo cc cnh bo li, dng bn k ca thit b v
vic s sng cc ng vo ra. Chnh iu ny gip ngi thit k la chn c
 40

thit b ch tt nht.
- Lp t trn thit b: i vi h CPLD th bc ny c gi l lp t, c
ngha l a thit k vo trong thit b ch (iu chnh cho ph hp vi ngun ti
nguyn ca thit b ch). Trong hnh v 1.26 trn, c mt phn ca thit k c
gi l lp t vo trong CPLD. Cc CPLD c cu trc c nh , v th nn phn mm
cn ly cc cng v cc ng ni ph hp vi mch thit k. Cng vic ny thng
c phn mm x l rt nhanh bng phn mm. Mt vn khc na c kh nng
xy ra l vic gn v tr ca cc chn vo ra (Thng c gi l s kho chn I/O)
c th b thc hin trc. Thng th iu ny hay xy ra khi dng li mt thit
k m thit k ny c tha hng, hoc thit k ny c np vo board mch
in ca thit k no .
Cc cu trc m n cung cp vic kho cc chn vo ra (chng hn nh XC
9500, CoolRunner CPLDs ) c s thun tin rt ln . Chng cho php gi li cc
chn vo ra gc, bt k thit k thay i hay c s tn dng no , hoc c s thc
hin theo yu cu no . S kho chn rt quan trng khi s dng ISP (In system
Programmable Device - Cho php lp trnh trong h thng), nu mch in v v
ni vi cc chn vo ra, sau thit k b thay i v np li chng trnh, bn hy
yn tm l cc chn ny vn c gi nguyn .
- Sp t v nh tuyn :
Vi h FPGA, chng trnh xp t v nh tuyn c chy sau khi bin dch.
Xp t chnh l qu trnh chn la cc module c th hoc cc khi logic trong
FPGA ni m cc cng ca thit k s nm trong .
nh tuyn n mang ng ngha ca n, chnh l vic ni vt l cc ng
ni gia cc khi logic. Hu ht cc nh phn phi cung cp cng c t ng sp t
v nh tuyn, v th bn khng phi lo lng v cc chi tit kh hiu phc tp ca
cu trc thit b.
Mt s nh phn phi a ra cng c cho php bn sp t v nh tuyn bng
tay nhng phn then cht nht ca thit k, c th thu c s thc hin tt hn
cng c t ng.
B to s mt bng b tr cc phn t logic l mt kiu ca cng c s dng
 41

bng tay.
Chng trnh sp t v nh tuyn cn nhiu thi gian nht hon thin
thnh cng mt thit k, bi v n l cng vic rt phc tp xc nh ni t
nhng thit k ln v m bo rng chng c ni vi nhau chnh xc v p ng
c s thc hin nh mong mun.
Tuy nhin cc chng trnh ny ch c th lm vic tt nu cu trc ca thit b
ch c s nh tuyn ph hp vi thit k.
Bn khng th sa m chng trnh b mt cu trc c hnh thnh sai
lch, c bit nu cu trc ca thit b khng nh tuyn cc ng ni. Nu
nh gp phi vn ny, th gii php chung nht l chn mt thit b ch ln hn.
Mt b phn tch thi gian tnh thng thng l mt phn ca phn mm thc
thi ca nh phn phi. N cung cp thng tin v thi gian ca cc ng dn trong
thit k, thng tin ny rt chnh xc v c th hin th theo nhiu cch khc nhau.
Chng hn nh hin th tt c cc ng ni v xp loi chng t gi chm
di nht n gi chm ngn nht.
Hn na khi ny bn c th s dng thng tin xp t c chi tit ho sau
khi nh dng v quay tr v b m phng c chn vi cc thng tin chi tit v
thi gian.
Qa trnh ny c gi l ch thch ngc (hay thng tin phn hi), n c s
thun li trong vic cung cp chnh xc thi gian ca s thc hin cc s khng v
cc s mt trong thit k cu bn. Trong c hai trng hp, thi gian phn nh s
gi chm ca cc khi logic cng nh cc ng ni.
Bc thc hin cui cui cng l ti hay np cu hnh xung thit b.
- Ti hay np chng trnh:
Ti chng trnh nhn chung c xem nh l ti thng tin xung thit b d
bin i nh SRAM FPGA . ng vi tn gi ca n, bn ti thng tin cu hnh
thit b vo trong b nh ca thit b.
Lung cc bit m n c truyn i c cha tt c cc thng tin nh ngha
logic v cc ng ni cu thit k, thng tin ny s l khc nhau i vi thit k
khc nhau. Xem hnh 1.27.
 42

Hnh 1.27. Gii thch phn bit np chng trnh v ti cu hnh

Do v cc thit b SRAM mt i cu hnh khi mt ngun, v th lung cc bit
cn phi ct u gii quyt vn ny.
Mt ni thng c dng ct thng tin cu hnh thit b, l PROM ni
tip. y l thnh phn kt hp vi phn cng m n ni t my tnh ti bo mch
m bo mch ny c cha thit b ch.
Np chng trnh c dng cho lp chng trnh cho tt c cc thit b
logic c th lp trnh c khng b thay i, chng hn nh PROM ni tip.
Vic np chng trnh thc hin chc nng ging nh ti chng trnh, ring
cc thng tin v cu hnh vn cn sau khi mt in.
Vi cc thit b m c kiu kt ni ngc vi mt cu tr (kt ni mt ln), th
vic np chng trnh ch c th thc hin c mt ln trn thit b hay c th gi
theo thut ng khc : "Cho php lp trnh mt ln ".
Vic np chng trnh i vi cc CPLD ca Xilinx c th thc hin trn h
thng thng qua cp JTAG hoc cng vi b np chng trnh truyn thng.
Qut bin JTAG c hiu thng thng nh mt chun IEEE/ANSI 1149.1-
1190, n l mt dy cc qui lut thit k m cc qui lut ny d kim tra, d np
chng trnh cho thit b v g ri trn chip, trn bo mch mc h thng.
Np chng trnh trn h thng c rt nhiu thun li, v vy thit b c th
c hn trc tip trn bo mch in, v nu c thay i thit k th thit b khng cn
phi tho khi mch m vn lp trnh li trn h thng mt cch n gin .
 43

Chng II
Gii php v t chc phn mm m bo
2.1. Gii thiu s lc
Thit k logic lp trnh c a ra k nguyn m trong mt ca thit
b n v hng triu cng, s thc hin ca h thng tc hng trm MHz.
Xilinx a ra cc cng c thit k in t hon ton y m n cho php
thc hin cc thit k trong h PLD ca Xilinx. Cc gii php pht trin kt hp vi
cc k thut mnh to ra mt s linh hot, mm do, giao tip ho d s dng
gip bn c c cc thit k tt nht c th trong mt d n ln - m khng cn
quan tm n kinh nghim ca bn. Cng c phn mm thit k ISE (Integrated
Sofware Enviroment- Mi trng phn mm tch hp) l cng c thit k tng th,
bao hm cc cng c phn mm thit k chuyn dng khc nhau v y cng l
cng c c s dng nhiu nht trong thit k cc PLD (Programmable Logic
Device) ca Xilinx.
2.2. Cc cng c thit k
Phn mm ISE ci thin ng k thi gian a mt sn phm ra th trng bi
vic tng tc qu trnh nhp thit k. Cc bc thc hin mt thit k c cung cp
trong phn mm ISE, ngoi ra chng cn c h tr thm bi cc phn mm b
xung khc. tin cho vic nm bt v phn loi cc loi phn mm chng ta s i
m t phn ny theo th t thc hin ca mt thit k .
2.2.1 Nhp thit k
Cc cng c h tr cc phng php ph bin nht ngy nay vic to ra mt
thit k bao gm : Nhp thit k bng s , bng ngn ng HDL, bng vic tch
hp cc li IP, h tr mnh m vic ti s dng cc li IP. S a dng ca vic nhp
mt thit k a ra mt mi trng thit k d s dng nht v cho php vi tt
c cc thit k logic. N bao gm cc cng c thit k sau: Schematic Editor, HDL

Editor, State Diagram Editor, Core Generator System, PACE (Pinout and Area
Constraint Editor), Architecture Wizard (DCM-Digital Clock Management, MGT-
Multi_Gigabit Transceiver), Xilinx System Generator for DSP.
 44

2.2.2. Tng hp thit k . ISE ci tin b my tng hp HDL a ra kt

qu ti u ho cho vic tng hp trn cc PLD, y l mt trong cc bc c bn
nht trong phng php thit k. N ly cc nh ngha ca thit k trn HDL v to
ra s m t vt l hoc logic cho thit b silicon ch.
B my tng hp tin tin a ra mt kt qu ti u ho cao vi mt thi gian
iu chnh v thi gian dch nhanh. ph hp vi yu cu ny, b my tng hp
cn phi c tch hp cht ch vi cng c thc hin vt l, hn na s b qua vic
thm d gia thng tin thit k vt l v m thit k HDL ci thin c thi gian
bin i thit k.
Phn mm ISE a ra mt s tch hp gn lin vi cc b my tng hp ch
o nh : Mentor Graphics Leonardo Spectrum, Exempla, Synopsys v Synplicity
Synplify/Pro, ABEL, XST ( Xilinx Synthesis Technology ) .
2.2.3. Thc thi v np cu hnh
Vic thc hin thit k logic lp trnh c l gn cc chc nng logic c to
trong sut qu trnh nhp thit k v tng hp chng vo trong ti nguyn vt l c
th. Thut ng " Xp t v nh tuyn " c s dng m t qu trnh thc hin
cho FPGA, cn " Lp t " c s dng cho CPLD. Thc thi chnh l np cu hnh
cho thit b, m s thc thi ny chnh l to v ti mt lung cc bit c to ra t
thng tin xp t v nh tuyn vo trong cc thit b ch PLD. thc hin phn
ny c cc cng c h tr sau: FloorPlanner, Constraints Editor, Timing Driven
Place & Route, Modular Design, Timing Improvent Wizard .
2.2.4. Tch hp mc Board. Phn mm ISE a ra s h tr mnh m gip
ngi thit k m bo thit k logic lp trnh lm vic trong mt h thng. Xilinx
d bo trc c cc kt qu chnh, chng hn nh vic xp t mt board mch
phc tp, tch hp cc tn hiu, giao tip Bus tc cao, rng di thng vo ra,
cc nhiu in t cho ngi thit k mc h thng. c th d dng thc hin cc
bc ny Xilinx cung cp cc k thut ch o cho FPGA:
- XCITE ( Tr khng iu khin c s ).
- DCM B qun l ng h s cho thi gian ca h thng .
- EMI B qun l nhiu in t trng .
 45

- Thng tin ng gi cho s tch hp mc Board .

- Kim tra mc Board ISE.
N bao gm cc phn mm sau:
- IBIS Models.
- STAMP Models.
- LMG Models.
- ChipScope ILA
2.2.5. Cc k thut kim tra
Phn mm ISE a ra vic kim tra m n h tr trong tt c cc giai on ca
thit k, t khi vo thit k cho n khi tch hp chng trn board.
* Kim tra tnh : Cng c kim tra tnh cho php ngi thit k kim tra thit
k ngoi yu cu. Vic kim tra c th thc hin mi kha cnh hoc kim tra theo
s chn la, cho php tm li trong qu trnh thc thi. Cng c kim tra tnh cng
a ra cc kh nng g ri v phn tch mnh m. Cc cng c kim tra tnh :
- Constraint Editor
- Delay Calculator
- Trace
- Timing Analyzer
- Prime Time
- XPower
- Formality
- Conformal LEC
- DRC
- Chip Viewer
* Kim tra ng : Bao gm cc cng c sau
- HDL Bencher
- ModelSim XE
- State Bench
- HDL Simulation Libraries
 46

* Kim tra mc Board :

Vic s dng cng c kim tra ti mc board nhm m bo rng thit k
thc hin ng theo d nh v chng c tch hp vi phn cn li ca h thng.
Cc cng c ny bao gm :
- IBIS Models
- Tau
- BLAST
- Stamp Models
- Impact
2.2.6 Cng c phn mm nhng cho Virtex-II Pro FPGAs
Cc tu chn vi thit k nng cao ca phn mm ISE chnh l nhm to ra cc
thit k vi mt cao, d dng c gn kt cc phn t logic nh nht.
Thut ng " Cng c phn mm nhng " thng thng c ng dng cho cc
cng c c yu cu dng to, son tho, dch, ti v g ri cc m ngn ng
bc cao nh C, C++ , c dng thc hin trong mt b my x l no . C th
ly mc ch cho cc modul thit k vi Virtex-II Pro Platform FPGA, c th hoc
l mt chip phn cng silicon hoc l cc ng dng phn mm, bn c th chy b
x l mt li cng PowerPC c nhng trong .
Khi ni n s pht trin phn mm nhng, Xilinx a ra s h tr rt nhiu
mc. Xilinx h tr cc b vi x l nhng trong Virtex-II Pro Platform FPGA vi cc
phin bn ca Xilinx, cc cng c ny c dng lm mu cho cc ng dng thc
hin cao v gi thnh thp.
Vi cc k s phn cng, h mun pht trin cc modul thit k vo trong
phn mm v chy trong li PowerPC, th Virtex-II Pro l mt gii php rt n
gin v chi ph thp ca Xilinx.
Vi cc k s phn mm, h mun c mi trng vi cc c tnh phong ph
c th pht trin cc ng dng phc tp hn, Xilinx cung cp kh nng truy cp
cc cng c tt nht dng cho mc ch chuyn dng ho t cc nh dn u cng
nghip nhng. Bn c th a cc thit k m bn c tha hng (Tn dng li)
mt cch d dng vo trong Virtex-II Pro Platform FPGA.
 47

2.3. Li s hu tr tu ca Xilinx ( IP_Core )

Cc Website ca Xilinx c mt c s d liu tng hp ca tt c cc li logic
(LogicCore) m cc li ny c kim tra v chy th . Bn c th tham kho ti
trang Web ca trung tm IP ( Intellectual Property ) www.Xilinx.com/ipcenter.
Cng c CORE Generator t Xilinx a ra cc li logic c ti u ho cao,
tng thch vi cc phng php thit k tiu chun cho Xilinx FPGA. Cng c ny
rt d s dng to ra cc li linh hot, thc hin cao vi mt mc cho php
nh trc.
2.4. Gii thiu v lp trnh ng dng trn phn
mm WebPack ISE 6.2
2.4.1. Tng quan ISE v cc cng c tng hp
Phn mm thit k ISE c kh nng a thit k vo trong cc PLD
(Programmable Logic Device) c chn la cng nh cc bc thc hin thit k
a dng. Nhn chung cc bc tin hnh thit k cho FPGA v CPLD l ging nhau,
ngi thit k c th nhp vo mt thit k di dng mt s hoc dng HDL
(VHDL, Verilog, hoc ABEL).
Mt thit k c th bao gm c di dng s v HDL. Phn mm ISE c
kt hp vi b m phng MXE a ra kh nng m phng v kim tra chc nng
ca VHDL. B m phng MXE a ra mt biu kim tra, n cho php ngi
dng a ra cc mu th test cc chc nng trong qu trnh tng hp (c gi l
TestBencher). Qu trnh tng hp mt thit k c thc hin theo lung cc bc
nh hnh 2.1 di y.
 48

Hnh 2.1. Lung thit k c bn ca CPLD v FPGA

Biu trn ch ra s ging nhau v khc nhau ca cc bc thc hin thit k
mt FPGA v mt CPLD. Khi mt thit k hon thnh, kt qu c th c m
phng v ti xung thit b. c mt cch nhn tng quan v thc hin tip cn cc
bc thit k mt cch nhanh nht, trong mc ny ch a ra mt khi qut s lc
c bn nht v cc mc tip theo xin c trnh by mt v d c th v cc bc
tin hnh thit k trn FPGA v CPLD.
Vi FPGA : Qu trnh thc hin bao gm bn bc c bn sau:
1. Translate - Dch thit k v cho chy kim tra theo qui lut thit k .
2. Map - Tnh ton v cp pht ti nguyn trong thit b ch.
3. Place and Route - Xp t cc khi logic, nh cu hnh ph hp vi cc v
tr logic v s dng cc ti nguyn nh tuyn .
4. Generate Programming File - to ra dng cc bit chng trnh (To file.Bit).
Vi CPLD: Qu trnh thc hin bao gm ba bc c bn sau :
1. Translate - Dch thit k v cho chy kim tra theo qui lut thit k
 49

2. Fit - Cp pht ti nguyn v kt ni .

3. Generate Programming File : To file JED cho chng trnh .
Cc cng c phn mm tng hp thit k ca ISE :
* Vic nhp thit k c vi cch khc nhau v cng c tng hp thit k
chnh l tng hp m ngun c vit di dng VHDL, Verilog, ABEL sang dng
file netlist. Cc thit k di dng s c chuyn i sang m ngun VHDL
hoc Verilog m cc m ngun ny c tng hp bng XST theo dng thng
thng.
* StateCAD l mt cng c phn mm cho php nhp thit k di dng
ho theo nhm cc trng thi, nhm cc trng thi ny s c dch ra HDL v c
nh vo trong phn mm ISE.
* B m phng MXE c th c s dng cho vic m phng c v thi gian
v chc nng .
* HDL Bencher : To ra cc biu kim tra cho php m phng thit k
dng test.
* Implemention : Cng c thc thi ny c mt vi bc v s c gii thiu
k hn trong cc phn sau thng qua v d c th .
* iMPACT Programmer : Modul ny cho php np chng trnh vo thit b
ch ( Lc ny cp JTAG cn phi c ni vi cng song song ca my tnh. )
* CHIP VIEWER : Cng c ny c s dng kim tra thit k sau khi
thc thi cu hnh, ch ra vic kt ni gia cc chn ca thit b .
* Xpower : Cho php tnh ton kh nng tiu th ngun ca thit k khi chy
trong thit b ch .
2.4.2 . Thit k v thc hin thit k trn CPLD v FPGA
tip cn nhanh hn cc cng c phn mm tng hp thit k, y chng
ta s tin hnh thit k trn mt v d c th. Trong mc ny xin gii thiu mt v
d chnh :
"Thit k b iu khin n tn hiu giao thng thc hin trn CoolRunner-II
CPLD v Spartan-3 FPGA"
2.4.2.1 Thit k trn VHDL v StateCAD
 50

1. Nhp thit k: Chn Start-> Program-> Xilinx ISE 6-> Project Navigator.
Chn New Project trong menu File, t project l Traffic v t trong th mc
Traffic.

Hnh 2.2. Ca s nhp tn Project

Nhn nt Next ca s sau s xut hin, chn thit b v cc property nh hnh
di . y ta chn CoolRunner II CPLD - xc2c256.

Hnh 2.3 Ca s nhp New Project

Nhp next v chn New Source nh ca s sau. Chn VHDL modul v t tn
file l Counter .
 51

Hnh 2.4. Ca s chn m son tho chng trnh

Nhp chut vo nt Next v t cc cng vo ra nh sau:
- clock : in
- reset : in
- count : inout [3 down to 0] -- B m 4 bit.
Sau nhp nt Next , Next , Finish .

Hnh 2.5. Ca s nhp u vo ra

Ca s Project Navigator s hin ra nh sau:
 52

Hnh 2.6. Ca s son tho m chng trnh

Nhp p chut vo Counter.vhd trong ca s Sources in Project bn s
c chng trnh to ra mt khung gm cc t kho trong ca s Editor. Bn c th
s dng cc mu chng trnh c sn trong th vin ca Xilinx. Mu ny c gi
l " Language Template". Mu ny l cng c hu dng, n tr gip cho bn trong
khi vit code chng trnh. N bao gm cc modul chc nng thng dng nh b
m , b chn knh, b gii m, thanh ghi dch ... m cc modul mu bn kch
chut vo menu Edit chn Language Template, ca s sau xut hin.
 53

Hnh 2.7. Ca s ly cc mu modul chun

Chn VHDL v kch chut vo du cng ca dng Synthesis Template, chn
modul counter, ko v th chng vo gia Begin v End ca khung chng trnh,
sau thot Language Template. Vo Edit chn Replate v thay clk bng clock .
Xo phn sau y v ch li on code nh hnh 3.8.
if CE='1' then
if LOAD='1' then
COUNT <= DIN;
else
if DIR='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
 54

Hnh 2.8. Ca s m chng trnh b Counter

Nh vy trong chng trnh s gm hai ng vo l clock v reset, mt bus
u ra count ra 4 bit (3 downto 0). Chc nng ca b m ny l m tin khi c
mi xung Clock u vo dng. Tn hiu reset khng ng b v n c xem xt
trc khi xung clock hot ng. Nhn nt save ghi li Project.
2. M phng chc nng ca b m:
T Project Menu chn New Source, chn Test Bench Waveform v t tn
cho file ny l counter_tb nh hnh di.

Hnh 2.9 Ca s chn m ngun son tho

 55

Nhp nt Next, ca s khi to timer hin ra v chn nh ca s di y,

nhn ok, biu kch thch hin ra chun b cho m phng chc nng ca b
m.

Hnh 2.10. Ca s khi to Clock

Hnh 2.11. Ca s khi to kch thch u vo ra cho TestBench

Thit lp cc kch thch vo ra nh sau:
- t ng Reset chu k th nht ln1
 56

- t ng Reset chu k th hai xung 0

- Kch chut vo mu vng ca COUNT[3:0] ti chu k th nht v kch
vo nt Pattern ca s Pattern Wizard hin ra nh sau :

Hnh 2.12. Ca s thit lp b m

Nhn nt OK , lc ny biu sng kch thch s hin ra :

Hnh 2.13. Ca s khi to kch thch vo ra cho TestBench

Kch vo Save ghi li biu sng. Nu mun thay i bn c th kch p
chut vo file counter_tb.tbw khi biu sng s hin ra cho bn sa i. By
 57

gi bn cho chy th biu sng ca b m . Chn file counter_tb.tbw trong ca

s Sources in Project ca mi trng ISE, kch chut phi vo Simulate
Behavioral VHDL Model chn Properties, trong trng Simulation Run Time g
"-all" bm OK. Trong ca s Processes for Source kch p chut vo dng
Simulate Behavioral VHDL Model, dng sng ca b m s c hin ra nh
sau:

Hnh 2.14. Biu sng u ra ca b m

Kch vo nt Save ghi li dng sng di dng file ".do" kch vo nt Close
thot chng trnh.
3. B son tho my trng thi ( StateCAD )
Vi thit k b iu khin n tn hiu giao thng, b m ng vai tr nh
mt timer xc nh thi gian chuyn trng thi . My trng thi bao gm bn
trng thi nh sau:
- Trng thi mt : n sng (Red Light)
- Trng thi hai : n v n vng sng ( Red and Amber light )
- Trng thi ba : n xanh sng ( Green Light )
- Trng thi th t : n vng sng ( Amber Light )
gi b son tho nhm trng thi, chn New Source t Project Menu. Chn
 58

Modul State Diagram v t tn file l stat_mac.dia, kch nt Next sau nhn

finish. Ca s New Source hin ra nh sau:

Hnh 2.15. Ca s chn m ngun son tho

Mi trng son tho nhm trng thi hin ra nh hnh v:

Hnh 2.16. Ca s son tho my trng thi

Kch chut vo biu tng di c nhn Draw State Machines, sau ca s
State Machine Wizard hin ra nh hnh 3.17.
 59

Hnh 2.17. Ca s to nhm cc trng thi my

Chn s trng thi l 4, nhp nt Next sau chn ch reset l
synchronous, nhp nt Next vo ca s chuyn trng thi, y trong hp
chuyn trng thi ta g TIMER .

Hnh 2.18. Ca s thit lp cc kch thch chuyn trng thi

Kch chut vo nt Finish v v cc nhm trng thi trong trang son tho. Khi
nhn nt finish mt khung vung xut hin cng vi mi tn ca con chut v bn
ch vic v mt khung trn nn son tho. Lc ny bn trng thi xut hin v by
gi ta i son cc trng thi . Kch p chut vo Reset State 0 mu vng v thay
i tn ca trng thi ny thnh "RED", sau nhn vo nt "output Wizard".
 60

Hnh 2.19 Ca s son tho trng thi n

Thit k s bao gm ba u ra c t tn l RD, AMB, GRN. Trong trng
DOUT ca hp thoi di y ta g vo RD khai bo u ra, t u ra ny vi
hng l "1" v chn l u ra ca thanh ghi .

Kch chut vo nt OK quay v hp thoi Edit State, lm tng t vi ba

trng thi cn li .
- i tn State1 thnh "REDAMB" v s dng "Output Wizard" thit lp
RD =1 v mt u ra mi vi tn l AMB =1 v u ra l mt thanh ghi.
- i tn State 2 thnh "GREEN" v s dng "Output Wizard" thit lp
mt u ra mi vi tn l GRN =1 v u ra cng chn l thanh ghi.
- i tn State 3 thnh "AMBER" v s dng "Output Wizard" thit lp
mt u ra AMBER =1, u ra cng chn l thanh ghi.. Khi ny nhm trng thi
phi c nh hnh 3.20:
 61

RESET RED

RD = '1';
TIMER
TIMER

REDAMB
AMBER
RD = '1';
AMB = '1'; AMB = '1';

TIMER

TIMER

GREEN

GRN = '1';

Hnh 2.20. Cc nhm trng thi trong b son tho StateMachine

Kch p chut vo ng chuyn trng thi gia trng thi "RED" v
"REDAMB", lc ny bn phi thit lp b Timer hin ra nh ca s hnh 3.21, sau
nhn OK .
Lm tng t nh trn vi ba ng cn li:
- ng gia REDAMB v GREEN , TIMER = "0100"
- ng gia GREEN v AMBER , TIMER = "0011"
- ng gia AMBER v RED , TIMER = "0000"

Hnh 2.21. To iu kin kch thch u ra

Cui cng bn phi khai bo mt vector Timer bi vic kch vo nt bn tri
 62

ca ca s sn tho nhm trng thi c biu tng .Ko v th vo ca s

son tho, kch p vo chng v i tn vector thnh TIMER nh ca s sau.

Hnh 2.22. Ca s to vc t chuyn trng thi

Kch nt OK , khi ny ca s son tho ca bn phi c hnh 3.23.

RESET RED

RD = '1';
TIMER[3:0]
TIMER="1111"
TIMER="0000"

REDAMB
AMBER
RD = '1';
AMB = '1'; AMB = '1';

TIMER="0011" TIMER="0100"

GREEN

GRN = '1';

Hnh 2.23. Cc nhm trng thi sau khi son tho xong

Kch chut vo nt Generate HDL c biu tng . Hp thoi thng bo

kt qu s xut hin, ch dng ch "Compiled Perfectly" ng hp thoi ny, ghi
v ng chng trnh son tho nhm trng thi li. Nhm cc trng thi ny by
gi c nh vo chng trnh ISE ca chng ta. Quay li ISE ta thy chng
trnh n giao thng bao gm hai modul chnh l Counter.vhd v Stat_mac.vhd .
 63

4. Thit k VHDL mc cao: Nh vy trong chng trnh ca chng ta gm hai

modul chnh, by gi chng ta phi th hin hai modul ny trong mt lp trn cng
m c cha hai modul ny, hay cn c gi l th hin chng trong lp chnh-lp
Top. T Project Menu chn New Source v t tn cho chng l top.vhd

Trong ca s Source chn file counter.vhd, trong ca s Process nhp p

chut vo dng View VHDL Instantiation Template trong phn Design Entry
Utilities. Copy phn sau v dn vo phn khai bo component v phn
Instantiation ca file top.vhd.
COMPONENT counter
PORT ( clock : IN std_logic;
reset : IN std_logic;
count : INOUT std_logic_vector(3 downto 0));
END COMPONENT;
 64

Inst_counter: counter PORT MAP (clock => ,

reset => ,
count => );
Tip tc, thc hin tng t trong ca s Sources in Project chn file
stat_mac.vhd, trong ca s Source nhy p vo View VHDL Instantiation
Template. Copy phn khai bo Component v phn Instantiation dn vo file
top.vhd. Khai bo mt Signal timer : std_logic_vector (3 downto 0) di khai bo
cu trc . Sau khi thc hin cc bc ta s c chng trnh ca lp top nh sau.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( clock : in std_logic;
reset : in std_logic;
red_light : out std_logic;
amber_light : out std_logic;
green_light : out std_logic);
end top;
architecture Behavioral of top is
signal timer : std_logic_vector (3 downto 0);
COMPONENT counter
PORT ( clock : IN std_logic;
reset : IN std_logic;
count : INOUT std_logic_vector(3 downto 0));
END COMPONENT;
COMPONENT stat_mac
PORT (TIMER : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
RESET : IN std_logic;
AMB : OUT std_logic;
 65

GRN : OUT std_logic;

RD : OUT std_logic);
END COMPONENT;
begin
Inst_counter: counter PORT MAP (
clock => clock,
reset => reset,
count => timer);
Inst_stat_mac: stat_mac PORT MAP (
TIMER => timer,
CLK => clock,
RESET => reset,
AMB => amber_light,
GRN => green_light,
RD => red_light);
end Behavioral;
Sau khi c c chng trnh nh trn bn nhp nt Save, lc ny trong ca s
Sources in Project s t ng xp xp theo th t. Lp top.vhd l lp trn cng c
cha hai modul con.

Hnh 2.24. Ca s Source ca Project Traffic

By gi ta c th i m phng ton b thit k, chn file top.vhd v trong
menu Project chn New Source, t file m phng l top_tb.tbw. Lc ny cn phi
cho cc kch thch u vo ca thit k. Vi ng tn hiu vo Reset, trong chu k
mt t l High, t chu k th hai l low . Ko ng sc ng mu xanh n chu
 66

k th 64, hoc bm chut phi vo ng sc xanh v chn Set End of

Testbench. Ghi li file testbench ny vi tn file l top_tb.tbw, ng ca s son
tho biu kim tra li. Trong ca s Sources in Project chn file top_tb.tbw.
Trong ca s Processes for Source nhy p vo dng Simulate Behavioral
VHDL Model lc ny ta thu c gin sng ca thit k nh hnh 3.25.

Hnh 2.25. Dng sng u ra ca Project Traffic

n y chng ta c th bc sang phn thc thi trn thit b , xong y xin
gii thiu mt phng php khc c th thc hin c thit k ny.
3.2.2 Thit k trn S ( Schematic Design )
i khi cho d hnh dung c thit k, ngi ta dng phng php thit k
trn s . y chng ta xy dng thit k theo s mc top, kt ni cc khi
trong chng v s dng cng c ECS Schematic.
Gi s ta xy dng c hai modul l counter.vhd v stat_mac.vhd nh
hnh 3.26.
Trong mi trng ISE chn menu Project, chn New Source v t tn cho
thit k lp nh l Top_SCH.
 67

Hnh 2.26. To Project Traffic bi Schematic

Nhp nt NEXT , lc ny b son tho ECS xut hin nh sau:

Hnh 2.27. Ca s son tho ECS

Quay tr li vi mi trng ISE Project Navigator trong ca s Source chn
file counter.vhd, trong ca s Process, kch p vo dng Creat Schematic
Symbol. Thc hin tng t vi file stat_mac.vhd, quay tr li vi mi trng ECS
ta s thy hai biu tng counter v stat_mac trong th vin symbol.
 68

Trong ca s th vin nhy p vo counter v t tr chut vo trong mi

trng son tho, lm tng t vi stat_mac ta s thy hai symbol th hin trong file
top_sch nh sau.

Chn cng c Add Wire bng vic kch vo biu tng , sau ni hai
ng clock v reset ca hai khi li, ng count ni vi ng timer. Sau chn

Add Net Name c biu tng ch abc , lc ny nhp Net xut hin, ta g
clock sau n Enter, t vo net clock, lm tng t vi cc net cn li .

Hnh 2.28. Project Traffic trong ECS

Tip theo phi i t cc im du vo ra. T menu thanh cng c chn Add
I/O Marker, lc ny trong Tab Option s hin Add an input, Add an output. Nu
Marker l u vo th phi chn y l Add an input sau t vo ng clock
v reset. Ghi li v thot khi b son tho ECS. Quay tr li Project Navigator ta
thy top_sch c xp xp ln trn cng. By gi bn c th nhn thy s th
hin ca top_sch di dng VHDL bng cch chn file top_sch trong ca s
Source sau ch vic nhy p vo dng View VHDL Functional Model trong
th mc Design Entry Utilities ca ca s Processes. Tip tc i m phng
top_sch, lm tng t nh phn trc ta cng thu c biu xung nh hnh 3.25 .
2.4.3. Thc thi trn CPLD
2.4.3.1. Tng hp v thc thi trn CPLD
Sau khi m phng thnh cng thit k, qu trnh tng hp s chuyn cc
 69

thit k dng text sang file nestlist c ui ".NGC". File ny bn khng th c

c, v y l file m t mch thc t v n c thc thi mc thp. Thi im
thc thi s s dng file Nestlist v file rng buc ngi dng c ui ".ucf". Bc
u tin chng ta cn thc hin l dch thit k. Bc ny s kim tra thit k v
m bo rng Nestlist ph hp vi cu trc c chn, vic bin dch cng kim tra
file UCF xem c ch no khng ph hp vi cu trc ca CPLD. Sau vic ghp
ni vo thit b ch ( Fitter) s to ra file Jedec v np chng trnh vo thit b ch
hoc board mch thng qua cp song song JTAG.Trong ca s Source chn file
top.vhd hoc chn top_sch, cn trong ca s Processes nhy p vo Check
Syntax. Qu trnh tng hp s t n nhn ra hai modul c th t thp hn l file
Counter.vhd v stat_mac.vhd .Sau khi thc hin Check Syntax xong phi m bo
khng c li no xut hin v phi c ch V mu xanh bn tri dng Synthesize-
XST trong th mc ca Implement Design. Trong mc Synthesize-XST bm
chut phi v chn Properties, kim tra mc Add I/O Buffer trong tab Xilinx
Specific Options c c chn hay khng, sau bm OK. to file ".UCF", cn
phi c s rng buc v chn v v thi gian ca thit b ch. Gi s clock dng cho
thit b ch dng trong v d ca chng ta l 100 MHz v cc chn ra c xc nh
trc trong CoolRunner-II. Trong ca s Source chn file top.vhd , trong project
chn New Source v t tn file ny l top_cosntraints. Chn file ny trong ca s
Source v trong ca s Processes chn Assign Package Pins.

Hnh 2.29 Chn v to file .UCF

Nhp p dng Assign Package Pins, lc ny ca s gn chn PACE s hin
ra nh sau. Ghi li cng vic thc hin trn PACE v EXIT.
 70

Hnh 2.30 Thit lp cc chn vo ra trong PACE

By gi ta c th xem li vic gn chn di dng file text, trong ca s Source
chn file top_cosntraints.ucf, trong ca s Processes kch p chut vo dng Edit
Constraints s thy ca s file ny di dng text.

Hnh 2.31 To file .UCF bng text

Tuy nhin cn phi b xung thm ng tn hiu vo ti nguyn ton cc. V
vy b xung mt b m clock BUFG . G vo ca s text trn dng khai bo sau:
NET "clock" BUFG=CLK;
Ghi li v thot khi ca s son tho ny. Bc tip theo l gn s rng buc
v thi gian. Chn file UCF trong ca s Source, kch p vo dng Create Timing
Constraint trong ca s Processes . Ca s son tho gn s hin ra nh hnh 3.32.
 71

Hnh 2.32 Ca s gn rng buc thi gian v gn chn thit b

Nh chng ta thy ng clock c b son tho gn nhn ra trong trng
Clock Net Name, bm chut phi vo ch clock trong trng ny v chn Period,
ca s Clock Period xut hin. Thit lp gi tr thi gian l 10nS , thi gian cao l
50% , thi gian thp l 50%.
Vic gn khong thi gian c ghi vo file UCF m bn c th nhn thy
cui bn k trong ca s gn. Kch chut vo PORT tab ca b son tho gn, bn
s thy cc chn c gn trong file UCF bc thc hin trc c nhp vo
trong ca s son tho. Dng phm Ctr chn cc u ra, sau g vo hp
Group Name ch lights.
Sau kch vo nt Create Group, trong hp Select Group chn lights v
kch vo nt Clock to Pad. Hp thoi s hin ra v thit lp thi gian theo yu cu
l 15nS, kch nt OK. Khi ny vic gn thi gian c gn vo trong file UCF.
Kch chut vo nt Save v thot khi b son tho gn. Quay li vi mi
trng ISE, nhn trong ca s Processes, bc tip theo l phi cho chng trnh
hon thnh vic thc thi thit k, c ngha l phi m bo c ch V mu xanh bn
tri dng Implement Design. Bm chut phi vo dng ny v chn Properties,
chn mc Fitting. v d ny chng ta chn Output Voltage Standard l
LVCMOS18 (Tc chun vo ra1,8V), nhn OK. Nhy p chut vo dng
Implement Design, lc ny ton b thit k ca chng ta s c thc thi trn thit
 72

b ch m khng c li.

Hnh 2.33. Cc thng bo hon thnh vic bin dch trong ca s Process
Khi ny b phn tch thi gian cng c t ng thc hin v chng trnh
a ra cc thng bo ca Fitter v Timing. Lc ny bn c th xem cc thng bo v
li, v logic, u vo, u ra, danh sch cc chn...bng vic kch vo cc dng
thng bo bn tri trong ct Fitter Report.

Hnh 2.34. Cc thng bo sau bin dch ca CPLD

2.4.3.2. Np chng trnh cho CPLD
Dng cp Parallel - JTAG v b np chng trnh iMPACT ti cu hnh
xung thit b. Ch Jc ngun ca cp phi c ni. Trong ca s Source chn
file top.vhd, nhy p vo dng Configure Device (iMPACT) trong ca s
Processes, ca s b np iMPACT hin ra v thc hin np chng trnh.
2.4.4 Thc thi trn FPGA.
Sau khi m phng thnh cng thit k, qu trnh tng hp s chuyn i thit
 73

k di dng VHDL sang file Nestlist c ui '.NGC '. Bc thc thi s ly file ny
v file rng buc ngi dng to li thit k m n s dng cc ti nguyn cho
php trong FPGA. Sau qu trnh xp xp s phn chia thit k vi cc ti nguyn
cho php trong FPGA, n s dng file .UCF qun l thi gian c gn v quyt
nh a ra xem c th a thm hoc ti to li cc n v logic ph hp vi thi
gian c yu cu. Cc bc thc thi trn FPGA gm bn bc c bn sau y:
- Tng hp thit k
- Lp t
- M phng thi gian
- Np chng trnh
Trong mc ny chng ta s tip tc i thc thi v d b iu khin n tn hiu
giao thng trn Spartan-3 FPGA. Quay li thit k vi CPLD trong ca s Sources
ca Project Navigator nhy p vo dng xc2c256-7tq144-XST VHDL v chn
cc thng s ca FPGA nh hnh sau.

Thit k nguyn thu cho CPLD by gi tr thnh Project cho FPGA

Spartan-3, cc ch V mu xanh trong ca s Processes bin mt v thay vo l
nhng du hi chm mu vng, hin th thit k cn phi c tng hp v thc thi
li.
2.4.4.1. Tng hp thit k.
Trong thit k ca chng ta cng c tng hp s nhn ra file top.vhd gm hai
khi c mc thp hn l "counter" v "stat_mac".Trong ca s Processes kch chut
vo du "+" v chn dng Check Syntax, kch p th ch V mu xanh c hin
 74

th, bi n c kim tra trong phn thc thi ca CPLD.

Kch chut phi vo dng Synthesize v chn Properties vo tab ca HDL
Option chn mc FSM Encoding Algorithm t l one-hot. Trong tab ca Xilinx
Specific Option phi mc Add I/O Buffer c chn, kch nt OK. Trong ca
s Processes kch p vo dng Synthesize v m bo rng c ch V mu xanh
bn tri c hin ln. V ta t ch one-hot nn khi tng hp s c thng bo
cc trng thi ( red , amber, redamb, v green ) s c gn ring thanh ghi mt bit.
Synthesizing Unit <SHELL_STAT_MAC>.
Related source file is D:/Traffic/Traffic/STAT_MAC.vhd.
Found 1-bit register for signal <RD>.
Found 1-bit register for signal <GRN>.
Found 1-bit register for signal <AMB>.
Found 1-bit register for signal <AMBER>.
Found 1-bit register for signal <GREEN>.
Found 1-bit register for signal <RED>.
Found 1-bit register for signal <REDAMB>.
2.4.4.2. File rng buc ngi dng (.UCF).
c c s thc hin cui cng trn thit b bn phi a ra cng c thc
thi thc hin ci g v u. Vi thit k ny gi s c thc hin vi clock c tn
s l 100 MHz, v cc chn ra c xc nh trn FPGA. Trong mc ny file
top_constraints.ucf cn phi c gn cc chn mi, v thit k c dng trong
CPLD. Trong ca s Source chn file ny, cn trong ca s Processes trong User
Constraints kch p vo dng Edit Constraints. Sa i v ghi li, ng ca s
Constraints. Kch p vo dng Assign Package Pins nh hnh di.
 75

Ca s PACE s c khi to, chn cc chn gn cho u vo v ra nh sau:

Hnh 2.35. Gn chn ngi dng trong FPGA

Ghi li v thot khi ca s PACE. Kch p vo dng Create Timing
Constraints trong ca s processes, ca s Constraints Editor hin ra, lc ny cc
chn c gn trong PACE c nhp vo trong ca s ny. Nhy p vo
Period trong tab ca Port, lc ny ca s nh ngha chu k clock hin ra.

Hnh 2.36. Ca s nh ngha Clock

a vo chu k l 10nS , kch chut vo nt OK.Trong tab cu Port ta thy
cc ng vo ra c nhp, dng phm Ctr chn cc u ra.Trong trng
Group Name nhp vo ch lights, nhn Create Group.Trong hp Select Group
chn lights v nhn Clock to Pad.
 76

Trong hp thoi Clock to Pad t Offset =15nS, kch nt OK. Lc ny trng

Clock To Pad c in t ng vo ca s pha di ca Constraints Editor .
Ghi v ng ca s Constraints Editor. Kch p vo Implement Design
trong ca s Processes ca Project Navigator, lc ny cc tch mu xanh hin th
dng Translate, Map, Place and Route . Thit k hon thnh giai on thc thi.

Mi mt giai on thc hin u c mt thng bo. Trong Translate s ch ra

thng bo v li thit k v li rong file UCF, cn trong Map s a ra thng bo v
s xc nhn ti nguyn c s dng trong FPGA....
2.4.4.3. Ti cu hnh xung FPGA.
Kch chut phi vo Generate Programming File v kch vo Properties
trong tab Startup Options, phi m bo rng clock khi ng phi c t l
 77

JTAG Clock, nhn OK. Kch p vo Generate Programming File , thao tc ny

s to ra file ".bit" s dng cho chng trnh np iMPACT. M cng c
Generate Programming File kch p vo Configure Device (iMPACT), (Lc
ny phi m bo cp JTAG c ni vi PC ). Nu nh cc thng s trong thit
k khng c t ng a vo t cng c ISE th kch chut phi vo ca s ca
iMPACT v chn Add Xilinx Device, a ng dn ca thit k v chn file
top.bit sau kch vo biu tng ca thit b .
T Menu Operation chn Program, sau s c thng bo vic np
thnh cng. Tuy nhin vi Board Spartan-3 bn cn lu khi np chng trnh , v
trn n bao gm mt Flash Rom ni tip bn s c chng trnh hi mt s cu
hi trc khi np.
 78

Chng III
Gii thiu ngn ng VHDL
3.1. Cc cu trc c bn ca ngn ng VHDL.
Cc thnh phn chnh xy dng trong ngn ng VHDL c chia ra thnh nm
nhm c bn nh sau:
- Entity
- Architecture
- Package
- Configuration.
- Library.
Entity: Trong mt h thng s, thng thng c thit k theo mt s xp
chng cc modul, m mi Modul ny tng ng vi mt thc th thit k ( c gi
l Entity ) trong VHDL. Mi mt Entity bao gm hai phn :
- Khai bo thc th ( Entity).
- Thn kin trc ( Architecture Bodies )
Mt khai bo Entity c dng m t giao tip bn ngoi ca mt phn t
(component), n bao gm cc khai bo cc cng u vo, cc cng u ra ca phn
t . Phn thn ca kin trc c dng m t s thc hin bn trong ca thc
th .
Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny
c s dng bi mt vi Entity no .
Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t
no cn dng ca mt thit k no c dng mt cu trc v a cc th hin
ny vo trong cp Entity v Architecture.
N cho php ngi thit k c th th nghim thay i cc s thc thi khc
nhau trong mt thit k. Mi mt thit k dng VHDL bao gm mt vi n v th
vin, m mt trong cc th vin ny c dch sn v ct trong mt th vin thit k.
3.1.1 Khai bo Entity:
 79

Nh trn cp, phn khai bo Entity ch a ra mt ci nhn pha bn

ngoi cu mt phn t m khng cung cp thng tin v s thc hin ca phn t
nh th no. C php khai bo ca mt Entity nh sau:
Entity entity_name is
[generic (generic_declaration);]
[port (port_declaration);]
{entity_declarative_item {constants, types, signals};}
end [entity_name];
[] : Du ngoc vung ch ra cc tham s c th la chn.
| : Du gch ng hin th mt s la chn trong s cc la chn khc.
{} : Khai bo mt hoc nhiu cc i tng, m cc i tng ny c th c
nh ngha bi ngi dng.
a. Khai bo Generic dng khai bo cc hng m chng c th c dng
iu khin cu trc v s hot ng ca Entity. C php ca khai bo ny nh
sau:
generic ( constant_name : type [:=init_value]
{;constant_name: type[:=init_value]});
y tn hng constant_name ch ra tn ca mt hng dng generic (hng
dng chung).
Kiu (Type) c dng ch ra kiu d liu ca hng.
init_value : ch ra gi tr khi to cho hng.
b. Khai bo cng ( Port ): c dng khai bo cc cng vo, ra ca Entity.
C php ca khai bo ny nh sau:
Port ( port_name : [mode] type [:= init_value]
{; port_name:[mode] type [:=init_value]});
port_name c dng ch ra tn ca mt cng, mode ch ra hng
vo ra ca tn hiu ti cng . Type ch ra kiu d liu ca mt cng v init_value
ch ra gi tr khi to cho cng .
Ch ! Vi VHDL khng phn bit ch hoa v ch thng, chng hn nh :
 80

xyz = xYz = XYZ.

* C bn mode c s dng trong khai bo cng :
- in : ch c th c c, n ch c dng cho cc tn hiu u vo ( ch c
php nm bn phi php gn )
- out : Ch c dng gn gi tr, n ch c dng cho cc cng u ra (
N ch c nm bn tri ca php gn ).
- inout : C th c dng c v gn gi tr. N c th c nhiu hn mt
hng iu khin ( C th nm bn tri hoc bn phi php gn ).
- Buffer : C th c dng c v gn gi tr. ( C th nm bn tri hoc
bn phi php gn ).
inout l mt cng hai hng, cn Buffer l mt cng khng c hng.
c. entity_declarative_item : c dng khai bo cc hng, kiu d liu,
hoc tn hiu m n c th c s dng trong khi thc hin ca mt Entity.
d. V d :
* V d v khai bo cc cng vo ra:
entity xxx is
port ( A : in integer ;
B : in integer ;
C : out integer ;
D : inout integer ;
E : buffer integer) ;
end xxx;
architecture bhv of xxx is
begin
process (A,B)
begin
C <= A ; -- ( Cu lnh ng: A c gn cho C ).
A <= B ; -- ( Cu lnh sai: A l mt u vo ).
E <= D + 1; -- ( Cu lnh ng: D mode inout v vy n c th c gn v
 81

c )
D <= C + 1; -- ( Cu lnh sai : C l cng u ra nn khng th c c cho
u vo ).
end process;
end bhv;
* V d v khai bo Entity:

A B

COUT FULL_ADDER CIN

SUM

Hnh trn ch ra mt giao din ca mt b cng mt bit. Tn Entity ca phn

t ny l FULL_ADDER. N bao gm cc cng u vo A, B v CIN. Cc
cng ny c kiu d liu l kiu Bit, cn cc cng u ra SUM v COUT cng mang
kiu d liu l kiu BIT. Ngn ng VHDL dng din t giao din ny nh sau:
Entity FULL_ADDER is
port ( A, B, CIN : in BIT;
SUM, COUT : out BIT );
End FULL_ADDER ;
Chng ta c th iu khin cu trc cng nh thi gian ca mt Entity bi vic
s dng cc hng generic. V d sau s ch ra vic iu khin ny, trong v d ny
hng N c dng ch ra s bt ca mt b cng. Trong qu trnh m phng hoc
qu trnh tng hp, gi tr thc t cho mi hng dng chung generic c th b thay
i.
entity ADDER is
generic (N : INTEGER := 4);
 82

M : TIME := 10ns);
port ( A, B : in BIT_VECTOR (N -1 downto 0 );
CIN :in BIT;
SUM : out BIT_VECTOR (N-1 downto 0);
COUT : out BIT );
end ADDER;

Giao din m t b cng ny nh sau:

A (3) B (3) A (2) B (2) A (1) B (1) A (0) B (0)

COUT CIN
FULL _ ADDER

SUM (3) SUM (2) SUM (1) SUM (0)

3.1.2. Cc kiu kin trc ( ARCHITECTURES ):

Mt kin trc a ra kt cu bn trong ca mt Entity. Mt Entity c th c
nhiu hn mt kin trc, n ch ra quan h gia cc u vo v u ra ca mt
Entity m quan h ny c din t theo cc thut ng sau :
- Kiu hnh vi hot ng ( Behavioral ).
- Kiu hot ng ca cc lung d liu ( Dataflow ).
- Kiu cu trc ( Structure ).
Mt kin trc xc nh chc nng ca mt Entity. N bao gm phn khai bo (
Khai bo cc cc tn hiu, hng, khai bo cc kiu, cc phn t, cc phn t, tip
theo l cc pht biu ng thi ).
Khai bo mt kin trc s dng c php sau:
architecture architecture_name of entity_name is
{ architecture_declarative_part }
Begin
{concurrent_statement}
 83

end [ architecture_name ];
3.1.2.1. Kin trc theo kiu hnh vi hot ng ( Behavioral ):
Mt kin trc kiu hnh vi hot ng ch ra cc hot ng m mt h thng
ring bit no phi thc hin trong mt chng trnh, n ging nh vic din t
cc qu trnh hot ng, nhng khng cung cp chi tit m thit k c thc thi
nh th no. Thnh phn ch yu ca vic din t theo kiu hnh vi trong VHDL l
process. Di y l v d ch ra kiu din t theo kiu hnh vi ca mt b cng vi
tn l FULL_ADDER.
architecture BEHAVIOUR of FULL_ADDER is
begin
process (A,B,CIN)
begin
if ( A ='0' and B ='0' and CIN='0' ) then
SUM <= '0';
COUT <= '0' ;
elsif
(A='0' and B='0' and CIN='1') or
(A='0' and B='1' and CIN='0') or
(A='1' and B='0' and CIN='1') then
SUM <= '1';
COUT <= '0' ;
elsif (A='0' and B='1' and CIN='1') or
(A='1' and B='0' and CIN='1') or
(A='1' and B='1' and CIN='0') then
SUM <= '0';
COUT <= '1';
elsif (A='1' and B='1' and CIN='1') then
SUM <='1';
COUT <='1';
end if;
end process;
end BEHAVIOURAL;

3.1.2.2. Kin trc theo kiu hot ng ca cc lung d liu:

Mt kin trc kiu lung d liu ch ra mt h thng di dng m t ng
thi ca cc lung iu khin v dch chuyn ca d liu. N s dng theo mu
 84

thng tin hoc mu hot ng ca lung d liu , hoc mu thi gian ca cc

chc nng logic t hp. Chng hn nh cc b cng, b so snh, b gii m, v cc
cng logic nguyn thu.
V d :
architecture DATAFLOW of FULL_ADDER is
signal S : BIT;
begin
S <= A xor B ;
SUM <= S xor CIN after 10 ns;
COUT <= (A and B ) or (S and CIN) after 5ns;
end DATAFLOW;

3.1.2.3. Kin trc kiu cu trc:

Mt kin trc kiu cu trc ch ra s thc thi cu trc theo dng s dng cc
khai bo phn t v cc th hin ca phn t . V d di y ch ra s din t
cu trc ca mt b cng FULL_ADDER nh trn gii thiu. Hai kiu phn t
c s dng trong v d ny l HALF_ADDER v OR_GATE.
architecture STRUCTURE of FULL_ADDER is
component HALF_ADDER
port (L1, L2 : in BIT;
CARRY, SUM : out BIT);
end component;
component OR_GATE
port (L1, L2 : in BIT;
O: out BIT);
end component;
begin
HA1: HALF_ADDER port map (A,B,N1,N2);
HA2: HALF_ADDER port map (N2,CIN,N3,SUM);
OR1 : OR_GATE port map (N1, N3,COUT);
end STRUCTURE;
v d ny Entity mc cao nht s cha hai th hin ca HALF_ADDER v
mt th hin ca OR_GATE. Th hin HALF_ADDER c th b rng buc vi mt
Entity khc, m Entity ny bao gm mt cng XOR v mt cng AND. Giao tip
ca mt b cng HALF_ADDER c dng nh sau:
 85

L1
X1 SUM

A1 CARRY
L2

B cng ny gm c hai u vo L1 v L2 , u ra l SUM v CARRY. Kiu

BIT l kiu tin nh ngha ca ngn ng VHDL, n c kiu lit k dng ch k t
nh '0' v '1'.
3.1.3. Cc kiu ng gi ( Packages ):
Mc ch chnh ca Package l tp hp cc phn t c th b chia s bi hai
hay nhiu n v thit k ( Hay cc phn t c th dng chung c). N c cha
cc kiu d liu, cc hng, cc chng trnh con c th dng chung gia cc thit
k. Mt Package c cha hai phn chnh:
- Phn khai bo Package.
- Phn thn Package.
3.1.3.1. Phn khai bo Package.
Mt khai bo Package c dng ct gi hng lot cc khai bo dng
chung, chng hn nh cc phn t, cc kiu, cc th tc, cc hm. Cc khai bo ny
c th nhp vo cc n v thit k khc bi vic s dng mt mnh use.
V d :
package EXAMPLE_PACK is
type SUMMER is ( MAY, JUN, JUL, AUG, SEP);
component D_FLIP_FLOP
port (D, CK:in BIT;
Q, QBAR: out BIT)
end component;
constant PIN2PIN_DELAY:TIME:=125ns;
function IN2BIT_VEC(INT_VALUE:INTEGER)
return BIT_VECTOR;
end EXAMPLE_PACK;
v d ny tn ca package c khai bo l EXAMPLE_PACK. N c cha
 86

cc khai bo kiu, phn t, hng, v hm. Lu rng hot ng ca hm

INT2BIT_VEC khng xut hin trong khai bo gi, m ch c giao tip ca hm
xut hin. Vic nh ngha, hay thn ca hm ch xut hin trong thn ca ng gi
( Body Package ).
Gi s rng ng gi ny c dch v to thnh mt th vin thit k v
c gi l DESIGN _LIB . Xem xt vic dng mnh use s dng chng di
y:
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.all
Entity RX is.........

Mnh library DESIGN_LIB cho php th vin thit k DESIGN_LIB c

php dng trong phn m t ny, iu c ngha l tn DESIGN_LIB c th c
s dng. Mnh use tip theo s ly tt c cc khai bo c trong Package
EXAMPLE_PACK vo trong khai bo Entity ca RX. C ngha l ta c th chn
la cc khai bo t trong mt cc khai bo ca mt ng gi vo trong mt n v
thit k khc. V d :
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.D_FLIP_FLOP;
use DESIGN_LIB.EXAMPLE_PACK.PIN2PIN_DELAY;
architecture RX_STRUCTURE of RX is.........

Hai mnh use v d ny nhm to ra khai bo cho D_FLIP_FLOP v khai

bo hng cho PIN2PIN_DELAY c php s dng trong thn kin trc.
3.1.3.2. Phn khai bo thn Package.
S khc bit gia khai bo Package v thn Package c cng mc ch nh
khai bo ca mt Entity v phn thn kin trc Architecture ca chng. C php
khai bo ca Package c khai bo nh sau:
package package_name is
{package_declarative_item}
end [package_name ];

package body package_name is

{package_declarative_item}
 87

end [package_name]
Mt thn package c dng lu cc nh ngha ca mt hm v th tc,
m cc hm v th tc ny chng c khai bo trong phn khai bo package
tng ng. V vy phn thn package lun c kt hp vi phn khai bo ca
chng, hn na mt phn khai bo package lun c t nht mt phn thn package
kt hp vi chng.
V d : package EX_PKG is
subtype INT8 is integer range 0 to 255;
constant zero : INT8:=0;
procedure Incrementer (variable Count : inout INT8);
end EX_PKG;
package body EX_PKG is
procedure Incrementer (variable Data : inout INT8) is
begin
if (Count >= MAX ) then
Count:=ZERO;
else Count:= Count +1;
end if;
end Incrementer;
end EX_PKG;
3.1.4. nh cu hnh ( Configurations ) :
Mi mt Entity bao gm nhiu kin trc khc nhau. Trong qu trnh thit k,
ngi thit k c th mun th nghim vi cc s bin i khc nhau ca thit k
bng vic chn la cc kiu kin trc khc nhau. Configuration c th c s dng
cung cp mt s thay th nhanh cc th hin ca cc phn t ( Component ) trong
mt thit k dng cu trc. C php khai bo ca Configuration ny nh sau:
Configuration configuration_name of entity_name is
{configuration_decalarative_part}
For block_specification
{use_cluse}
 88

{configuration_item}
end for;
Vi mt Entity ca b cng FULL_ADDER nh gii thiu phn trn, v
d ny ta c th s dng chng trong php nh cu hnh nh sau:
configuration FADD_CONFIG of FULL_ADDER is
For STRUCTURE
for HA1, HA2 : HALF_ADDER use entity
burcin.HALF_ADDER(structure);
for OR1: OR_GATE use Entity burcin.OR_GATE;
end for;
end FADD_CONFIG;
y tn ca php nh cu hnh l tu , v d ny ta ly tn l
FADD_CONFIG, cn vi dng lnh For STRUCTURE ch ra kin trc c nh
cu hnh v c s dng vi thc th Entity FULL_ADDER. Gi s rng chng ta
dch hai thc th HALF_ADDER v OR_GATE thnh th vin vi tn l burcin
v s dng chng trong v d trn.
3.1.5. Cc th vin thit k :
Kt qu ca vic bin dch VHDL l chng c ct gi bn trong cc th vin
dng cho bc m phng tip theo, iu ny ging nh vic s dng mt phn t
c khai bo trong mt thit k khc. Mt th vin thit k c th cha cc n
v th vin nh sau:
- Cc ng gi (PACKAGES)
- Cc thc th Entity
- Cc kiu kin trc Architectures
- Cc php nh cu hnh Configurations.
Ch ! VHDL khng h tr cc th vin theo th bc. Bn c th c
nhiu th vin nh theo mun nhng khng c khai bo lng nhau!
m mt th vin v truy cp chng nh mt Entity c bin dch trong
mt thit k VHDL mi, iu u tin cn lm l phi khai bo tn th vin. C
php ca chng nh sau:
 89

Library library_name : [path/directory_name];

Bn c th truy cp cc n v c bin dch t mt th vin VHDL ti ba
mc nh sau:
library_name.Package_name.item_name
V d: Gi s chng ta to mt ng gi ct mt hng m hng ny c s
dng trong nhiu thit k, sau dch n v ct vo trong th vin vi tn l burcin .
Package my_pkg is
constant delay: time:=10ns;
end my_pkg;
Tip n chng ta gi my_pkg s dng chng trong thit k di y:
architecture DATAFLOW of FULL_ADDER is
signal S : BIT;
begin
S <= A xor B;
SUM <= S xor CIN after burcin.my_pkg.delay;
COUT <= (A and B ) or (S and CIN) after 5ns;
end DATAFLOW;
3.2. Cc i tng d liu :
Mt i tng d liu gi mt gi tr ca mt kiu nht nh. Trong VHDL c
ba lp i tng d liu :
- Cc hng ( constants ).
- Cc bin ( Variables ).
- Cc tn hiu ( Signals ).
Lp cu mt i tng c ch ra bi mt t kho v n c ch ra im
bt u ca mt khai bo.
3.2.1. Cc hng ( Constant ):
Mt hng n l mt i tng m n c khi to ch ra mt gi tr c
nh v n khng b thay i. Khai bo hng c php khai bo trong cc ng gi,
cc Entity, cc kin trc, cc chng trnh con, cc khi, v trong pht biu ca cc
qu trnh processes.
 90

C php khai bo chng nh sau :

Constant constant_name {constant_name}: type [:= value];
V d :
constant YES : BOOLEAN:= TRUE;
constant CHAR7: BIT_VECTOR (4 downto 0 ):="00111";
constant MSB: INTEGER:=5;
3.2.2. Cc bin :
Cc bin c dng lu d liu tm thi, chng ch c php khai bo
trong pht biu Process hoc cc chng trnh con.
V d :
variable X,Y : BIT;
variable TEMP: BIT_VECTOR (8 downto 0) ;
variable DELAY : INTERGER range 0 to 15:=5;
3.2.3. Cc kiu tn hiu ( Signal ):
Tn hiu c dng kt ni cc Entity ca thit k li vi nhau v trao i
cc gi tr bin i trong pht biu process. Chng c th c xem nh cc dy
dn hay cc bus ni trong mch thc t. Tn hiu c th c khai bo trong cc
ng gi ( Package ), trong cc khai bo Entity, trong khai bo kin trc
(Architecture), trong cc khi ( Block ). Vi cc tn hiu c khai bo trong cc
package th tn hiu ny c gi l tn hiu ton cc ( Cc thit k c th s dng
chng ), cc tn hiu c khai bo trong Entity l tn hiu ton cc trong mt
Entity, tng t vi tn hiu c khai bo trong mt kin trc, n l tn hiu dng
chung trong mt kin trc .
C php ca chng c dng nh sau :
Signal Signal_name {,signal_name}: type [:=value];
V d :
signal BEEP : BIT:= '0';
signal TEMP: STD_LOGIC_VECTOR (8 downto 0);
signal COUNT: INTEGER range 0 to 100 :=5;
 91

3.3. Cc kiu d liu:

Tt c cc i tng d liu trong VHDL cn phi c nh ngha vi mt
kiu d liu. Mt khai bo kiu phi ch ra tn v di ca kiu . Khai bo kiu d
liu chng c php khai bo trong phn khai bo cc ng gi, trong phn khai
bo Entity, trong phn khai bo kin trc, trong phn khai bo cc chng trnh con
v trong phn khai bo cc Process. Cc kiu d liu bao gm cc kiu sau:
- Kiu lit k
- Kiu nguyn.
- Cc kiu d liu tin nh ngha.
- Kiu mng.
- Kiu bn ghi.
- Kiu d liu chun logic.
- Kiu d liu c du v khng du.
- Cc kiu ph.
3.3.1. Cc kiu lit k ( ENUMERATION ).
Mt kiu lit k c ch ra bi vic lit k cc gi tr cho php ca kiu .
Tt c cc gi tr c nh ngha bi ngi dng c th l cc tn nh danh, hoc
cc cc kiu ch k t . Tn nh danh thc cht l mt tn do ngi dng t ra,
chng hn nh blue, ball, monday. Kiu ch k t l kiu ca cc k t c km theo
du ngoc n, chng hn nh 'x', ' 0'...
C php khai bo cu chng nh sau:
Type type_name is (enumerattion_literal {, enumeration_literal});
Vi type_name l mt tn nh danh v mi enumerattion_literal hoc l mt
tn nh danh hoc l mt ch k t.
V d :
type COLOR is (RED, ORANGE, YELLOW, GREEN, BLUE, PURPLE);

type DAY is (MONDAY,

TUESDAY,WEDNESDAY,THURDAY,FRIDAY);
type STD_LOGIC is ('U','X','0','1','Z','W','L','H','_');
 92

Mi mt nh danh trong mt kiu u c mt v tr nht nh trong kiu,

chng c xc nh bi th t xut hin cu chng trong kiu . Trong v d trn,
mc nh RED c v tr 0, ORANGE s c v tr 1 ..... Nu chng ta khai bo mt
i tng d liu vi kiu l COLOR v khng nh ngha gi tr khi to th i
tng d liu s c khi to mc nh v tr u tin ca kiu lit k ( V tr
khng ), trong trng hp ny COLOR s nhn gi tr RED.
3.3.2. Kiu nguyn :
Kiu nguyn l cc kiu s nguyn, chng c dng cho cc php tnh, cc
ch s, cc iu khin s vng lp. Trong hu ht cc kiu thc thi trong VHDL c
di t - 2,147,483,647 n + 2, 147, 483,647. C php ca chng c khai bo
nh sau:
type type_name is range - 2,147,483,647 to + 2, 147, 483,647;
V d :
type INTEGER is range - 2,147,483,647 to + 2, 147, 483,647;
type COUNT is range 0 to 10;
3.3.3. Cc kiu d liu tin nh ngha trong VHDL :
IEEE nh ngha hai gi d liu STANDART v TEXTIO trong th vin STD.
Mi mt gi d liu ny c cha mt lot cc kiu v cc php tnh chun . Di
y l cc kiu d liu c nh ngha trong gi STANDARD:
- BOOLEAN: Mt kiu lit k vi hai gi tr true v False, cc thao tc Logic
v cc php ton quan h s tr v gi tr Boolean.
- BIT : Mt kiu lit k vi hai gi tr '0' v '1' , cc php tnh logic c th ly
v tr v gi tr kiu BIT.
- CHARACTER: Kiu lit k ca cc m ASCII.
- INTEGER : c dng miu t cc s m v dng. Di hot ng ca
chng c n nh t - 2.147.438.647 n 2.147.438.647. Cc hm ton hc nh
cng, tr ,nhn, chia c h tr kiu nguyn.
- NATURE: Cc kiu con ca kiu nguyn c dng miu t cc s kiu
t nhin ( khng m ).
- POSITIVE: cc kiu con ca kiu nguyn c dng miu t cc s
 93

dng.
- BIT_VECTOR : c dng miu t mt mng cc gi tr kiu BIT.
- STRING : Mt mng cc k t, mt gi tr kiu chui c i km bi du
ngoc kp.
- REAL: c dng m t cc kiu s thc, di hot ng t-1.0E+38 n
+1.0E+38.
- Kiu thi gian vt l : M t cc gi tr thi gian c dng trong m phng.
C mt vi kiu d liu c nh ngha trong gi STANDARD nh sau:
Type BOOLEAN is ( fase, true);
Type BIT is ( '0', '1' );
Type SEVERITY_LEVEL is (note, warning, error, failure );
Type INTEGER is range -2147483648 to 2147483648;
Type REAL is Range -1.0E38 to 1.0E38;
Type CHARACTER is (nul, soh, stx, eot, enq, ack, bel,............);
3.3.4. Kiu mng :
Kiu mng l kiu ca nhm cc phn t c cng kiu ging nhau. C hai kiu
mng nh sau:
- Kiu mng c gn kiu .
- Kiu mng khng b gn kiu.
Kiu mng b gn kiu l kiu m cc ch s mng ca chng c nh ngha
tng minh. C php ca chng nh sau:
type array_type_name is array (discrete_range) of subtype_indication;
y array_type_name l tn ca kiu mng c p kiu, discrete_range
kiu ph ca kiu nguyn khc hoc kiu lit k, subtype_indication chnh l kiu
ca mi phn t ca mng.
Kiu mng khng b gn kiu l kiu m ch s mng ca chng khng b ch
ra, nhng cc kiu ch s ca chng phi c ch ra. C php ca chng c ch ra
nh sau:
type array_type_name is array (type_name range <>) of subtype_indication;
 94

V d :
type A1 is array ( 0 to 31) of INTEGER;
type Bit_Vector is arrray (NATURAL range <>) of BIT;
type STRING is array (POSITIVE range <>) of CHARACTER;
A1 l mt mng gm ba hai phn t m trong mi phn t l mt kiu
nguyn. Mt v d khc ch ra kiu Bit_vector v kiu String c to ra trong chun
cc gi STANDARD.
V d : subtype B1 is BIT_VECTOR ( 3 downto 0);
variable B2 : BIT_VECTOR (0 to 10);
Di ch s xc nh s phn t trong mng v hng ca chng ( low to high |
high to low ).
VHDL cho php khai bo cc mng nhiu chiu c th dng khai bo
cc mu RAM v ROM. Xem v d di y:
type Mat is array (0 to 7, 0 to 3) of BIT;
constant ROM : MAT : = (( '0', '1', '0', '1'),
('1', '1', '0', '1' ),
('0', '1', '1', '1' ),
('0', '1' , '0', '0' ),
('0', '0' ,'0' , '0'),
('1', '1' , '0', '0' ),
('1', '1' , '1', '1' ),
('1', '1' , '0', '0' );
X := ROM (4,3);
Bin X s ly gi tr '0' c t m.
3.3.5. Kiu Record :
Kiu record l mt nhm c nhiu hn mt phn t c cc kiu khc nhau.
Phn t ca Record bao gm cc phn t ca bt c kiu no, n c th l cc kiu
mng hoc kiu Record.
V d :
 95

type DATE_TYPE is ( SUN, MON, TUE , WED , THR , FRI , SAT) ;

type HOLIDAY is
record
YEAR : INTEGER range 1900 to 1999;
MONTH : INTEGER range 1 to 12 ;
DAY : INTEGER range 1 to 31;
DATE : DATE_TYPE;
end record ;
signal S : HOLIDAY;
variable T1: integer range 1900 to 1999;
variable T2 : DATE_TYPE;
T1: = S .YEAR;
T2:= S . DATE;
S . DAY <= 30;
3.3.6. Cc kiu STD_LOGIC :
to mu cc ng tn hiu c nhiu hn hai gi tr ( '0' , '1' ), VHDL nh
ngha chn khong trong gi chun. Chn gi tr bao gm :
type STD_LOGIC is ( 'U' -- khng khi to gi tr
'X' -- Khng xc nh
'0' -- Kiu mc thp
'1' -- Kiu mc cao
'Z' -- Kiu tr khng cao
'W' -- Khng xc nh mc yu
'L' -- Mc thp yu
'H' -- Mc cao yu
'_' -- Khng quan tm n gi tr .);
Tng t nh kiu BIT v kiu BIT_VECTOR, VHDL cung cp mt kiu khc
gi l STD_LOGIC_VECTOR.
s dng cc nh ngha v cc hm trong gi chun logic, cc pht biu sau
y cn c phi khai bo nh km theo chng trnh .
 96

Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
3.3.7. Cc kiu d liu khng du v c du .
Cc kiu d liu c du v khng du chng c ch ra trong cc gi chun
NUMERIC_BIT v NUMERIC_STD. Cc i tng vi kiu c du v khng du
chng c hiu nh l cc s nguyn binary khng du v cc i tng vi kiu
c du v chng c dch nh cc nguyn b hai .
Vic nh ngha ca cc kiu d liu c ch ra nh sau:
type signed is array (NATURAL range <>) of BIT/STD_LOGIC;
Cc pht biu di y bao gm cc khai bo vic s dng ca cc kiu d
kiu c du v khng du.
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_BIT.all;
use IEEE.NUMERIC_STD.all;
3.3.8. Cc kiu con .
VHDL cung cp cc cc kiu con m cc kiu con ny chng c nh ngha
trong cc nh cc tp ph trong mt kiu khc. Bt c u c mt khai bo kiu
th c th xut hin mt nh ngha kiu con. Kiu NATURAL v kiu
POSITIVE l mt kiu ph hay kiu con ca kiu nguyn v chng c th c
dng vi bt k mt hm nguyn no.
V d :
subtype INT4 is INTEGER range 0 to 15;
subtype BIT_VECTOR6 is BIT_VECTOR (5 downto 0);
3.4. Cc ton t :
VHDL cung cp 6 lp ton t , mi mt ton t c mt mc u tin nht nh.
Tt c cc ton t trong cng mt lp th c cng mt mc u tin.
 97

Mc u
tin thp Cc ton t Cc ton hng
nht
.
and
. Cng kiu
Logical_operator or
. Cng kiu
nand
. Cng kiu
. nor Cng kiu
. xor Cng kiu
. = Cng kiu
. Relational _ /= Cng kiu
. operator < Cng kiu
. <= Cng kiu
> Cng kiu
>= Cng kiu
concatenation_op &
erator + Cng kiu
arithmetic_operat - Cng kiu
or
arithmetic_operat + Bt k kiu s no
or - Bt k kiu s no
arithmetic_operat * Cng kiu
or / Cng kiu
mod integer
rem integer
Mc u arithmetic_operat ** Kiu m integer
tin cao or abs Bt k kiu s no
nht not Cng kiu
Logical_operator
3.4.1. Cc ton t logical .
 98

Kiu ton t logic khng chp nhn cc ton hng l cc kiu tin nh ngha
nh kiu BIT, BOOLEAN v cc kiu mng cc bit, cc ton hng cn phi l cng
kiu v cng di.
V d :
signal A,B : BIT_VECTOR (6 downto 0);
signal C,D,E,F,G: BIT;
A<= B and C ; -- Khng xy ra v cc ton hng khng cng
kiu.
D <= (E xor F) and (C xor G);
3.4.2. Cc ton t quan h .
Cc ton t quan h cho ta kt qu c kiu Boolean, cc ton hng cn phi c
cng kiu v cng di.
V d :
signal A,B : BIT_VECTOR (6 downto 0);
signal C: BOOLEAN;
C <= B <= A; ( Tng ng nh C <= (B<=A));
3.4.3. Cc ton t cng .
Cc ton t cng bao gm "+", "-" , v "&" , trong ton t "&" l ton t
kt ni chui v cc i tng l mng cc thanh ghi. Vi s c du v khng du
c th c dng vi cc s nguyn v cc kiu BIT_VECTOR.
V d :
signal W: BIT_VECTOR (3 downto 0);
signal X: INTEGER range 0 to15;
signal Y,Z : UNSIGED (3 downto 0);
Z <= X + Y + Z;
Y <= Z (2 downto 0) & W(1);
"ABC" & "xyz" cho kt qu l : "ABCxyz"
"1010" & "1" cho kt qu l : "10101"
 99

3.5. Cc kiu ton hng .

Trong mt biu thc cc ton t s dng cc ton hng tnh ton cc gi tr
ca chng. Cc ton hng trong mt biu thc bao gm :
- Kiu ch
- Kiu nh danh
- Cc tn c nh theo ch s
- Tn cc Slice
- Tn cc c tnh
- Cc biu thc iu kin
- Cc li gi hm
- Cc biu thc chuyn i
3.5.1. Kiu ch .
Cc kiu ch c th chia ra thnh hai nhm chnh :
- Kiu v hng
. Kiu k t
. Kiu BIT
. Kiu chun STD_LOGIC
. Kiu Boolean
. Kiu s thc
. Kiu nguyn
. Kiu thi gian
- Kiu mng
. Kiu chui
. Kiu BIT_VECTOR
. STD_LOGIC_VECTOR
3.5.1.2. Kiu ch k t .
Kiu ch k t ch ra mt gi tr bng vic s dng mt k t n v km theo
mt du ngoc n. Nhn chung VHDL khng quan tm n cc trng hp ch
thng v ch hoa, xong vi kiu ch k t cn phi phn bit ch thng v ch
hoa. V d : 'a' hon ton khc vi kiu 'A' trong kiu ch k t. Kiu ch k t c
 100

th c dng nh ngha bt c kiu no trong cc ng gi chun v gi tr

mc nh ca chng l Null.
V d : 'A' , 'a' , ......'1' .
Kiu ch k t khng phi l kiu bit k t nh '1' hoc kiu nguyn 1, v vy
kiu ch l t cn phi c cung cp mt tn kiu no .
3.5.1.3. Kiu chui .
Mt kiu chui k t thc cht l mt mng cc k t . Mt chui cc k t
c nh ngha trong mt du ngoc kp .
V d : "A" , " hold time error ", " x " ....
3.5.1.4. Kiu BIT .
Kiu bit l kiu m t hai gi tr ri rc bng vic s dng cc ch k t '0' v
'1'. i khi cc kiu Bit ny c dng to ra kiu ch bit mt cch tng minh
dng phn bit chng vi cc kiu k t.
V d : '1' , ' 0 ' , bit' ('1')
3.5.1.5. Kiu BIT_VECTOR .
Kiu bit_vector l mt mng cc bit m chng c t trong du ngoc kp .
V d : "01001111000" , x"00FFF0" , b"100010101" , o"277756"...
Trong v d trn ch 'x' c dng din t cc gi tr s hexa, cn 'b' c
dng m t kiu binary, cn 'o' c dng cho h m c s 8.
3.5.1.6. Kiu ch trong ng gi chun STD_LOGIC.
Kiu ch logic chun l mt trong 9 gi tr c nh ngha trong ng gi
chun v c a ra di dng cc ch in hoa v t trong du ngoc n .
V d : ' U ' khng trng vi ' u '
'X','0','1','Z','W','L','H','_'
3.5.1.7. Kiu ch STD_LOGIC_VECTOR.
Mt kiu ch STD_LOGIC_VECTOR thc cht l mt mng bao gm cc
phn t ca kiu std_logic v c t trong du ngoc kp.
V d : " 10_1Z" , " UUUUU " , signed("1011 ").....
3.5.1.8. Kiu Boolean .
 101

Kiu Boolean c dng m t hai gi tr ri rc, l kiu true v false.

V d : true , false , True , TRUE, FALSE ...
3.5.1.9. Kiu s thc .
Kiu s thc l kiu c dng din t cc s thc nm trong khong t -
1.0E+38 n +1.0E+38.
Mt kiu s hc c th l kiu dng hoc m nhng chng phi c du chm
thp phn .
V d : + 1.0 khng c vit '1' hoc 1 hoc ' 1.0 '
0.0 khng c vit 0
-1.0 , -1.0E+10.
3.5.1.10. Kiu nguyn .
Mt kiu nguyn c dng din t cc s nguyn nm trong khong t -
2,147,438,647 n + 2,147,438,647.
V d : +1 , 862 862.0 , - 257 , + 123_456 , 16 # 00FF #.
Trong cc k hiu c dng nh ngha kiu nh sau: " C s_n # s
din t trong c s n ", y n nm trong h 2 n 16.
3.5.1.11. Kiu TIME.
Mt kiu vt l duy nht c nh ngha trc trong ng gi chun, l
thi gian time.
V d : 10 ns , 100 us , 6.3 ns ..... Ch phn s phi c vit cch phn n
v o bi mt khong trng.
3.5.2. Cc kiu nh danh:
Kiu nh danh n thun ch l mt ci tn do ngi dng nh ngha, n c
th l tn ca mt hng, mt bin hay mt tn hiu, mt Entity, mt cng, hay mt
chng trnh con, hay cc khai bo tham bin . Khi khai bo mt tn cn phi khai
bo k t u tin phi kiu ch k t, lu du gch di khng c php ng
sau cng, cc t kho ca VHDL khng c dng lm khai bo cc kiu nh
danh, chng hn nh entity, port ....
V d : xyz = xYZ = XYZ = XyZ
 102

S(3) phn t th ba ca mng S

X3.
3.5.3.Kiu INDEX.
Kiu INDEX c s dng ch ra mt phn t no trong mt mng. C
php s dng ca khai bo ny nh sau:
array_name (expression)
Vi array_name l mt tn ca mt hng hay mt bin no nm trong mt
mng. Cn expression phi tr v gi tr nm trong di ch s ca mng .
V d :
type memory is array ( 0 to 7 ) of INTEGER range 0 to 123;
variable DATA_ARRAY : memory;
variable ADDR : INTEGER range 0 to 7;
variable DATA: INTEGER range 0 to 123;
DATA:= DATA_ARRAY ( ADDR );
3.5.4. Kiu Slice v ALIAS.
Mt khai bo Slice c dng ch ra mt s phn t ca mng. Hng ca
n cn phi ph hp vi hng mng. Alias c dng to ra mt tn mi cho tt
c cc hoc mt s phn t no nm trong mt mng.
V d : variable A1: BIT_VECTOR ( 7 downto 0 );
A2: = A1(5 downto 2) ;
Alias A3: BIT_VECTOR (0 to 3) is A1(7 downto 4);
( C ngha l A3(0) = A1(7), A3(1) = A1(6), A3(2) = A1(5), A3(3) = A1(4) )
Alias A4: BIT is A1(3);
3.5.5. Kiu thuc tnh ATTRIBUTE:
Ly cc thuc tnh cu mt bin hay mt tn hiu ca mt kiu cho trc no
v tr v mt kiu gi tr. Di y l cc kiu thuc tnh thng dng trong
ngn ng VHDL:
- Left : Tr v ch s ca phn t bn tri cng ca mt kiu d liu.
- Right : Tr v ch s ca phn t bn phi cng ca mt kiu d liu.
 103

- High : Tr v ch s ca phn t cao nht ca mt kiu d liu.

- Low : Tr v ch s ca phn t thp nht ca mt kiu d liu.
- Range : c dng ly v di ca ch s.
- Reverse_range : Dng xc nh di ch s ngc li.
- Length : Tr v s phn t ca kiu BIT_VECTOR.
- Event : M t s thay i gi tr ca tn hiu ti thi im m phng.
V d : variable A1 : BIT_VECTOR ( 10 downto 0 );
A1' left -- Tr v gi tr l 10.
A1' right -- Tr v gi tr 0.
A1' high -- Tr v gi tr l 10.
A1' low -- Tr v gi tr l 0.
A1' range -- Tr v l 10 downto 0.
A1' reverse_range -- Tr v gi tr l 0 to 10.
A1' length -- Tr v gi tr l 11.
3.5.6. Kiu tp hp :
Kiu tp hp c th c dng gn gi tr cho mt i tng thuc kiu
mng hoc kiu Record trong khi khi to khai bo hoc trong cc pht biu gn.
V d : type color_list ( red, orange, blue, white );
type color_array is array (color_list) of BIT_VECTOR ( 1 downto 0 );
variable X : color_array;
X := (" 00 " , " 01 " , " 10 " ," 11 " );
X := ( red => "00" , blue => "01" , orange => "10" , white => "11" );
Trong dng th hai, chng ta nh ngha mt mng m s cc phn t ca
chng ( di ch s ) c a ra bi color_list. T color_list chng ta c mt mng
gm bn phn t v mng color_array cng s bao gm bn phn t, m mi phn
t ny li c nh ngha bi kiu Bit_Vector. Hn na chng ta s dng di ch s
ca mng color_list s c di t 0 n 3, v vic nh ngha ca mng ny ch ch ra
di ch s ch khng ch ra kiu ca phn t trong mng.
3.5.7. Biu thc gn kiu :
Biu thc gn kiu c dng ch ra kiu ca mt ton hng no . C
 104

php ca chng nh sau:

type_name' ( expression );
V d : type color1 is (red, orange, blue, white);
type color2 is (purple, green, red, black);
color2'(red);
Nh chng ta thy ton hng red c c trong hai kiu color1 v color2, v vy
n cn c phi c gn mt kiu d liu r rng v iu ny c thc hin bi
cu lnh th 3.
3.5.8. Php chuyn i kiu d liu.
Php chuyn i kiu cho php chuyn i cc kiu c kiu d liu gn ging
nhau.
V d : signal X : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Y : STD_ULOGIC_VECTOR ( 3 downto 0 );
Y <= STD_ULOGIC_VECTOR (X);
Sau cu lnh th ba Y s nhn kiu STD_ULOGIC_VECTOR.
3.6. Cc pht biu tun t .
Pht biu tun t ch ra s thc hin tng bc ca mt qu trnh. Chng thc
hin t cu lnh u tin, cu lnh th hai, ... cu lnh cui cng. Cc pht biu nm
trong mt pht biu qu trnh ( Pht biu Process ) c gi l pht biu tun t .
Cc pht biu sau y l cc pht biu tun t c nh ngha trong VHDL:
- Cc pht biu gn bin Variable.
- Cc pht biu gn tn hiu Signal.
- Cc pht biu if.
- Cc pht biu Case.
- Cc pht biu Null.
- Cc pht biu xc nhn ASSERTION.
- Cc pht biu vng lp Loop.
- Cc pht biu NEXT.
- Cc pht biu EXIT.
- Cc pht biu WAIT.
 105

- Cc pht biu Procedure.

- Cc pht biu RETURN.
3.6.1. Pht biu gn bin .
Dng thay th gi tr hin thi ca bin vi mt gi tr mi, gi tr mi ny
c ch ra bi mt biu thc. Bin c th c khai bo v s dng bn trong mt
pht biu qu trnh hay cn c gi l pht biu Process. Mt bin c gn mt
gi tr s dng thng qua pht biu gn bin, m pht biu ny c hnh thc nh sau:
target_variable : = expression;
Lu cc bin c khai bo trong mt Process khng th chuyn gi tr ra
ngoi Process, iu c ngha l chng ch c cp pht trong Process hoc trong
chng trnh con.
V d v php gn bin trong mt Process.

Biu thc c xc nh gi tr khi pht biu c thc thi v gi tr c tnh

 106

ton s c gn cho bin mt cch tc thi.

Bin c to ti thi im sn sinh v duy tr gi tr ca n trong sut
thi gian chy chng trnh. Do v mt qu trnh khng bao gi c thot ra
trong mi trng thi hot ng ca n, ngha l chng c thc thi, hoc
trong mt trng thi ch. Nu trng thi ch th chng phi ch cho n khi
mt s kin khc chc chn xy ra. Mt qu trnh bt u thc hin ti im
khi u ca mt qu trnh m phng, ti thi im ny n c thc thi cho
n khi gp mt pht biu wait hoc gp cc thnh phn c khai bo trong
danh mc cn c x l khai bo trong Process.
Xem th d v pht biu Process nh sau:
V d 1 :
process(A)
variable EVENT_ON_A : INTEGER : = -1;
begin
EVENT_ON_A : = EVENT_ON_A +1;
end process;
V d 2:
Subtype INT16 is INTEGER range 0 to 65536;
Signal S1, S2 : INT16;
Signal GT : BOOLEAN;
process (S1, S2)
variable A, B : INT6;
constant C : INT16 : = 100;
Begin
A := S1 +1 ;
B : = S2*2 - C;
GT <= A > B;
End Process;
Ti lc bt u ca qu trnh m phng. Qu trnh c thc thi mt ln. Bin
EVENT_ON_A c gn gi tr -1 sau tng ln 1. Sau , thi im bt k xy
ra, s kin trn tn hiu A, qu trnh c hiu lc v pht biu gn bin n c thc
thi. N lm cho bin EVENT_ON_A tng ln mt. Ti thi im kt thc ca qu
trnh m phng, bin EVENT_ON_A cha tng s s kin xy ra trn tn hiu A.
Mt th d khc ca pht biu qu trnh :
signal A, Z:INTEGER;
 107

...
PZ: process(A); -- PZ l nhn ca qu trnh
variable V1,V2 : INTEGER;
begin
V1:=A-V2; -- statement 1
Z<= -V1; -- statement 2
V2:= Z+V1*2; -- statement 3
end process PZ;
Gi s mt s kin xy ra trn tn hiu A ti thi im T1 v bin V2 c gn
gi tr l 10, trong pht biu th 3, sau mt s kin xy ra trn tn hiu A ti thi
im T2, gi tr ca V2 c s dng trong pht biu 1 s cng l 10. Mt bin cng
c th c khai bo bn ngoi mt qu trnh hoc mt chng trnh con. Mt bin
c th c c v cp nht bi mt hoc c th nhiu qu trnh, nhng bin ny
c gi l shared variable (Bin chia s).
3.6.2. Pht biu gn tn hiu.
Pht biu gn tn hiu s thay th gi tr hin ti ca tn hiu vi mt gi tr
mi bi vic s dng mt biu thc.
Tn hiu v kt qu ca biu thc cn c cng mt kiu d liu. C php ca
chng nh sau:
target_signal <= [ Transport] expression [after time_expression]
Pht biu gn tn hiu c th xut hin bn trong hoc bn ngoi mt qu trnh.
Nu n xy ra bn ngoi ca mt qu trnh, n c xem l mt pht biu gn tn
hiu ng thi.
Khi pht biu gn tn hiu xut hin bn trong qu trnh, n c xem nh l
mt pht biu gn tn hiu c th t v n c thc thi tun t theo th t ca
nhng pht biu tun t khc xut hin bn trong qu trnh.
V d php gn tn hiu trong mt Process (Vi A,B,C,D l cc tn hiu):
 108

Khi mt pht biu gn tn hiu c thc thi, gi tr ca biu thc c tnh

ton v gi tr ny c chun b gn cho tn hiu sau khi delay. Lu rng biu
thc c nh lng ti thi im pht biu v khng thc thi ngay m n s thc
thi sau mt thi gian gi chm. C hai kiu Delay c cung cp chun b cho
vic thc thi tn hiu:
- Transport Delay.
- Inertial Delay.
a. Transport Delay.
N tng t nh s gi chm bn trong ca mt dng in chy qua dy dn.
Nu thi gian gi chm ny c xem nh tiu tn vo thc hin cng vic no
v tip sau n ( ng thi im ca mt cng vic trc hon thnh ) cn phi thc
hin mt cng vic khc th thi gian thc hin cc cng vic tip theo s c thm
vo cui ca cng vic trc . Cn nu khong thi gian cn thc hin mt cng
vic tin nh ( Thi gian thc hin ca mt cng vic tip theo no ng trc
thi im thc hin mt cng vic trc, th cu lnh Transport s thc hin chn
vo v thc hin cng vic tin nh ny ).
Xem v d sau : Gi s ta c mt process v biu nh sau
 109

1 ns 3 ns 4 ns 5 ns

V d : ..........
process (.....)
Begin
S <= transport 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;
S <= transport 4 after 4 ns;
end process;
Nh v d v biu trn ta thy cng vic th t cn thc hin trc cng
vic th 5, nhng trong phn chng trnh th pht biu ca cng vic th 5 li c
thc hin trc cng vic th t. Hnh v di y m t pht biu Transport, sau 3s
n s c bt sng v sng trong khong thi gian ng bng thi gian bt cng
tc.

b.Inertial Delay.
Inertial Delay ( G chm do qun tnh ), l gi tr mc nh ca VHDL. N
 110

c dng cho cc thit b m khng c phn ng cho n khi u vo c php

trong mt khong thi gian nht nh. Thng th vi tn hiu c khong thi gian
tc ng khng u v nh hn thi gian gi chm ca cc cng th s b b qua.
Vi v d trn, m t hot ng ca n vi gi chm do sc qun tnh ca
mch. Nu thi gian tc ng ca cng tc nh hn gi chm ca mch th u
ra s khng c tc ng hay n s khng c bt sng. Gi s ta c cu lnh n
s c bt sng sau 3 giy, nhng cng tc ch tc ng trong thi gian hai giy th
n s khng c bt sng. Xem hnh v di y:

Gi s ta c cu lnh bt n sau 3s. Khi bt cng tc trong thi gian 4s sau

tt cng tc, th n s c sng sau khi cng tc bt c 3s v sng trong 4s ng
bng thi gian bt cng tc.
Xem hnh di y:
 111

c. So snh INERTIAL DELAY v TRANSPORT DELAY.

Inertial Delay Transport Delay

S <= A after 20 ns S <= Transport A after 20 ns

A
A

S
S

10ns 20ns 30ns 40ns 10ns 20ns 30ns 40ns

Nh trn hnh ta thy trong trng hp Inertial Delay, tn hiu A c tc ng

trong khong 10ns, nhng cu lnh thc hin u ra S sau 20ns, v vy u ra S s
khng c tc ng. Cn trong trng hp Transport Delay tn hiu u ra s c
sao y tn hiu u vo sau khi bt u sn ln ca tn hiu vo c tc ng ( ng
bng khong 20 ns ca cu lnh ).
3.6.3. Cc pht biu IF.
 112

Mt pht biu if c dng chn la nhng pht biu tun t cho vic thc
thi da trn gi tr ca biu thc iu kin. Biu thc iu kin y c th l mt
biu thc bt k m gi tr ca chng phi l kiu lun l.
Dng thng thng ca pht biu if l:
if boolean-expression then
sequential-statements
{elsif boolean-expression then
sequential -statement }
{else
sequential-statement}
enf if;
V d1:
if sum <=100 then -- <= is less-than-or-equal-to operator.
SUM:=SUM+10;
end if;

V d 2:

signal IN1, IN2, OU : STD_LOGIC;

process (IN1, IN2)
begin
if IN1 = '0' or IN2 = '0' then
OU <= '0' ;
elsif IN1 = 'X' or IN2 = 'X' then
OU <= '1';
else
OU <= '1' ;
end if;
end process;
V d 3:
 113

3.6.4. Pht biu CASE.

Dng ca pht biu case l:
case expression is
when choices => sequential -statement -- branch 1
when choices => sequential -statement -- branch 2
-- -- C th c nhiu nhnh
{when others => sequential-statement} -- last branch
end case;
Pht biu case la chn mt trong nhng nhnh cho vic thc thi da trn gi
tr ca biu thc. Gi tr biu thc phi thuc kiu ri rc hoc kiu mng mt chiu.
Cc chn la ( Choices ) c th c din t nh mt gi tr n, hoc mt di gi
tr bng vic s dng du " | " hoc s dng mnh khc. Tt c cc gi tr c th
c ca biu thc phi c th hin trong pht biu case ng mt ln. Cc mnh
khc c th c s dng bao qut tt c cc gi tr, v nu c, phi l nhnh cui
cng trong pht biu case. Mi mt chn la phi c cng kiu vi kiu ca biu
thc. Mt th d cho pht biu case:
V d 1:
type WEEK_DAY is (MON, TUE, WED, THU, FRI, SAT, SUN);
type DOLLARS is range 0 to 10;
variable DAY: WEEK_DAY;
 114

variable POCKET_MONEY: DOLLARS;

case DAY is
when TUE => POCKET_MONEY :=6; -- branch1
when MON | WED => POCKET_MONEY :=2; -- branch2
when FRI to SUN => POCKET_MONEY :=7; -- branch3
when others => POCKET_MONEY :=0; -- branch4
end case;
Nhnh 2 c chn nu DAY c gi tr l MON hoc WED. Nhnh 3 bao gm
cc gi tr FRI, SAT v SUN. Trong khi nhnh 4 gm cc gi tr cn li, THU. Pht
biu case cng l pht biu tun t, tuy nhin n cng c th c pht biu xp
lng nhau.
V d 2:

3.6.5. Pht biu NULL.

Pht biu null
L mt pht biu tun t khng gy ra bt k hnh ng no; H thng s b
qua pht biu NULL v tip tc thc thi vi pht biu k tip. Mt th d cho vic s
 115

dng pht biu ny l trong pht biu if hoc trong pht biu case.
V d : Variable A, B : INTEGER range 0 to 31 ;
Case A is
when 0 to 12 =>
B:= A;
when others =>
Null;
End Case;
3.6.6. Pht biu xc nhn ASSERTION.
Pht biu xc nhn rt hay dng cho vic kim tra thi gian v cc iu kin
ngoi di.
V d : assert (X >3 )
report " Setup violation"
severity warning;
3.6.7. Pht biu Loop.
Mt pht biu lp c s dng lp li mt lot cc cu lnh tun t. C
php ca pht biu lp l:
[loop-label:] iteration-scheme loop
sequential-statements
end loop [loop-lebel];
C 3 kiu s lp. u tin l s lp c dng:
for identifier in range
V d 1: V d v For ...Loop
FACTORAL:=1;
for NUMBER in 2 to N loop
FACTORAL :=FACTORAL*NUMBER;
enf loop;
Trong th d ny, thn ca vng lp thc thi N-1 ln, vi nh danh lp l
NUMBER v tng ln 1 sau mi vng lp. i tng NUMBER c khai bo n
trong vng lp ty thuc vo kiu integer, n c gi tr t 2 n N. V vy khai bo
khng r rng cho nh danh vng lp l iu cn thit, nh danh vng lp cng
khng th c gn cho bt k gi tr no trong vng lp for. Nu mt bin khc c
cng tn c to bn ngoi vng lp for, l hai loi bin c gii quyt ring r
 116

v bin s dng trong vng lp for s chuyn giao cho nh danh vng lp. Vng
ca vng lp FOR cng c th l vng ca mt kiu lit k.
V d 2: type HEXA is ( 0 , 1 , 2 , 3 , A , B , C ); . . . .
for NUM in HEXA ( 2 ) downto HEXA ( 0 ) loop
-- Num s ly nhng gi tr trong kiu HEXA t 2 cho n 0.
end loop;
V d 3: V d v While .... loop

3.6.8. Pht biu Next.

Pht biu next cng l pht biu lin tc cng ch c th s dng bn trong
vng lp. C php tng t nh pht biu exit:
next [loop-label][when condition];
Kt qu ca pht biu next s b qua nhng pht biu cn li trong ln lp hin
ti ca vng lp v tip tc thc thi vi pht biu u tin trong vng lp k tip.
Nu tn ti mt ln v nu nhn vng lp khng r rng th s xy ra hin tng lp
n v cng. i lp vi pht biu exit, n l nguyn nhn ca vng lp b gii hn.
V d 1:
for j in 10 downto 5 loop
if SUM < TOTAL_SUM then
SUM:=SUM +2;
elsif SUM:= TOTAL_SUM then
 117

next;
else
null;
end if;
K:=K+1;
end loop;
Khi pht biu next c thc thi, qu trnh thc hin s nhy n phn cui
ca vng lp (pht biu cui cng K: =K+1) sau gim gi tr ca nh danh vng
lp j, v thc hin li t u.
V d 2:

3.6.9. Pht biu EXIT.

Pht biu exit l mt pht biu tun t n ch c th s dng bn trong vng
lp. N c th lm cho qu trnh thc hin nhy n vng lp trong cng hoc ra
khi vng n v tr ca nhn xc nh no khi n gp nhn ny trong vng lp.
C php ca mt pht biu exit l:
exit [loop-label][when condition]
Nu nhn vng lp khng c ch ra th qu trnh thc hin s lp n
vng lp trong cng. Nu mnh WHEN c s dng th vic tn ti vng
lp ch xy ra nu iu kin l ng. Ngc li, vic thc hin s tip tc vi
 118

pht biu k tip.

V d :
SUM :=1; J:=0 ;
L3:loop
J:=J+21;
SUM:=SUM*10
if (SUM >100) then
exit L3; -- Thc hin exit khi L3 nu Sum> 100
enf if;
end loop L3;
3.6.10. Pht biu WAIT.
Nh chng ta thy, mt qu trnh m phng c th tr hon (Hay treo s
thc hin ca mt pht biu Process hoc mt chng trnh con ) cho n khi gp
mt iu kin ph hp. C 3 hnh thc c bn ca pht biu wait.
wait on sensitivity-list;
wait until boolean -expression;
wait for time-expression;
V d 1: wait on A,B ;
wait until A = B;
wait for 10 ns;
wait on CLOCK for 20 ns ;
wait until SUM >100 for 50 ms;
S hin din ca sensitivity list trong mt qu trnh trng vi trng hp mt trong
ba trng hp trn ca pht biu wait . Mt pht biu qu trnh c wait on cui
ca Process tng ng vi mt pht biu qu trnh c khai bo sensitivity-list.
Xem hnh di y: Hai process ny l tng ng nhau.

V d 2 :
process -- Khng sensitivity list
variable TEMP1, TEMP2:BIT;
 119

begin
TEMP1:=A and B;
TEMP2:=C and D;
TEMP1:=TEMP1 or TEMP2;
Z<=not TEMP1;
wait on A, B, C, D; -- Thay th cho sensitivity-list u Process .
End process.
V d 3: Hai Process trong v d di y ch ra hai process c pht biu Wait
on. Process bn tri s lm cho Process treo ngay sau khi Start v ch cho n khi c
s kin xut hin trn tn hiu SigA. Cn Process bn phi s thc hin ba cu lnh
v sau ri vo trng thi ch n khi xut hin s kin trn tn hiu SigB.

3.6.11. Cc li gi chng trnh con.

Khi m t thit k theo kiu hot ng hnh vi, cc chng trnh con thng
hay c s dng v a ra cch thc s dng thun tin. C hai loi chng trnh
con hay c s dng l Hm v Th tc.
- Th tc ( Procedure) tr v nhiu gi tr.
- Hm ( Function ) tr v mt gi tr n.
Cc li gi th tc s gi th tc m n cn c thc hin trong mt qu
trnh. Pht biu tr v ( return ) s l im kt thc mt chng trnh con, v n ch
c s dng trong mt hm hoc mt th tc. i vi hm th n c qui nh vi
pht biu tr v trong thn hm, nhng vi th tc th c th s dng tu trong
thn th tc. C php ca pht biu tr v nh sau:
return [expression];
y expression s a ra cc gi tr tr v ca hm, pht biu return trong
mt hm cn phi c mt biu thc v gi tr tr v ca n, nhng i vi pht biu
 120

tr v trong th tc th khng cn phi c mt ca biu thc. Mt hm c th c

nhiu hn mt pht biu tr v, nhng ch c mt pht biu tr v c s dng bi
mt li gi hm.
3.7. Cc pht biu ng thi.
Cc pht biu ng thi c thc hin song song trong cng thi im m
phng, chng khng thc hin theo th t m chng c vit ra trong mt kin
trc. Cc pht biu ng thi chuyn thng tin thng qua cc ng tn hiu.
Di y l cc pht biu ng thi c nh ngha trong VHDL:
- Cc pht biu gn ca mt qu trnh (Process).
- Cc pht biu gn tn hiu ng thi .
- Cc pht biu gn tn hiu iu kin.
- Cc pht biu gn tn hiu c chn la.
- Cc pht biu Block.
- Cc li gi th tc ng thi.
- Cc pht biu xc nhn ng thi.
3.7.1. Pht biu Process .
Pht biu process l pht biu bao gm mt tp cc pht biu tun t v pht
biu process li chnh l pht biu ng thi. C ngha l tt c cc pht biu
Process trong mt thit k c thc hin mt cch ng thi. Tuy nhin ti mt
thi im nht nh c a ra ch c mt pht biu tun t c thc hin trong
mi process. Mt Process c kt ni vi phn cn li ca thit k bi vic c
hoc vit ra cc gi tr t cc tn hiu v cc cng m chng c khai bo pha
ngoi Process. C php ca chng c vit nh sau:
[label:] process [(sensitivity_list)]
{process_declaration_part}
begin
{sequential_statements}
end process [label];
Phn khai bo ca mt process ch ra cc i tng m vng hot ng ca n
ch thuc vng ca mt process v chng c th l cc i tng sau y:
 121

- Khai bo bin .
- Khai bo hng .
- Khai bo cc kiu.
- Khai bo cc kiu con.
- Khai bo cc b danh Alias.
- Cc mnh USE.
Mt sensitivity list ( Tp cc s kin thay i trng thi cn x l trong mt
qu trnh ) c cng ngha vi mt Process c cha pht biu wait, m pht biu
wait ny l pht biu cui cng trong mt process v chng c dng sau: Wait
on sensitivity list ;
Mt process c chc nng ging nh mt vng lp v hn m trong n c cha
ton b cc pht biu tun t c ch ra trong vng lp . V vy mt pht biu
process cn phi c hoc mt sensitivity list hoc mt pht biu wait on hoc c hai.
V d 1:
architecture A2 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
pr1 : process (i1, i2, i3, i4)
begin
and_out <= i1 and i2 and i3 and i4;
end process pr1;
pr2 : process (i1, i2, i3, i4)
begin
or_out <= i1 or i2 or i3 or i4 ;
end process pr2;
end A2
V d 2:
 122

3.7.2. Cc php gn tn hiu ng thi.

Mt dng khc ca vic gn tn hiu ng thi l cc php gn tn hiu
ng thi , cc php gn ny c dng bn ngoi ca mt process nhng phi
nm trong mt kin trc ( architecture ). C php ca php gn ny nh sau:
target_sinal <= expression [after time_expression ];
Tng t nh cc php gn tn hiu tun t , mnh after s b b qua bi b
tng hp. Vi bt k mt tn hiu no nm bn phi ca mt php gn u mang
ngha tng t nh mt phn t trong sensitivity list .
Mt thn architecture c th cha s lng bt k ca nhng pht biu gn tn
hiu ng thi. V chng l nhng pht biu ng thi nn th t ca nhng pht
biu l khng quan trng. Nhng pht biu gn tn hiu ng thi c thc thi bt
c khi no c s kin xy ra trong tn hiu c s dng trong biu thc.
V d1 :
architecture A1 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
and_out <= i1 and i2 and i3 and i4;
or_out <= i1 or i2 or i3 or i4;
end A1;
 123

V d 2:
architecture A2 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
process (i1, i2, i3, i4)
begin
and_out <= i1 and i2 and i3 and i4;
end process ;
process (i1, i2, i3, i4)
begin
or_out <= i1 or i2 or i3 or i4 ;
end process ;
end A2
V d 3:
architecture A3 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
process
begin
and_out <= i1 and i2 and i3 and i4;
or_out <= i1 or i2 or i3 or i4;
wait on i1, i2, i3, i4;
end A3;
Ba v d trn y l tng ng nhau.
3.7.3. Cc php gn tn hiu c iu kin v cc php gn tn hiu
c chn la.
a. Cc php gn tn hiu c iu kin.
Mt php gn tn hiu c iu kin chnh l mt pht biu ng thi v c mt
ch gn nht nh, tuy nhin php gn ny c th c nhiu hn mt biu thc cho
 124

mt ch. Ngoi tr biu thc cui cng, cc biu thc cn li phi c mt iu kin
chc chn, cc iu kin ny c nh gi theo th t. Nu mt iu kin c
nh gi l TRUE th biu thc tng ng c s dng, ngc li cc biu thc cn
li s c s dng. Nh rng ch mt biu thc c s dng ti mt thi im . C
php ca cu lnh ny nh sau:
target <= {expression [ after time_expression ] when condition else}
expression [ after time_expression ];
Mt pht biu gn tn hiu c iu kin c th c m t bi mt pht biu
process m process c cha pht biu IF. Bn c th s dng pht biu gn tn hiu
c iu kin trong mt process .
V d 1:
architecture A1 of example is
signal a, b, c ,d : integer ;
begin
a <= b when ( d >10 ) else
c when ( d >5 ) else
d;
end A1;
V d 2:
architecture A2 of example is
signal a, b, c ,d : integer ;
begin
process (b, c, d)
begin
if ( d > 10) then
a <= b
elsif ( d >5 ) then
a <=c;
else
a <= d;
 125

end if;
end process;
end A2;
V d 3: S dng cc pht biu c iu kin.

b. Cc php gn tn hiu c chn la.

Php gn tn hiu c chn la c th ch mt ch gn v cng ch c mt biu
thc with. Gi tr ny c kim tra ging nh pht biu Case thng thng. N s
qun l bt c s thay i no xut hin ti cc tn hiu c chn la. C php ca
chng nh sau:
with choice_expression select
target <= {expression [after time_expression] when choices}
expression [ after time_expression] when choices;
Bt k php gn tn hiu c chn la no u c th c m t tng ng
bi pht biu process c cha pht biu case. Bn khng c s dng pht biu gn
tn c chn la trong mt process .
V d 1:
with SEL select
 126

Z <= a when 0 | 1 | 2,
b when 3 to 10,
c when others;
V d 2 :
process ( SEL, a, b, c )
case SEL is
when 0 | 1 | 2| =>
Z <= a;
when 3 to 10 =>
Z <= b;
when others =>
Z <= C;
end case;
end process ;

Hai v d trn y l hon ton tng ng nhau.

3.7.4. Cc pht biu Block.
Cc block cho php ngi thit k nhm cc phn theo trt t logic ca cc
mu ng thi, vi iu kin l cc phn ny khng nm trong lc s dng ca
cc mu khc ( cc mu m chng c s dng thay th cc thnh phn khc
trong mt thit k ). Cc block c s dng t chc cc pht biu gn ng thi
theo th bc. C php ca chng nh sau:
label : Block
{block_declarative_part}
begin
{concurrent_statement}
end block [label];
Phn khai bo block ch ra cc i tng thuc min cc b ca block v c
th l cc thnh phn sau y:
- Khai bo tn hiu.
- Khai bo hng.
- Khai bo kiu.
- Khai bo cc kiu con.
- Thn cc chng trnh con
 127

- Khai bo b danh ALIAS

- Cc mnh use
- Khai bo cc thnh phn ( Component).
Cc i tng c khai bo trong mt block ch c php hot ng trong
block v cc block vng trong ca n. Khi mt block con khai bo mt i tng
c trng tn vi i tng trong block cha th khai bo ca block con s nh ngha
li i tng trng tn vi block cha.
V d :
architecture BHV of example is
signal : out 1 : integer;
signal : out 2 : bit;
begin
B1 : block
signal S : bit;
begin
B1-1 : block
signal S : integer;
begin
out 1 <= S ;
end block B1-1;
end block B1;

B2: block
begin
out 2 <= S ;
end block B2;
end BHV;
Trong v d ny ta thy block B1-1 l block con ca block B1. C B1 v B1-1
u khai bo tn hiu S. Tn hiu S trong B1-1 s l kiu integer v truyn cho tn
hiu out 1 cng l kiu integer, mc d S c khai bo trong B1 l kiu Bit. Tn
hiu S trong B1 c s dng trong B2 l kiu Bit, trng vi kiu tn hiu out 2.
3.7.5. Cc li gi th tc ng thi.
Mt li gi th tc ng thi chnh l mt li gi th tc m n c thc thi
bn ngoi mt process, n ng c lp trong mt kin trc architecture. Li gi th
tc ng thi bao gm :
- C cc tham s IN, OUT, INOUT.
 128

- C th c nhiu hn mt gi tr tr v
- N c xem nh mt pht biu.
- N tng ng vi mt process c cha mt li gi th tc n.
Hai v d di ay l tng ng nhau.
V d 1:
architecture .................
begin
procedure_any (a,b) ;
end..........;
V d 2:
architecture ................
Begin
process
begin
procedure_ any (a,b);
wait on a,b;
end process ;
end .............;
3.7.6. Cc chng trnh con .
Cc chng trnh con bao gm cc th tc v cc hm m n c th c gi
thc hin cng vic no lp li t cc v tr gi khc nhau trong VHDL. Trong
VHDL cung cp hai kiu chng trnh con khc nhau l:
- Cc th tc (Procedure).
- Cc hm ( Function ).
a. Hm v cc c trng ca hm.
- Chng c gi v thc hin nh mt biu thc.
- Lun tr v mt i s.
- Tt c cc tham s ca hm u phi l ch mode IN.
- Tt c cc tham s ca hm phi thuc lp cc tn hiu hoc cc hng.
- Bt buc phi khai bo kiu ca ga tr tr v .
 129

- Khng c cha cc pht biu Wait.

C php ca hm c khai bo nh sau:
function identifier interface_list return type_mark is
{subprogram_declarative_item}
Begin
{sequential_statement}
end [identifier];
Cc nh danh identifier ch ra tn ca mt hm, cn interface_list ch ra nh
dng tham s ca mt hm. Mi mt tham s c nh nghi theo c php sau:
[class] name_list [mode] type_name [:=expression];
y class ca tham s i tng phi c ch ra l tn hiu hoc hng, cn
mode ca i tng cn phi l mode in. Nu khng c tham s mode c ch ra
th c hiu nh l mode IN, cn nu khng c tham s class c ch ra th tham
s c hiu nh l mt hng. Xem v d sau:
process
function c_to_f ( c : real ) return real is
variable f : real;
begin
f := c*9.0/5.0 + 32.0;
return (f);
end c_to_f;
variable temp : real;
begin
temp : = c_to_f (5.0) + 20.0; -- temp = 61
end process;
Tham s chuyn vo hm c hiu mc nh l mt hng s, v khng c khai
bo ca class.
b. Th tc v cc c trng ca chng.
- Chng c gi nh mt li pht biu.
- C th tr v khng hoc mt hoc nhiu i s.
- Cc tham s chuyn giao cho th tc c th l mode in, out, v inout.
 130

- Cc tham s chuyn giao cho th tc c th l tn hiu, hng, bin.

- C th c cha pht biu Wait.
C php khai bo th tc nh sau:
procedure identifier interface_list is
{subprogram_declarative_item}
begin
{sequential_statement}
end [identifier];
Identifier c s dng ch ra tn ca procedure v interface_list ch ra cc
tham s hnh thc ca procedure. Mi tham s c s dng theo nh ngha sau:
[class] name_list [mode] type_name [:=expression];
Class ca i tng c xem nh hng, bin , hoc l tn hiu v mode ca
i tng c th l in, out , inout. Nu khng c mode c ch ra th tham s c
hiu nh mode in, nu khng c class c ch ra th cc tham s mode in c hiu
nh l cc hng, cn tham s mode out v inout c hiu nh l cc bin.
Cc tham s c th l cc hng, cc bin, hoc cc tn hiu v mode ca chng
c th l in, out, hoc inout. Nu lp ca cc tham s khng xc nh r rng th
mc nhin n l constant, nu n l mode in, cn n l bin nu mode ca tham s
l out hoc inout.
Mt v d thn procedure m t hnh vi hot ng ca cc n v logic s hc
nh sau :
type OP_CODE is ( ADD, SUB, MUL, DIV, LT, LE, EQ);

procedure ARITH_UNIT (A, B : in INTEGER ;

OP : in OP_CODE ;
Z : out INTEGER;
ZCOMP : out BOOLEAN ) is
begin
case OP is
when ADD => Z := A+B;
when SUB => Z := A-B;
when MUL => Z := A*B;
when DIV => Z := A/B;
when LT => ZCOMP := A<B;
 131

when LE => ZCOMP := A<=B;

when EQ => ZCOMP := A=B;
end case ;
end ARITH_UNIT;
Ta xem mt v d khc ca thn mt procedure, procedure ny quay vc t
c xc nh vi tn l ARRAY_NAME, bt u t bit START_BIT ti bit
STOP_BIT, bi mt gi tr ROTATE_BY. Lp i tng ca tham s
ARRAY_NAME c xc nh mt cch tng minh. Bin FILL_VALUE t ng
c khi to v 0 mi khi procedure c gi.
Procedure ROTATE_LEFT
(signal ARRAY_NAME : inout Bit_vector ;
START_BIT, STOP_BIT : in NATUAL;
ROTATE_BY : in POSITIVE ) is
Variable FILL_VALUE : BIT;
begin
assert STOP_BIT > START_BIT
report STOP_BIT is not greater than START_BIT
severity NOTE;
for MACVAR3 in 1 to ROTATE_BY loop
FILL_VALUE := ARRAY_NAME (STOP_BIT);
for MACVAR1 in STOP_BIT downto (START_BIT + 1) loop
ARRAY_NAME (MACVAR1) <= ARRAY_NAME (MACVAR1 1);
end loop;
ARRAY_NAME (START_BIT) <= FILL_VALUE ;
end loop;
end procedure ROTATE_LEFT;
Cc procedure c gi bi li gi procedure. Mt li gi Procedure c th l
mt pht biu tun t hoc mt pht biu ng thi, pht biu ny ph thuc vo ni
xut hin li gi th tc hin ti. Nu li gi ny nm bn trong mt pht biu
process hoc mt chng trnh con khc th n c gi l pht biu gi procedure
tun t, ngc li n c gi l pht biu gi procedure gi ng thi. C php ca
 132

pht biu gi procedure nh sau :

[ label : ] procedure_name ( list_of_actual );
Thc t cc biu thc, cc bin, cc tn hiu hoc cc file, c chuyn vo
trong th tc v cc tn cu i tng v cc tn ny s c dng ly cc gi tr
tnh ton t trong th tc. Chng c ch ra mt cch r rng bi vic s dng s
kt hp theo tn v kt hp theo v tr .
V d:
ARITH_UNIT (D1, D2, ADD, SUM, COMP ); -- S kt hp theo v tr.
ARITH_UNIT ( Z => SUM, B=> D2, A=>D1,
OP=>ADD, ZCOMP => COMP); -- S kt hp theo tn.
Mt pht biu gi th tc tun t c thc thi tun t cng vi cc pht biu
tun t chung quanh n. Mt pht biu gi th tc ng thi c thc thi bt c lc
no khi c mt s kin xy ra trn mt trong cc tham s, m cc tham s ny l
mt tn hiu ch in hoc inout. Mt li gi th tc ng thi c ngha tng
ng vi mt process c cha mt li gi th tc tun t v mt pht biu wait.
Pht biu wait ny s lm cho qu trnh ch cho n khi c mt s kin xut hin
trn cc tham s tn hiu ca mode in hoc inout.
Sau y l mt v d ca li gi th tc ng thi v pht biu process tng
ng vi n:
architecture DUMMY_ARCH of DUMMY is
-- Tip n l thn ca th tc
procedure INT_2_VEC ( signal D : out BIT_VECTOR ;
START_BIT, STOP_BIT : in NATUAL ;
signal VALUE : in INTEGER ) is
begin
-- M t hot ng hnh vi ca th tc
end INT_2_VEC;
begin
-- y l v d ca mt li gi th tc ng thi.
INT_2_VEC (D_ARRAY, START, STOP, SIGNAL_VALUE);
 133

end DUMMY_ARCH;
Pht biu process tng ng vi li gi mt th tc ng thi nh sau:
process
begin
INT_2_VEC (D_ARRAY,START,STOP,SIGNAL_VALUE);
-- Phn th hin ca cc li gi th tc tun t
wait on SIGNAL_VALUE;
-- Ch s kin trn SIGNAL_VALUE v xem chng nh mt tn hiu vo.
end process;
Mt procedure c th s dng hoc l mt pht biu ng thi hoc l
pht biu tun t. Cc li gi ng thi thng xuyn c dng m t
chnh l cc process.
V d ca th tc dng c khai bo postpone ( Tr hon ).
postponend procedure INT_2_VEC ( signal D:out BIT_VECTOR ;
START_BIT,STOP_BIT : in NATUAL;
signal VALUE :in INTEGER) is
begin
-- Phn khai bo hot ng ca th tc
end INT_2_VEC;

Ng ngha ca mt li gi th tc ng thi dng postponed l tng

ng vi nh ngha ca pht biu process tng ng vi n v c gi l
pht biu process b tr hon.
Mt thn process c th c pht biu wait, trong khi mt function th khng
c php c. Cc function c s dng tnh ton cc gi tr mt cch tc th.
V vy mt function khng cn c pht biu wait trong . Mt function khng th
gi mt procedure c pht biu wait trong th tc . Mt process m c cha li
gi mt th tc m trong th tc ny c cha pht biu wait, th process ny khng
c khai bo sensitivity list. Hn na t thc t chng ta thy mt process khng
th nhn bit cc tn hiu thuc sensitivity list v nu c process ny s ri vo trang
 134

thi ch ngay lp tc. Vi mt th tc c cha pht biu wait th bt c bin hay

hng no c khai bo trong th tc s gi nguyn gi tr ca chng trong sut
thi gian thc hin pht biu wait v tn ti ch khi th tc c kt thc.
3.8. Cc ng gi ( Packages ).
Bn c th ng gi ct cc chng trnh con, cc kiu d liu, cc hng
...thng dng s dng chng trong cc thit k khc. Mt package bao gm hai
phn chnh: Phn khai bo v phn thn package, phn khai bo ch ra giao tip cho
package . C php ca khai bo package nh sau:
package package _name is
{package _declarative_item}
end [package _name];
Phn package _declarative_item c th l bt k kiu no sau y:
- Khai bo kiu.
- Khai bo cc kiu con.
- Khai bo tn hiu.
- Khai bo cc hng.
- Khai bo b danh ALIAS.
- Khai bo cc thnh phn.
- Khai bo cc chng trnh con.
- Cc mnh USE.
Ch ! khai bo tn hiu trong package c mt s vn cn lu trong khi
tng hp, bi v mt tn hiu khng th c chia s bi hai Entity. V vy nu
mun dng chung khai bo tn hiu bn phi khai bo tn hiu ny l tn hiu ton
cc.
Phn thn ca package ch ra hot ng thc t ca mt package. Phn thn
ca package phi lun c tn trng vi phn khai bo. C php ca khai bo ny
nh sau:
package body package _name is
{package _body_declarative-item}
end [package _name] ;
 135

Phn package _body_declarative-item c th bao gm:

- Khai bo kiu.
- Khai bo cc kiu con.
- Khai bo cc hng
- Mnh use.
- Thn cc chng trnh con.
V d:
library IEEE;
use IEEE.NUMERIC_BIT.all;
package PKG is
subtype MONTH_TYPE is integer range 0 to 12;
subtype DAY_TYPE is integer range 0 to 31;
subtype BCD4_TYPE is unsigned ( 3 downto 0);
subtype BCD5_TYPE is unsigned ( 4 downto 0) ;
constant BCD5_1: BCD5_TYPE : = b"0_0001" ;
constant BCD5_7: BCD5_TYPE : = b"0_0111" ;
function BCD_INC (L : in BCD4_TYPE) return BCD5_TYPE;
end PKG;
package body PKG is
function BCD_INC (L :in BCD4_TYPE) return BCD5_TYPE is
variable V,V1, V2 : BCD5_TYPE;
begin
V1 : = L + BCD5_1;
V2 : = L + BCD5_7;
case V2(4) is
when ' 0 ' => V : = V1;
when ' 1 ' => V : = V2;
end case;
return (V);
end BCD_INC;
end PKG;

3.9. M hnh cu trc .

Thng thng mt h thng s c m t theo tp hp c th bc ca cc
thnh phn . Mi thnh phn bao gm mt tp cc cng c th giao tip c vi
cc thnh phn khc. Khi m t mt thit k trong VHDL v mt thit k c th bc
chnh l mt thit k a ra cc khai bo ca cc thnh phn v cc pht biu th
hin thnh phn .
 136

Mt n v c s din t hnh vi hot ng chnh l cc pht biu process,

cn n v c s din t theo kiu cu trc chnh l cc pht biu th hin ca
cc n v thnh phn. C hai loi ny u c th c mt trong mt thn ca mt
kin trc ( architecture ).
3.9.1. Cc khai bo thnh phn .
Mt thn kin trc c th s dng cc Entity khc (khng trong cng khai bo
ca architecture ), cc Entity ny c m t tch bit v c t trong th vin
thit k. s dng chng, ngi ta dng cc khai bo thnh phn v cc pht biu
th hin ca chng .Trong m t thit k, mi pht biu khai bo thnh phn phi
tng ng vi mt Entity . Cc pht biu khai bo thnh phn phi ging vi cc
pht biu c ch ra trong Entity (cc pht biu giao tip vo ra ca thnh phn
). C php khai bo ca chng nh sau:
component component _name
[ port ( local_port_declaration ) ]
end component ;
Trong component _name m t tn ca Entity v port_declaration l khai
bo cc cng ca component v phi trng vi phn khai bo ch ra cu
component nm trong phn khai bo ca Entity.
3.9.2. Cc th hin ca component.
Mt component c nh ngha trong mt architecture c th c th hin
thng qua vic s dng cc pht biu th hin ca chng. Khi th hin ch c
php th hin phn giao tip ca component ( Bao gm tn, kiu , hng ca cc
cng vo ra ca chng ), cc tn hiu bn trong chng khng c th hin. C php
th hin component nh sau:
instantiation_label : component _name
port map (
[ local_port_name =>] expression
{ [local_port_name =>] expression}
);
Mt pht biu th hin component cn phi khai bo phn nhn ca th hin
trc instantiation_label. Hnh v di y m t phn giao din v phn thc thi
 137

bn trong ca mt b cng full_Adder.

A
Sum
B FULL_Adder
Cin Cout

Phn giao din component ca b cng Full_adder.

Cin
A
N1 SUM

N3
Cout

N2

Phn thc thi bn trong ca component Full_Adder.

Nh trn hnh v chng ta thy phn thc thi c ba loi cng khc nhau v
chng c mang tn nh sau: OR2_gate, AND2_gate, XOR_gate, chng c
dng xy dng nn b cng. m t v th hin chng trong thit k, ta c th
vit chng trnh thc thi tng thnh phn ca chng nh sau:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity AND2_gate is
port ( I0, I1 : in STD_LOGIC ;
O : out STD_LOGIC );
End AND2_gate;
Architecture BHV of AND2_gate is
Begin
O <= I0 and I1;
End BHV;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity XOR_gate is
port ( I0, I1 : in STD_LOGIC ;
O : out STD_LOGIC );
End XOR_gate;
Architecture BHV of XOR_gate is
 138

Begin
O <= I0 xor I1;
End BHV;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity OR2_gate is
port ( I0, I1 : in STD_LOGIC ;
O : out STD_LOGIC );
End OR2_gate;
Architecture BHV of OR2_gate is
Begin
O <= I0 xor I1;
End BHV;

th hin cc component ny trong mt thit k, ta khai bo chng nh sau:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity FULL_ADDER is
port (A, B, Cin : in STD_LOGIC;
Sum, Cout : out STD_LOGIC);
End FULL_ADDER;

Architecture IMP of FULL_ADDER is

component XOR_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component ;

component AND2_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component;
component OR2_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component;
signal N1, N2, N3: STD_LOGIC;
 139

begin
U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1);
U2 :AND2_gate port map ( A, B, N2);
U3 :AND2_gate port map ( Cin, N1, N3);
U4 :XOR_gate port map ( Cin, N1, Sum);
U5 :OR2_gate port map ( N3, N2, Cout);
end IMP;
3.9.3. Cc pht biu Generate.
Pht biu generate l mt pht biu ng thi v n c nh ngha trong
phn architecture. N c dng m t cc cu trc ging nhau, hay ti to li
cc cu trc khc ging nh bn gc. C php ca chng nh sau:
instantiation _label : generation_scheme generate
{concurrent_statement}
end generate [instantiation _label];
C hai loi lc generation : Lc for v lc if. Lc for c
dng din t cu trc thng thng, n c dng khai bo mt tham s
generate v mt di ri rc ca lc for ( ch ra tham s vng lp v di ri rc
trong cc pht biu lp tun t ). Cc gi tr tham s ca generate c th c c
nhng khng c gn hay chuyn ra ngoi pht biu generate.
a. S dng lc for:
V d : Gi s ta c b cng 4 bit m trong bao gm bn b cng
Full_adder nh c m t trn. Xem hnh di y:
 140

X (3) Y (3) X (2) Y (2) X (1) Y (1) X (0) Y (0)

Cout '0'
FA (3) FA (2) FA (1) FA (0)

Z (3) Z (2) Z (1) Z (0)

m t b cng 4 bit ny v s dng pht biu generate, s dng m t b

cng Full_Adder nh trn ta m t. Ta c th vit chng nh sau:
architecture IMP of FULL_ADDER4 is
signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ;
signal Cout : STD_LOGIC ;
signal TMP : STD_LOGIC_VECTOR ( 4 downto 0 ) ;

component FULL_ADDER
port ( A, B, Cin : in STD_LOGIC ;
Sum, Cout : out STD_LOGIC );
end component ;
begin
TMP (0) <= ' 0 ';
G : for I in 0 to 3 generate
FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 ));
end generate ;
Cout <= TMP (4);
end IMP;
 141

b. S dng lc if.
X (3) Y (3) X (2) Y (2) X (1) Y (1) X (0) Y (0)

Cout
FA (3) FA (2) FA (1) HA (0)

Z (3) Z (2) Z (1) Z (0)

S b cng bn bit s dng mt b cng

Half_ADDER v ba b cng FULL_ADDER
Mt s cu trc c dng khng theo qui lut chun no, vi trng hp ny ta
c th s dng lc if. Gi s ta m t b cng bn bit nh trn hnh trn v s
dng lc IF generate m t b cng ny. Chng trnh c vit nh sau:
architecture IMP of FULL_ADDER4 is

signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ;

signal Cout : STD_LOGIC ;
signal TMP : STD_LOGIC_VECTOR ( 4 downto 1) ;
component FULL_ADDER
port ( A, B, Cin : in STD_LOGIC ;
Sum, Cout : out STD_LOGIC );
end component ;

component HALF_ADDER
port ( A, B : in STD_LOGIC ;
Sum, Cout : out STD_LOGIC );
end component ;
begin
G0 : for I in 0 to 3 generate

G1: if I = 0 generate
 142

HA: HALF_ADDER port map ( X (I), Y(I), Z (I), TMP ( I+1 ));
end generate ;

G2: if I >= 1 and I <= 3 generate

FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 ));
end generate ;

end generate ;
Cout <= TMP ( 4 );
end IMP;
3.9.4. Cc thng s ca vic nh cu hnh.
Trong mt Entity c th c mt vi cu trc, v vy cc chi tit cu vic nh
cu hnh cho php ngi thit k chn cc Entity v kin trc ca n. C php khai
bo ca chng nh sau:
for instantiation _list : component _name
use Entity library_name. Entity _name [( architecture _name)] ;
Nu ch c mt kin trc architecture th tn architecture c th b b qua.
Xem thm mt v d di y:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity FULL_ADDER is
port (A, B, Cin : in STD_LOGIC;
Sum, Cout : out STD_LOGIC);
End FULL_ADDER;
Architecture IMP of FULL_ADDER is
component XOR_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component ;
component AND2_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component;
component OR2_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
 143

end component;
signal N1, N2, N3: STD_LOGIC;
for U1 : XOR_gate use entity work.XOR_gate (BHV);
for others : XOR_gate use entity work.XOR_gate (BHV);
for all : AND2_gate use entity work.AND2_gate (BHV);
for U5 : OR2_gate use entity work.OR2_gate (BHV);

begin
U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1);
U2 :AND2_gate port map ( A, B, N2);
U3 :AND2_gate port map ( Cin, N1, N3);
U4 :XOR_gate port map ( Cin, N1, Sum);
U5 :OR2_gate port map ( N3, N2, Cout);
end IMP;

3.10. M hnh mc RT (Register Tranfer) v cc mch logic t hp.

DIN DOUT
Combinational
Logic
register

clock

Mt thit k mc chuyn i thanh ghi bao gm mt tp cc thanh ghi c

kt ni vi mch logic t hp nh c ch ra trn hnh v. Mt process khng c
cha cc pht biu if trn cc sn chuyn i tn hiu hoc cc pht biu wait trn
cc s kin ca tn hiu th c gi l cc process t hp.
Tt c cc pht biu tun t ngoi tr pht biu wait , pht biu lp, pht biu
if trn sn chuyn i tn hiu c th c s dng m t cc mch logic t hp
.
 144

Cc mch logc t hp khng c b nh nh cc gi tr. V vy mt bin

hoc mt tn hiu cn phi c gn mt gi tr trc khi c tham chiu. y l
mt v d m t mch logic t hp :
process (A, B, Cin)
begin
Cout <= ( A and B ) or (( A or B) and Cin );
end process ;
Ch ! V khng c cc pht biu if, wait, loop nn cc tn hiu vo phi
thuc danh sch sensitivity list .
3.11. Cc thit b logic c bn.
3.11.1. Cc b cht.
Cc flip - flop v cc b cht l hai thit b nh mt bit thng hay c s
dng nht trong cc mch s. Mt Flip - Flop chnh l mt thit b nh c khi
to bi kch thch ca sn tn hiu, cn b cht l mt thit b nh cm nhn
chuyn mc ca tn hiu. Ni chung cc b cht chng c tng hp t cc biu
thc iu kin khng hon ton r rng trong vic m t mch logic t hp. Tt c
cc tn hiu hoc cc bin m khng c iu khin di tt c cc iu kin u
tr thnh phn t cht.
Cc pht biu if and case c ch ra khng hon ton r rng u to ra cc
b cht.
V d di y pht biu IF khng gn mt gi tr cho tn hiu Data_out khi S
khng bng ' 1', v vy khi tng hp b tng hp s to ra mt b cht.

Signal S, Data_in, Data_out : bit; Data_In SET Data_out

process (S, Data_in) D Q
Begin
if ( S = '1' ) then
Data_out <= Data_in; S
end if;
end process ;
CLR
Q

trnh b cht nhm ta phi gn tt c cc gi tr ti tt c cc tn hiu di

tt c cc iu kin, thm vo pht biu else ca v d trc th b tng hp s tng
 145

hp nh mt cng AND. xem v d di y:

Signal S, Data_in, Data_out : bit;
Data_In
process (S, Data_in) Data_out
Begin
if ( S = '1' ) then
Data_out <= Data_in; S
else
Data_out <= ' 0 ';
end if;
end process ;

Chng ta c th ch ra mt b cht vi ng reset khng ng b hoc cc

ng preset khng ng b nh sau:
Signal S, RST, Data_in, Data_out : bit;
Data_In SET Data_out
process (S, RST, Data_in) D Q
Begin
if ( RST = '1' ) then
Data_out <= ' 0 ';
elsif ( S = ' 1 ' ) then S
Data_out <= Data_in; en Q
CLR
end if;
end process ;

RST

Thay v ng Data_out c gn bng ' 0 ', chng ta c th gn '1' cho ng

Preset khng ng b.
3.11.2. Cc FLIP - FLOP.
Mt process vi cc pht biu if trn sn chuyn tn hiu hoc cc pht biu
wait trn s kin ca tn hiu c gi l mt qu trnh thc hin theo nhp ng h.
Mt Flip - Flop s oc to ra nu c c mt kch thch bi mt sn tn hiu, hn
na nu php gn tn hiu c thc hin trn vic kch thch chuyn mc ca mt
tn hiu khc.
V d :

Signal CLK, Data_in, Data_out : bit;

Data_In SET Data_out
process (CLK) D Q
Begin
if ( CLK'event and CLK = '1' ) then
Data_out <= Data_in;
end if; CLK
end process ; CLR
Q
 146

3.11.3. Cc ng tn hiu SET v RESET ng b.

Vic thit lp cc u vo (SET) v reset cc u ra ng b ca Flip - Flop
cng vi hot ng ca h thng ng h, ngoi cc khong thi gian khc cc tn
hiu ny khng c xem xt, iu ny c thc hin bi phn t nh.
Signal CLK, S_RST, Data_in, Data_out : bit;
process (CLK) Data_In
Begin SET Data_out
if ( CLK'event and CLK='1' ) then ' 0' MUX D Q
if (S_RST ='1') then
Data_out <= ' 0 ';
S_RST
else
Data_out <=Data_in; CLK
end if; CLR
Q
end if;
end process ;

3.11.4. Cc ng tn hiu SET v RESET khng ng b.

Signal CLK, A_RST, Data_in, Data_out : bit;
Data_In SET Data_out
process (CLK, A_RST) D Q
Begin
if ( A_RST = '0' ) then CLK
Data_out <= ' 0 ';

elsif ( CLK'event and CLK = ' 1 ' ) then Q

Data_out <= Data_in; CLR
end if;
end process ;
A_RST

Cc ng SET v RESET ca Flip - Flop hot ng c lp vi ng Clock.

3.11.5. Cc mch RTL t hp v ng b.
Chng ta c th chia cc pht biu ca mt process RTL thnh vi mch t hp
v vi mch ng b.
Phn mch ng b dng m t cc mch con m cc hot ng hnh vi
ca chng ch c c nh lng khi c chuyn mc ca tn hiu.
Phn mch t hp dng m t cc mch con m hot ng hnh vi ca
chng s c nh lng bt c khi no c s thay i ca tn hiu thuc sensitivity
list . Tt c cc tn hiu c tham chiu trong phn mch t hp cn phi thuc
trong danh sch sensitivity list . Xem v d sau:
 147

PB Q1
Q2
CLK FF FF

PB.Pulse

Entity PULSER is
port ( CLK, PB : in bit;
PB_PULSER : out bit );
end PULSER;
architecture BHV of PULSER is
signal Q1, Q2 : bit;
begin
process ( CLK, Q1, Q2 )
begin
if ( CLK'event and CLK = ' 1' ) then
Q1 <= PB;
Q2 <= Q1;
end if;
PB_PULSE <= ( not Q1 ) nor Q2;
end process ;
end BHV;
3.11.6. Cc thanh ghi.
C rt nhiu kiu thanh ghi m chng c s dng trong mt mch. V d
sau y s ch ra mt thanh ghi bn bit m chng c t trc khng ng b v
tr " 1100 ".
 148

Dout (3) Dout (2) Dout (1) Dout (0)

Q Q Q Q

S S R R
D D D D
CLK

ASYNC

Din (3) Din (2) Din (1) Din (0)

signal CLK, ASYNC : Bit;

signal Din, Dout : Bit_vector ( 3 downto 0 );
process ( CLK, ASYNC )
begin
if (ASYNC = '1' ) then
Dout <= " 1100 ";
elsif ( CLK'event and CLK = '1' ) then
Dout <= Din;
end if;
end process ;
3.11.7. Thanh ghi dch.
Mt thanh ghi c kh nng dch cc bit thng tin hoc sang phi hoc sang tri
c gi l mt thanh ghi dch. Cu hnh logic ca thanh ghi bao gm mt lot cc
Flip - Flop c ni tng vi nhau, u ra ca Flip - Flop ny c ni vo u vo
ca Flip - Flop kia. Tt c cc Flip - Flop u nhn xung ng h chung nn n c
th lm cho d liu dch t trng thi ny sang trng thi tip theo.
Xt v d v thanh ghi dch 4 bt sau:
signal CLK, Din, Dout : Bit ;
process (CLK)
variable REG : bit_vector ( 3 down to 0 );
begin
if ( CLK'event and CLK = '1' ) then
 149

REG : = Din & REG ( 3 downto 1);

end if;
Dout <= REG (0);
end process ;
Cu hnh ca chng nh sau:

Din Dout
D Q D Q D Q D Q
FF FF FF FF

CLK

3.11.8. Cc b m khng ng b.
B m khng ng b l b m m trng thi ca n thay i khng b iu
khin bi cc xung ng b ng h.
Cch m t b m ny nh sau:
Count (0) Count (1) Count (2) Count (3)

1 Q 1 1 1
T T Q T Q T Q
CLK FF FF FF FF

RESET

signal CLK, RESET : Bit;

signal COUNT : Bit_vector ( 3 downto 0 );
process ( CLK, COUNT, RESET )
begin
if RESET = '1' then COUNT <= "0000";
else
if (CLK' event and CLK = '1' ) then
COUNT (0) <= not COUNT (0);
end if;
if (COUNT(0)' event and COUNT(0) = '1' ) then
COUNT (1) <= not COUNT (1);
end if;

if (COUNT(1)' event and COUNT(1) = '1' ) then

 150

COUNT (2) <= not COUNT (2);

end if;

if (COUNT(2)' event and COUNT(2) = '1' ) then

COUNT (3) <= not COUNT (3);
end if;
end if;
end process ;

3.11.9. Cc b m ng b.
Nu tt c cc Flip - Flop ca b m c iu khin bi tn hiu clock
chung th chng c gi l b m ng b.
Cch vit chng nh sau:
signal CLK, RESET, load, Count, Updown : Bit;
signal Datain : integer range 0 to 15;
signal Reg : integer range 0 to 15: = 0;
process ( CLK, RESET )
begin
if RESET = '1' then Reg <= 0;
elsif ( CLK'event and CLK = '1' ) then

if ( Load = ' 1' ) then

Reg <= Datain;
else

if (Cout = '1' ) then

if Updown = '1' then
Reg <= ( Reg +1) mod 16;
else
Reg <= ( Reg -1 ) mod 16;
end if;
end if;
end if;
end if;
end process ;

3.11.20. Cc b m ba trng thi.

Bn cnh cc s 0 v 1, cn mt tn hiu th ba trong h thng s : l trng
thi tr khng cao ( Z ).
Trong cc kiu tin nh ngha ca cc ng gi chun khng c kiu no m
 151

t gi tr ca tr khng cao, v vy ta cn s dng kiu STD_LOGIC m t b

m ny.

Library IEEE; OE
use IEEE.STD_LOGIC_1164. all;

architecture IMP of TRI_STATE is

Signal Din, Dout, OE : STD_LOGIC;
Begin
process (OE, Din) Din Dout
Begin
if ( OE = '0' ) then
Dout <= ' Z ';
else
Dout <= Din;
end if;
end process ;

3.11.21.M t Bus.
Mt h thng Bus c th c xy dng vi cc cng ba trng thi thay v cc
cng multiplexers.
Ngi thit k phi m bo khng c nhiu hn mt b m trng thi kch
hot ti bt k thi im no. Cc b m kt ni cn phi c iu khin v vy
ch c b m ba trng thi truy cp ng Bus trong khi cc b m khc duy tr
trng thi tr khng cao.
Thng thng cc php gn tn hiu tc th, chng hn nh cc ng Bus
trong v d di y khng c php mc mt kin trc. Tuy nhin cc kiu
d liu STD_LOGIC v STD_LOGIC_VECTOR c th c nhiu ng iu khin.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity BUS is
port (S : in STD_LOGIC_VECTOR ( 1 downto 0 );
OE : buffer STD_LOGIC_VECTOR ( 3 downto 0 );
R0, R1, R2, R3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
BusLine : out STD_LOGIC_VECTOR ( 7 downto 0 ) );
end BUS ;
 152

architecture IMP of BUS is

Begin
Process (S)
Begin
Case (S) is
when " 00 " => OE <= "0001";
when " 01 " => OE <= "0010";
when " 10 " => OE <= "0100";
when " 11 " => OE <= "1000";
when others => null;
end Case;
end Process ;
BusLine <= R0 when OE (0) = ' 1' else "ZZZZZZZZ";
BusLine <= R0 when OE (1) = ' 1' else "ZZZZZZZZ";
BusLine <= R0 when OE (2) = ' 1' else "ZZZZZZZZ";
BusLine <= R0 when OE (3) = ' 1' else "ZZZZZZZZ";
end IMP;

Bus Line

OE (0) OE (1) OE (2) OE (3)

0
S (0) 2 to 4
1
Decoder
S (1)
2

3
R0 R1 R2 R3

Cu trc ng Bus tm bit

 153

Chng IV
Thit k b iu khin ng c bc
4.1. Gii thiu tm tt
Vic ng dng iu khin cc m t bc, thng thng c kt hp vi cc
b vi x l to ra mt kh nng iu khin v tr vi chnh xc cao. Motor
bc l thit b m n c th quay vi mt s chnh xc trn mi bc. Cc loi
motor bc in hnh thng quay vi gc quay l 150 hoc 7.50 trn mt bc,
thng th motor c ch ra s bc cn thit quay ht mt vng 3600 ( Vi
motor bc quay 150 trn mt bc s quay 24 bc trong mt vng). Vic iu
khin ng c bc chnh l iu khin vic cung cp in p trn cc cun dy ca
chng. chng ny tc gi xin trnh by mt v d n gin s dng CPLD, FPGA
v gii thiu b vi x l thng dng iu khin ng c bc vi bn cun dy
pha. V d ny l mt v d n gin nhm lm quen v hiu cch lp trnh trn
cu trc cu CPLD v FPGA ch khng a vo ng dng no c. Tuy nhin nu
mun pht trin v d ny thnh ng dng th vic trin khai cng rt d dng, v cc
bc c bn ca thit k s c tin hnh theo trnh t, v ch thm mt s thit b
n gin khc nh Encoder hay cc mt quang l c th c mt vng iu khin kn
i vi v d ny .
4.2.Thit k b iu khin ng c bc
4.2.1. iu khin ng c bc s dng b vi iu khin 89C51 truyn
thng .
iu khin ng c bc, c ngha l ta phi cung cp mt lot cc in p
vo bn cun ca motor. Cc cun s c cp nng lng motor quay c mt
bc. Cc mu cp nng lng cho cc cun cn phi c cung cp chnh xc. Cc
mu ny s c thay i ph thuc vo ch s dng vi motor. Vi cc ch
thng thng cho cc ng dng c m men quay thp, thng c s dng ch
iu khin na bc, c ngha l vi motor c phn gii 24 bc trong mt
vng quay th s quay 48 bc trong mt vng quay. S in hnh iu khin
mt ng c bc c s nh hnh 4.1. y l s c tc gi s dng trong
 154

thc t iu khin vi cc ng dng c m men quay ca motor thp . S dng

bng MosFet iu khin , v loi ny thng thng iu khin bng p.

VCC VCC
VCC

IRF 630 IRF 630

Bit0
VCC
Bit1

Bit2 VCC
VCC

Bit3 M

IRF 630 IRF 630

Hnh 4.1. S iu khin Motor bc, phn cng sut

Gi s b vi x l dng bn cng to ra mu bit (Bit 0, Bit 1, Bit 2, Bit 3)
iu khin ng c quay, mu bit iu khin ng c quay na bc c ch ra nh
bng 4.1:
Bng 4.1. Mu bit iu khin na bc
Step Bit 3 Bit 2 Bit 1 Bit 0
1 1 0 1 0
2 1 0 0 0
3 1 0 0 1
4 0 0 0 1
5 0 1 0 1
6 0 1 0 0
7 0 1 1 0
8 0 0 1 0
Vi cc ng dng c m men quay ln mu bc thng c s dng ch ra
bng 4.2.
 155

Bng 4.2. Mu bit iu khin c bc:

Step Bit 3 Bit 2 Bit 1 Bit 0
1 1 0 1 0
2 1 0 0 1
3 0 1 0 1
4 0 1 1 0
iu khin motor bc, b vi x l cn phi a ra cc mu bit tun t nh
hai bng va nu. o chiu quay ca ng c phi thc hin to mu bit tun t
theo th t ngc li ca cc bc. Lu , sc qun tnh ca ng c cn c mt
gi chm nht nh (thng thng khong t 5 n 15 ms) gia mi bc.
Di y xin gii thiu chng trnh c vit bng ngn ng C v np cho
chip vi iu khin h 89C51 hoc 89C2051 dng bn dng song song ca cng P1.
Nu dng thch anh khc th phi tnh gi tr np cho TH0 v TL0 khc,
chng trnh sau iu khin cho motor quay 30 bc lin tc sau o chiu quay.
y l chng trnh v d dng tham kho trc khi bc sang thc hin trn
CPLD v FPGA.
#include <c:\keil\c51\inc\reg51.h>
#include <c:\Keil\c51\inc\absacc.h>
void time()
{
TH0=0x9E; /* Thch anh 6Mhz*/
TL0=0x58; /* Np b m gi chm 50 ms */
TF0=0;
TR0=1;
while (TF0==0);
TR0=0;
}
/*-------------------------------------------------------------------------------*/
unsigned char steptab[] = {0x0a, 0x08, 0x09, 0x01, 0x05, 0x04, 0x06, 0x02};
//unsigned char steptab[] = {0x0a,0x09,0x05,0x06};
main()
 156

{
unsigned char ptr =0;
unsigned char cntr;
bit DFLAG;
TMOD=0x21;
DFLAG=0;
while(1)
{
for (cntr=0;cntr<30;cntr++)
{
P1=steptab[ptr&0x7];
time();
if (DFLAG==0)
ptr++;
else
ptr--;
}
DFLAG=!(DFLAG);
}
}
c gi chm gia cc bc, phi to b dm gi chm 50 ms vi thch
anh 6 MHz th phi np 9E58H vo thanh ghi TH0 v TL0.
4.2.2 iu khin ng c bc s dng CPLD XC9572XL
Mc ny s thit k b iu khin ng c bc vi bn phm gt a vo
CPLD iu khin ng c bc vi cc chc nng sau:
- SW1 : Dng khi ng v dng ng c . ( Cng tc Start/Stop)
- SW2 : Dng o chiu quay ca ng c . ( Cng tc Dir)
- SW3: Dng tng gim tc ng c. ( Tng, gim tc ng c Inc/Dec)
- SW4 : Dng Reset h thng .
1. S khi ca h thng :
thit k mt chng trnh trong CPLD, thng thng ta phi v s khi,
 157

hoc m t k hn dng m t my trng thi, sau in cc tn hiu vo ra.Vi

thit k ny, cn phi thit k ba khi trong CPLD, sau tng hp chng v a
vo mt thit k m c cha ba khi ny.
Trc tin khi x l phm v to tn hiu iu khin bn trong phi lun qut
phm, nhn bit tn hiu iu khin, sau ra lnh cho khi to bc xut ra
cc mu bc ( Xem hnh 4.2 ).
Khi to mu bc s nhn tn hiu t b to xung Clock lm Clock ca
mnh, ph thuc vo tn hiu iu khin ca khi iu khin a sang, b to Clock
s to Clock cho khi to bc, t s iu khin c tc ca ng c nhanh
hay chm.
Khi to mu bc c thc hin ph thuc vo khi to Clock a sang, v
th cc bc tun t c a ra theo tn hiu Clock ny.
Do y s dng loi XC9572XL 3.3V nn mch u ra ta phi ghp opto
cch ly trnh hng vi mch.

CPLD XC9572

Khi X L Tn hiu
iu khin Cc mu bit
Phm v To Khi To Cc
Khi Cng Sut
Tn Hiu iu Xung Ra Theo
IRF 630 M
Khin Mu Bc

Tn hiu iu khin
Clock

Clock h thng 8 MHz

Khi Phm Khi To Xung
Chc Nng Clock

Hnh 4.2. S khi b iu khin ng c t bn phm

s dng CPLD XC9572XL
2. To thit k:
a. Thit k Modul to mu bc: Trc tin ta i vit chng trnh cho Modul
to mu bc trc, xy dng c khi ny ta s dng m t FSM ( C th dng
 158

chng trnh StateCAD hoc vit trc tip bng VHDL). y tc gi xin gii thiu
chng trnh c vit bng VHDL. S m t trng thi ca modul to bc c
dng nh sau:
RESET

E = 0 & DIR = 0
E =1 E =1
Step_0 Step_1
E = 0 & DIR = 1

E = 0 & DIR = 0 E = 0 & DIR = 1 E = 0 & DIR = 1 E = 0 & DIR = 0

E = 0 & DIR = 1
E =1 E =1
Step_3 Step_2
E = 0 & DIR = 0

Hnh 4.3. S m t my trng thi ca Modul SecGenerator

Cc mu bc s l bn bc hoc 8 bc nh sau:
-- Full Step Table : ( x"A", x"9" , x"5",x"6" )
-- Half Step Table : (x"A",x"8",x"9",x"1",x"5",x"4",x"6",x"2").
Vi s trn ta thy, motor quay bn bc theo mt chiu nht nh, ta
phi to tn hiu E = 0, v Dir = 0 a vo khi ny.
Cn mun quay theo chiu ngc li ta phi cho E = 0 v Dir = 1.
Trong chng trnh Project Navigator ta to mt modul mi vi tn l
SecGenerator.vhd v khai bo cc u vo u ra, chng trnh c vit di
dng VHDL ( Xem phn ph lc1, file SecGenerator.vhd ).
Sau khi vit xong tin hnh kim tra c php v m phng. To file m phng
vi tn l Sec_tb.tbw v to biu kim tra nh hnh 4.4.

Hnh 4.4. To biu kim tra

 159

Khi m phng dng sng u ra c dng sau:

Hnh 4.5. Dng sng ra ca modul SecGenerator

Nh chng ta thy cc mu bc c a ra u ra vi tn sec nh hnh 4.5.
Nh vy modul to mu bc hon ton c m phng, hn na n cng
c kim nghim v chy th trong mch thc t (Xem hnh 4.25 v hnh 4.26).
b. Thit k Modul to xung Clock :
Vic modul to mu bc s a ra cc bc nhanh hay chm l do khi to
xung Clock ny a sang. Trong phn mm Project Navigator to modul mi vi
tn Clk_Generator.vhd. Lu thut ton ca Modul ny nh hnh 4.6.
Xem file Clk_Generator.vhd trong ph lc1. Tip theo ta i kim tra c php
ca modul ny v i m phng.
File m phng h thng c tn l Clk_tb.twb, kt qu m phng s thu c
v c dng nh hnh 4.7.
 160

Init
COUNT 10M = 0, Clk_1ms = 0,
COUNT_xms = 0, Clk_Out =0

Yes
RESET = 1 ?

No

No
Clk_1ms?

No
Clk In ?
Yes

Yes
COUNT_xms = COUNT_xms + 1

COUNT 10M = COUNT 10M + 1

No
COUNT_xms = DIV ?

No
COUNT 10M = 4000 ? Yes

COUNT_xms = 0
Yes Clk_Out = Not (Clk_Out)

COUNT 10M = 0
Clk_1ms = Not (Clk_1ms)

Hnh 4.6. Lu thut ton ca Modul Clk_Generator

Hnh 4.7. Biu dng sng u ra ca Modul Clock

Nh trn biu ta thy dng sng u ra ca tn hiu Clk_out thay i ph
 161

thuc vo tn hiu Div a vo u vo. Nh c tn hiu ny thay i m motor s

xut ra cc mu bc nhanh hay chm.
c. Thit k Modul qut phm v to lnh iu khin:
Nh gii thiu phn trn, cc phm s c cc chc nng nh Reset,
Inc/Dec, Cnt_Dir, Start/Stop. Xong v thit k phm theo kiu phm gt nn ch cn
kim tra bn phm.
Khi bt ngun, chng trnh phi kim tra cc phm ny lin tc a ra cc
lnh iu khin . Cc lnh iu khin Motor bao gm :
- Tn hiu Reset : Reset h thng.
- Tn hiu Start/Stop : Cho php hay khng cho php h thng hot ng.
- Tn hiu Inc : Tng hay gim tc ng c.
- Tn hiu Dir : Dng o chiu ng c.
Lu thut ton ca Modul ny th hin hnh 4.8. Xem chng trnh phn
ph lc 1, file Inc_Dec.vhd. By gi ta i m phng modul ny.
Tng t nh trn, chy file Inc_Dec_tb.tbw v biu m phng s thu c
nh hnh 4.9.

Init
Dout = "000", E =1, Dir =1

Yes
Reset = 1

No

No No
No Inc = 0 ? Dout =Dout - 1
Cnt_Dir = 0 ? Dir =1
Start = 0 ? E=1

Yes Yes
Yes
Dir = 0 Dout =Dout +1
E=0

Hnh 4.8. Lu thut ton Modul qut phm chc nng, Inc_Dec.vhd
 162

Hnh 4.9. Dng sng u ra ca Modul iu khin v qut phm

Nh biu dng sng ra ta thy s ph thuc vo phm Inc c gt v
khng hay mt th d liu Dout a ra tng ln hay gim i. Hoc khi o chiu cc
bt s to ra theo th t ngc li trong bng.
d. Thit k Modul tng th : Vic thit k Modul ny ch n thun l ghp
cc modul thit k li vi nhau, hay th hin chng trong mt modul lp trn
(Xem chng trnh trong File Top_Step.vhd trong phn ph lc 1), v th trong
chng trnh Project Navgator khi chy chng trnh ECS s cho ta mt khi chc
nng kn ch c u vo v ra nh hnh 4.10.

Hnh 4.10 . S tng th ca Modul iu khin Motor bc

khi chy chng trnh ECS trong Project Navigator
 163

Modul ny s c bn u vo phm ( Inc , Start , Reset, Cnt_Dir ), mt ng

Clock 8MHz u vo, clock ca h thng. Ba u ra bao gm mt Bus u ra bn
bit dng to mu bc cho Motor v hai u ra tn hiu Led ch th. S gn
chn ngi dng c thc hin trong chng trnh PACE nh sau:

Ton b thit k ny c dch, np vo trong CPLD XC9572XL thng qua

cp JTAG v cho chy th trn mch thc t. Cc modul chng trnh c gii
thiu trong ph lc 1. mc ny tc gi xin khng gii thiu s mch in phn
iu khin v mch in phn cng sut v hai s ny l hai s dng n gin.
4.2.3 iu khin motor bc ghp ni vi my tnh PC s dng Board
mch Spartan-3 FPGA
Phn ny l phn thit k nng cao v s dng vi mch chnh l XC3S200
FPGA. Vic ghp ni vi my tnh i hi chng trnh phi c thit k mt b
UART nhn d liu t my tnh PC. Thng thng khi thit k phn cng, ta
thng phi dng mt vi mch chuyn i mc Max 232 hoc Max3232, cc vi
mch UART 1640 hoc 1650. Vi nhng ngi lp trnh vi iu khin th cng vic
ghp ni vi my tnh PC l cng vic kh n gin, v trong cc b vi iu khin c
sn mt b UART. Khi s dng CPLD hoc FPGA, chng ta phi thc hin vit
chng trnh thc hin cc chc nng ca vi mch UART ny. Ni nh vy vic s
dng CPLD v FPGA phc tp hn?. ng vy, khi mi bt u lm quen vi CPLD
v FPGA bt u t u lun l mt cu hi kh. thc hin c cng phi c
 164

mt thi gian cn thit c, tham kho, tm ti. Xong khi thc hin c trn
n, th mi thy c n rt u vit, bi l chng ta c th to chng trnh ca
chng ta vit ra thnh mt core (li), m khi c ln no ta c th s dng li
chng mt cch d dng. V mt iu quan trng na l chng ta a mt vi
mch UART vo trong mt chp n m trong chip ny c th c tch hp cng
nhiu cc vi mch khc na thc hin mt h thng phc tp ch trong mt chip.
y mi ch l mt ng dng s khai ban u, vi FPGA n cn c mt chng di
cc ti nguyn cha c khai thc ht, bn c th to RAM trong chng, to mt
b vi x l trong chng hay bin chng thnh mt b DSP, hay cc b lc s chuyn
dng, b x l cc thut ton x l nh ... Vi v d nh b ny tc gi cng xin
c trnh by, v d sao n cng l bc i ban u trn nn ca cc chp mt
cao tc ln ny. Cng vi v d gii thiu, by gi ta khng iu khin bng
phm na m ta s dng chng trnh iu khin. Chng trnh ny c vit
bng Visual Basic iu khin motor bng my tnh thng qua cng COM1. Trong
chip Spartan s c vit mt b UART nhn d liu t my tnh PC a sang.
1. Chng trnh iu khin giao din phn mm Visual Basic
Mc ch ca chng ta l i thit k b UART kt hp vi modul iu khin
ng c bc nh gii thiu. Chnh v l do ny chng trnh vit bng Visual
Basic c vit n gin vi cc nt n thay cho phm trong v d trc. Nu
thm mt bc na l chng ta c th ly d liu t mch phn hi ca ng c
x l trong my tnh. Tuy nhin lun vn ny tc gi ch cp n mt mc ch
c bn v vic ghp ni my tnh vi FPGA thng qua mt b UART c vit
trong FPGA. Trn form chng trnh, khi ta kch chut vo cc nt nhn ny th
chng trnh s truyn cc Byte d liu qua cng COM 1 vi khun mu truyn t
sn l "9600,N,8,1". (Chng trnh ny c th nghim ghp ni vi b vi x l
89C51 v FPGA Spartan3 XC3S200 5ft256). Mi ln kch chut l mt ln
chng trnh truyn mt Byte d liu, v th b UART c vit trong bo mch
Spartan-3 s cng phi vit vi tc Baudrate l 9600 vi khun mu truyn nhn
nh trn. Chng trnh iu khin ny c vit di dng mt Form n vi su
nt nhn nh sau: - Start : Khi ng Motor.
 165

- Left, Right : Dng o chiu ng c

- Nt Slow/Fast : Dng tng gim tc ng c.

Hnh 4.11. Giao din khi iu khin Motor

M chng trnh c vit nh sau:
Option Explicit
Dim command As Byte
Dim FLAG As Boolean
Private Sub cmdDown_Click()
If FLAG = True Then
command = &H44 'character D
MSComm1.Output = Chr(command)
Else
MsgBox ("Start Command Button haven't been pressed")
End If
End Sub
------------------------------------------------------------------------------------
Private Sub cmdLeft_Click()
If FLAG = True Then
command = &H4C 'character L
MSComm1.Output = Chr(command)
 166

Else
MsgBox ("Start Command Button haven't been pressed")
End If
End Sub
------------------------------------------------------------------------------------
Private Sub cmdRight_Click()
If FLAG = True Then
command = &H52 'chatacter R
MSComm1.Output = Chr(command)
Else
MsgBox ("Start Command Button haven't been pressed")
End If
End Sub
------------------------------------------------------------------------------------
Private Sub CmdStart_Click()
FLAG = True
command = &H53 'character S
MSComm1.Output = Chr(command)
End Sub
------------------------------------------------------------------------------------
Private Sub cmdSTOP_Click()
FLAG = False
command = &H42 'character B = stop
MSComm1.Output = Chr(command)
End Sub
------------------------------------------------------------------------------------
Private Sub cmdUp_Click()
If FLAG = True Then
command = &H55 ' character U
MSComm1.Output = Chr(command)
Else
MsgBox ("Start Command Button haven't been pressed")
 167

End If
End Sub
Private Sub Form_Load()
FLAG = False
MSComm1.CommPort = 1
MSComm1.Settings = "9600,N,8,1"
MSComm1.PortOpen = True
End Sub
------------------------------------------------------------------------------------
Private Sub Form_Unload(Cancel As Integer)
MSComm1.PortOpen = False
End Sub
2. Thit k b UART v ghp ni PC :
thit k Modul UART chng ta phi thit k mt Modul chnh v hai
modul con vi cc tn file nh sau (S c gii thiu phn ph lc2 ):
- Modul UART.vhd : Modul chnh cha cc Modul thnh phn .
- Modul Rx.vhd : Modul dng lm b thu d liu khng ng b.
- Modul Tx.vhd: Modul dng thc hin b pht d liu khng ng b.
- Modul Counter.vhd : Dng to ng h Baudrate, khi thit lp tc
Baudrate vi my tnh PC.
- Modul Synchroniser.vhd dng ng b Clock.
thit k mt Modul UART v to chng thnh Core rt phc tp, cn phi
hiu r hot ng chc nng ca mt b UART v cch to core.
y n gin trong vic vit chng trnh, b uart ny s lm vic t ng
thu pht d liu ni tip, khng thit k cc ng dn bt tay nh CTS, RTS, DTR,
DSR, khng c FIFO .
Vi khun dng d liu ca b truyn s c truyn di dng sau:
S tart d0 d1 d2 d3 d4 d5 d6 d7 S top S tart

Hnh 4.12 Khun dng d liu c truyn i

 168

Khun dng d liu ca b thu s c thu di ng sau:

S ta rt d0 d1

Hnh 4.13. Khun dng d liu c thu v

a. B m truyn d liu :
B truyn d liu s truyn nh sau:
u tin s h ng Start xung mc thp trong mt thi gian bng tc
Baud, sau s pht cc bit cn li. n bit Stop, n s nng ng ny ln mc
cao.Vi b thu d liu, s d ng Bit Start bng cch d sn xung ca bit ny,
sau m clock n gia bt Start th ghi li mt bit. Tip tc m Clock n gia
chu k ca bit d0 th ghi li bit ny, tip tc m cho n bt Stop sau ghp chng
li thnh mt byte d liu thu c.
B UART s c s khi chc nng nh hnh 4.14:

RXD
UART_RX

BAUD
RATE
TIMING
TXD
UART_TX

Hnh 4.14. S khi chc nng tng qut ca b UART

Nh vy s khi tng qut ca b iu khin Motor bng my tnh s nh
sau:

Modul IO XC3s200

pin_rs232_td Led
Start/Stop

Cnt_Dir
Sec [3:0]
pin_rs232_rd Modul UART Modul Step_Motor
Inc/Dec Led1

Clock Reset

Hnh 4.15. S tng quan Modul iu khin ghp ni vi my tnh

 169

Vi Modul Step_Motor nh c gii thiu trn, y ta ch vic thu d

liu, sau x l ri a cc ng iu khin nh trn hnh sang khi Step_motor..
Cng vic tip theo l vit chng trnh v m phng cc b Tx v Rx, vic x l
cc tn hiu iu khin ch vit thm mt Process trong modul I/O l c th chy
c. Chng trnh c thc hin vi ngn ng VHDL, sau s c ghp vi
modul iu khin motor bng phm nh trnh by. Tuy nhin cc ng iu
khin trong modul IO.vhd (ph lc 2) cn phi l b cht, c th chng trnh dich
s t to b cht cho cc tn hiu iu khin ny trong FPGA, xong cn phi xem
thng bo sau khi dch chng trnh.

Init
TxD= 1, Bitpos=0, TbufL =0

Yes
Reset = 1

No

No
Enable= 1 ?

Yes LoadS=1?
No
Yes

No No No
BitPos=0? BitPos=1? BitPos=10
Yes Yes
Tbuff=DataIn
TbufL = 1,
Yes Busy = TbufL or LoadA
TxD=1 TxD=0

TBufL=1?

Yes

Treg = Tbuff
TxD=Treg(BitPos) TxD=Treg(BitPos)
BitPos = BitPos+1
BitPos = BitPos+1 BitPos = 0
TBufL= 0.

Hnh 4.16. Lu thut ton ca b m TxD

S ca b m pht c u vo v ra khi chy chng trnh ECS nh hnh
4.17.
 170

Hnh 4.17. S vo ra ca b m pht

Sau khi chy chng trnh m phng ta thu c tn hiu trn ng Tx nh
hnh di y. Gi s ta np s 04 Hex truyn i, khi trn ng Tx c dng
xung nh trong biu hnh 4.18:

Hnh 4.18. Biu m phng b m pht

b. B m thu d liu: Tng t, b m thu c lu thut ton nh hnh
4.19
 171

Init
RRegL = 0, Bitpos = 0

Yes
Reset = 1

No

No
ReadA =1 ? RxAv = 1
No
Enable= 1 ?
Yes

RxAv = 0
Yes

No No
BitPos=0? BitPos= 2 - 9 No
No SampleCount = 3 ?
BitPos=10
Yes
Yes
No Yes
Yes
RxD = 0 ? No
SampleCount =1 &
BitPos >= 2? RReg = 1, Bitpos=0 SampleCount = 0
Yes
DataO = RReg
SampleCount = 0 No
Yes
Bitpos = 1 SampleCount = 3 ?
RRegL = 0
Yes SampleCount =
RReg (BitPos ) =RxD
SampleCount + 1
BitPos = 0 BitPos = BitPos+1

Hnh 4.19. Lu thut ton b m thu d liu

Trong chng trnh Project Navigator chy chng trnh ECS ta thu c s
khi vo ra ca b m thu nh hnh 4.20.

Hnh 4.20. S khi vo ra ca Modul b m thu Rx

Biu m phng ca b m thu sau khi cho u vo Rx s 06 Hex, chy
chng trnh ModelSim ta thu c cc tn hiu du ra Data[7:0] s 06 Hex nh
 172

biu di y:

Hnh 4.21. Biu sng u ra ca b m thu d liu Rx

( Xem chng trnh File Rx.vhd ph lc 2 )
By gi ch cn vit thm mt on Process x l cc Byte nhn t my tnh
sang a ra cc ng iu khin nh hnh 4.15. Trong file IO.vhd khai bo thm
mt s tn hiu ca Modul Top_Step (Add thm component Top_Step phn iu
khin bng phm gt nh gii thiu trn), thm on x l Process di y
(Xem chng trnh trong file IO.vhd ph lc 2):
-----------------------------------------------------
process (charBuf)
Begin
case charBuf is
when x"53" => -- Start
Start <= '0';
when x"42" => -- Stop
Start <= '1';
when x"4C" => -- Left
Cnt_Dir <= '1';
 173

when x"52" => -- Right

Cnt_Dir <= '0';
when x"55" => -- Up
Inc <= '0';
when x"44" => -- Down
Inc <='1' ;
when others =>
Start <= '1';
Cnt_Dir <= '1' ;
Inc <= '1';
end case;
end Process;
end arch;
Sau i tng hp v thc thi chng trnh, ta s thu c cc du tch mu
xanh, chng trnh Project Navigator s thng bo rng vic thc thi trn thit b
khng c li nh ( Hnh 4.22).

Hnh 4.22. Thc thi chng trnh trn Spartan-Xc3S200-5ft256

Thc hin gn chn trong chng trnh Xilinx PACE dng cho Board mch
Starter Kit Board Spartan-3 vi cc chn c gn nh hnh 4.23:
 174

Hnh 4.23. Ca s gn chn Spartan-Xc3S200-5ft256

Sau khi dch, chng trnh s to ra file IO.bit, khc vi CPLD, sau khi dch n
to ra file .Jed. Sau np chng trnh vi tool iMPACT tn file IO.bit vo thit b.
Chng trnh c chy th nghim b UART ghp ni my tnh thng qua phn
mm Hyper Terminal ca Windows, sau c np vo kt Spartan3Xc3s200-
5ft256 v chy th. Bc th nghim trn Hyper Terminal l bc nn lm trong
lp trnh ghp ni vi PC.

Hnh 4.24. Th nghim trn HyperTerminal

Ghp ni vi chng trnh Hyper Terminal, khi bn g bt k phm no trn
bn phm, b UART s t ng thu v truyn ngc tr li nh hnh 4.24.
 175

Nh vy ton b chng ny gii thiu vic thc hin iu khin Mtor vi

hai thit b ch khc nhau l CPLD v FPGA. V d ny c cho chy trn thc
t vi m t c chn l 7.50 bc, in p cp cho ng c l 5V, c th
nghim trn c hai board mch CPLD XC9572 v Spartan3-XC3s200 xem hnh 4.25
v hnh 4.26.
 176
Hnh 4.25. nh chp qu trnh th nghim trn FPGA Spartan3
 177
Hnh 4.26. nh chp qu trnh th nghim trn CPLD XC9572XL
 1

Ph lc chng trnh 1

Chng trnh iu khin m t s dng phm

thc hin trn CPLD XC9572XL

Cc file chng trnh:

1. Top_Step.vhd
2. Inc_Dec.vhd
3. Clk_Generator.vhd
4. SecGenerator.vhd
 2

---------------------------- Top_Step.vhd ---------------------------

--
-- ---------------------------------------------
--Author :PHAM TUAN HAI_ Lop Dieu Khien K15 --
--Project:Step_Motor_Controller using KeyPad --
--Modul :Top_Step.vhd --
-- ---------------------------------------------
------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Top_Step is
Port ( Clk,Reset,Inc,Start,Cnt_Dir : in std_logic;
Sec : out std_logic_vector(3 downto 0);
Led,Led1 : Out std_logic );
end Top_Step;
------------------------------------------------
architecture Behavioral of Top_Step is
------------------------------------------------
Component Clk_Generator
Port ( Clk,Reset : in std_logic;
Div : in std_logic_vector(2 downto 0);
Clk_Out : Buffer std_logic);
end Component Clk_Generator;
-----------------------------------------------------------
Component Inc_Dec
Port ( Clk, Reset,Inc,Start,Cnt_Dir :Std_logic;
E,Dir,Led,Led1 : Out Std_logic;
DOut : Buffer std_logic_vector(2 downto 0));
end Component Inc_Dec;
-----------------------------------------------------------
Component SecGenerator
Port ( Clk,Reset,E,Dir : in std_logic;
Sec : out std_logic_vector(3 downto 0));
end Component SecGenerator;
-----------------------------------------------------------
Signal E,Clk_Step : Std_Logic;
Signal SysDiv : Std_Logic_Vector(2 downto 0);
signal Dir : Std_logic;
--Signal Dec : Std_logic;
-----------------------------------------------------------
-------------------------------------------------------------
begin
X1: Inc_Dec port map ( Clk,Reset,Inc,Start,Cnt_Dir,E,Dir,Led,Led1,SysDiv);
X2: Clk_Generator port map ( Clk, Reset, SysDiv, Clk_Step );
X3: SecGenerator port map ( Clk_Step, Reset, E, Dir, Sec);
-----------------------------------------------------------
end Behavioral ;
--------------------------- Inc_Dec.vhd-------------------------------
--
-- ---------------------------------------------
--Author :PHAM TUAN HAI_ Lop Dieu Khien K15 --
--Project:Step_Motor_Controller using Key --
--Modul : Inc_Dec.vhd --
-- ---------------------------------------------
------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 3

entity Inc_Dec is
Port ( Clk, Reset,Inc,Start,Cnt_Dir :Std_logic;
E,Dir,Led,Led1 : Out Std_logic;
DOut : Buffer std_logic_vector(2 downto 0));
end Inc_Dec;
-----------------------------------------------------------
architecture Behavioral of Inc_Dec is
Signal Dec : Std_logic;
-----------------------------------------------------------
begin
Dec <= NOT (Inc);
-----------------------------------------------------------
Process(Reset,Clk,Start)
begin
if Reset = '1' then
E <= '1';
elsif Clk'event and Clk = '1' then
if Start = '0' then
E <= '0';
Led1 <= '0';
elsif Start = '1' then
E <='1';
Led1 <= '1';
end if;
end if;
End Process;
-----------------------------------------------------------
Process (Clk,Cnt_Dir)
Begin
if Cnt_Dir='0' then
Dir <= '1';
led <='0';
else
Dir <= '0';
led <= '1';
end if;
End process;
-----------------------------------------------------------
Process(Clk, Inc, Dec, Reset)
begin
If Reset = '1' then
DOut <= b"000";
elsif Clk'event and clk='1' then
If Inc = '0' then
if Dout = "100" then
Dout <= "000";
else
Dout <= Dout + 1;
end if;
elsif Dec = '0' then
if Dout = "000" then
Dout <= "100";
else
Dout <= Dout - 1;
end if;
else
Dout <= Dout;
end if;
end if;
end process;
end Behavioral;
--------------------------- Clk_Generator.vhd---------------------
-
 4

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Clk_Generator is
Port ( Clk,Reset : in std_logic;
Div : in std_logic_vector(2 downto 0);
Clk_Out : Buffer std_logic);
end Clk_Generator;

architecture Behavioral of Clk_Generator is

Signal Count_10MHz : Integer Range 0 to 8000;

Signal Count_xms : Integer Range 0 to 8;
Signal Clk_1ms : Std_Logic;
--signal Clk_Out :Std_logic;
begin
-------------------------------------
Process( Clk, Reset )
Begin
If Reset = '1' then
Count_10MHz <= 0;
Clk_1ms <= '0';
elsif Clk'event and Clk = '1' then
if Count_10MHz = 2 then
Count_10MHz <= 0;
Clk_1ms <= not(Clk_1ms);
else
Count_10MHz <= Count_10MHz + 1;
end if;
end if;
end Process;
---------------------------------------
Process( Count_xms,Clk_1ms, Reset, Div,Clk_Out )
Begin
If Reset = '1' then
Count_xms <= 0;
Clk_Out <= '0';
elsif Clk_1ms'event and Clk_1ms = '1' then
if Count_xms < DIV then
Count_xms <= Count_xms + 1;
else
Count_xms <= 0;
Clk_Out <= not(Clk_Out);
end if;
end if;
end Process;
end Behavioral;
----------------------------- SecGenerator.vhd---------------------
-
-- ---------------------------------------------
--Author :PHAM TUAN HAI_ Lop Dieu Khien K15 --
--Project:Step_Motor_Controller using KeyPad --
--Modul :SecGenetator.vhd --
-- ---------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SecGenerator is
Port ( Clk,Reset,E,Dir : in std_logic;
 5

Sec : out std_logic_vector(3 downto 0));

end SecGenerator;
-----------------------------------------------------------
architecture Behavioral of SecGenerator is
-- Full Step Table : ( x"A", x"9" , x"5",x"6" )
-- Half Step Table : (x"A",x"8",x"9",x"1",x"5",x"4",x"6",x"2")
Type States is (Step_0, Step_1, Step_2,
Step_3,Step_4,Step_5,Step_6,Step_7);
Signal Next_State, Current_State : States;
begin
----------------------
Process( Clk, Reset, E, Dir, Current_State )
Begin
if Reset = '1' then -- Reset ='1' key Pressed
Next_State <= Step_0;
Sec <= x"A";
elsif Clk'event and Clk = '1' and E = '0' then
Case Current_State is
When Step_0 =>
Sec <= x"A";
if DIR = '1' then
Next_State <= Step_1;
else
Next_State <= Step_7;
end if;
When Step_1 =>
Sec <= x"8";
if DIR = '1' then
Next_State <= Step_2;
Else
Next_State <= Step_0;
end if;
When Step_2 =>
Sec <= x"9";
if DIR = '1' then
Next_State <= Step_3;
Else
Next_State <= Step_1;
end if;
When Step_3 =>
Sec <= x"1";
if DIR = '1' then
Next_State <= Step_4;
Else
Next_State <= Step_2;
end if;
When Step_4 =>
Sec <= x"5";
if DIR = '1' then
Next_State <= Step_5;
Else
Next_State <= Step_3;
end if;
When Step_5 =>
Sec <= x"4";
if DIR = '1' then
Next_State <= Step_6;
Else
Next_State <= Step_4;
end if;
When Step_6 =>
Sec <= x"6";
if DIR = '1' then
Next_State <= Step_7;
 6

Else
Next_State <= Step_5;
end if;
When Step_7 =>
Sec <= x"2";
if DIR = '1' then
Next_State <= Step_0;
Else
Next_State <= Step_6;
end if;
When Others =>
Next_State <= Step_0;
end Case;
end if;
end Process;
-----------------------------------------------------------
Process(Clk)
Begin
if Clk'event and clk = '1' then
Current_State <= Next_State;
end if;
end process;
end Behavioral;
 7

Ph lc chng trnh 2

Chng trnh iu khin m t bc ghp ni PC

thc hin trn FPGA Spartan3-XC3S200-5ft256

Cc file chng trnh:

1. IO.vhd
2. UART.vhd
3. Rx.vhd
4. Tx.vhd
5. COUNTER.vhd
6. Synchroniser.vhd
V cc file ca Project Top_Step.vhd trong ph lc 1.
1. Top_Step.vhd
2. Inc_Dec.vhd
3. Clk_Generator.vhd
 8

4. SecGenerator.vhd

------------------------------------- IO.vhd----------------------------
---
------------------------------------------------
-- ---------------------------------------------
-- Author : PHAM TUAN HAI_ Lop Dieu Khien K15 --
-- Project RS232 CONNECTION --
-- ---------------------------------------------
------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity IO is
port( CLK : in std_logic;
Pushbtn : in std_logic;
rs232_rd: in std_logic;
rs232_td: out std_logic;
Led,Led1,pin_led: Out std_logic ;
Sec : out std_logic_vector(3 downto 0));
end IO;
-------------------------------------------------------
architecture arch of IO is
constant YES: std_logic := '1';
constant NO: std_logic := '0';
constant HI: std_logic := '1';
constant LO: std_logic := '0';
signal sysClk : std_logic;
signal sysReset : std_logic;
-- uart component
component uart
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130);
port(
CLK_I : in std_logic; -- clock
RST_I : in std_logic; -- Reset input
ADR_I : in std_logic_vector(1 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
DAT_O : out std_logic_vector(7 downto 0);
WE_I : in std_logic; -- Write Enable
 9

STB_I : in std_logic; -- Strobe

ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic;
IntRx_O : out std_logic;
BR_Clk_I : in std_logic;
TxD_PAD_O: out std_logic;
RxD_PAD_I: in std_logic);
end component;
---------------------------------------------------------------------
component Top_step
Port ( Clk,Reset,Inc,Start,Cnt_Dir : in std_logic;
Sec : out std_logic_vector(3 downto 0);
Led,Led1 : Out std_logic );
End component;
-----------------------------------------------------------
-----------------------------------------------------------
-- uart signals
signal uart_CLK_I : std_logic;
signal uart_RST_I : std_logic;
signal uart_ADR_I : std_logic_vector(1 downto 0);
signal uart_DAT_I : std_logic_vector(7 downto 0);
signal uart_DAT_O : std_logic_vector(7 downto 0);
signal uart_WE_I : std_logic;
signal uart_STB_I : std_logic;
signal uart_ACK_O : std_logic;
signal uart_IntTx_O : std_logic;
signal uart_IntRx_O : std_logic;
signal uart_BR_Clk_I : std_logic;
signal uart_TxD_PAD_O: std_logic;
signal uart_RxD_PAD_I: std_logic;

signal charBuf :std_logic_vector(7 downto 0);

signal Inc,Start,Cnt_Dir:std_logic;
signal Step_Clk : std_logic;
signal Step_Reset : std_logic;
signal charAvail :std_logic;
----------------------------------------------------------------------------
-----
BEGIN
sysClk <= CLK;
sysReset <= Pushbtn;
uart_ADR_I <= "00";
----------------------------------------------------------------------------
-----
--------------------------------------------
sysuart: uart generic map(BRDIVISOR => 1320)
port map(CLK_I => uart_CLK_I,
RST_I => uart_RST_I,
ADR_I => uart_ADR_I,
DAT_I => uart_DAT_I,
DAT_O => uart_DAT_O,
WE_I => uart_WE_I,
STB_I => uart_STB_I,
ACK_O => uart_ACK_O,
--process signals
IntTx_O => uart_IntTx_O,
IntRx_O => uart_IntRx_O,
BR_Clk_I => uart_BR_Clk_I,
TxD_PAD_O => uart_TxD_PAD_O,
RxD_PAD_I => uart_RxD_PAD_I );
----------------------------------------------------------
sysstep:Top_Step
port map (Step_Clk,Step_Reset,Inc,Start,Cnt_Dir,Sec,Led,Led1);
 10

----------------------------------------------------------
--uart port connections/conversions
uart_CLK_I <= sysClk;
uart_RST_I <= sysReset;
Step_Reset <= sysReset;
uart_BR_Clk_I <= sysClk;
Step_Clk <= sysClk;
rs232_td <= uart_TxD_PAD_O;
uart_RxD_PAD_I <= rs232_rd;
----------------------------------------------------------------------------
-----
----------------------------------------------------------------------------
-----
process(Pushbtn,CLK,uart_IntRx_O, uart_IntTx_O,uart_DAT_O,charBuf,charAvail)
begin
if Pushbtn = '1' then
charBuf <= "00000000";
charAvail <= NO;
uart_ACK_O <= '0' ;
pin_led <= '1';
elsif CLK'event and CLK = '1' then
if(uart_IntRx_O = HI) then
charBuf <= uart_DAT_O;
charAvail <= YES;
uart_WE_I <= LO;
uart_STB_I <= HI;
uart_ACK_O <= uart_STB_I;
pin_led <= '1';
elsif(uart_IntTx_O=HI) then
if( charAvail=YES ) then
uart_DAT_I <= charBuf;
charAvail <= NO;
uart_WE_I <= HI;
uart_STB_I <= HI;
uart_ACK_O <= uart_STB_I;
end if;
-- pin_led <= '0';
else
-- charBuf <= "00000000";
uart_STB_I <= LO;
uart_ACK_O <= uart_STB_I;
pin_led <= '0';
end if;
end if;
end process;
------------------------------------------------------
process (Pushbtn,charBuf,CLK)
Begin
if Pushbtn = '1' then
Start <= '1' ;
Cnt_Dir <= '1';
Inc <= '1';
elsif CLK'event and CLK = '1' then
case charBuf is
when x"53" => -- Start
Start <= '0';
when x"42" => -- Stop
Start <= '1';
when x"4C" => -- Left
Cnt_Dir <= '1';
when x"52" => -- Right
Cnt_Dir <= '0';
when x"55" => -- Up
Inc <= '0';
 11

when x"44" => -- Down

Inc <='1' ;
when others =>
Start <= '1';
Cnt_Dir <= '1' ;
Inc <= '1';
end case;
end if;
end Process;
end arch;

--------------------------------- UART.vhd-----------------------------
---
-------------------------------------------------------------
-- Title : UART ---
-- Project : UART ---
-- Clock : 50MHz Using Clock of Board XC3s200 ---
-- Author : Pham Tuan Hai_Lop Dieu Khien K15 ---
-------------------------------------------------------------
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity UART is
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130);
port (
CLK_I : in std_logic;
RST_I : in std_logic;
ADR_I : in std_logic_vector(1 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
DAT_O : out std_logic_vector(7 downto 0);
WE_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
-- process signals
-- Transmit interrupt: indicate waiting for Byte
IntTx_O : out std_logic;
IntRx_O : out std_logic;
BR_Clk_I : in std_logic;
TxD_PAD_O: out std_logic;
RxD_PAD_I: in std_logic);
end UART;
-- Architecture for UART for synthesis
architecture Behaviour of UART is
------------------------------------------------------------
component Counter
generic(COUNT: INTEGER range 0 to 65535);
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
O : out std_logic); -- Output
end component;
------------------------------------------------------------
component Rx
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
-- Async Read Received Byte . ReadA =1 then no thing to do, ReadA=0 => read
ReadA : in Std_logic;
RxD : in std_logic;
RxAv : out std_logic;
DataO : out std_logic_vector(7 downto 0));
 12

end component;
------------------------------------------------------------
component Tx
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
-- Asynchronous Load signal =1 then transfer Data in input to Buffer, BufL=1
LoadA : in std_logic;
TxD : out std_logic;
Busy : out std_logic;
DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component;
------------------------------------------------------------
-- Signals of uart
signal RxData : std_logic_vector(7 downto 0);
signal TxData : std_logic_vector(7 downto 0);
signal SReg : std_logic_vector(7 downto 0);
signal EnabRx : std_logic; -- Enable RX unit
signal EnabTx : std_logic; -- Enable TX unit
-- Data Received =1 Buffer contains a received byte ,=0 Buffer empty or idle
signal RxAv : std_logic;
-- Transmiter Busy =1 is Busy , =0 Accept a byte to transmit
signal TxBusy : std_logic;
signal ReadA : std_logic; -- Async Read receive buffer
signal LoadA : std_logic; -- Async Load transmit buffer
signal Sig0 : std_logic; -- gnd signal
signal Sig1 : std_logic; -- vcc signal
------------------------------------------------------------
BEGIN
sig0 <= '0';
sig1 <= '1';
----------------------------------------------------------------------------
---
Uart_Rxrate : Counter
generic map (COUNT => BRDIVISOR)
port map (BR_CLK_I, sig0, sig1, EnabRx);
----------------------------------------------------------------------------
--
Uart_Txrate : Counter
generic map (COUNT => 8)
port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
----------------------------------------------------------------------------
---
Uart_Tx : Tx
port map (BR_CLK_I, RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
Uart_Rx : Rx
port map (BR_CLK_I, RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
----------------------------------------------------------------------------
---
IntTx_O <= not TxBusy;
-- Flag signal TxBusy=1 Transmiter is Busy ,or IntTx_0 = 0 is Busy
IntRx_O <= RxAv;
-- RxAv =1 one Byte Received
-- RxAv =0 Receiver Buffer empty
SReg(0) <= not TxBusy;
SReg(1) <= RxAv;
SReg(7 downto 2) <= "000000";
----------------------------------------------------------------------------
---
-- Clocked on rising edge. Synchronous Reset RST_I
----------------------------------------------------------------------------
---
WBctrl : process(CLK_I, RST_I, STB_I, WE_I, ADR_I)
 13

variable StatM : std_logic_vector(4 downto 0);

begin
if Rising_Edge(CLK_I) then -- System Clock rising
if (RST_I = '1') then -- if no Reset
ReadA <= '0'; -- ReadA Signal =0
LoadA <= '0'; -- LoadA Signal =0
else -- When reset = 0 occured
-- Write Byte to Tx
if (STB_I = '1' and WE_I = '1' and ADR_I = "00") then
-- Get input connect to TxData input signal of Transmiter
TxData <= DAT_I;
-- Async transmit buffer Load signal , load data into Transmiter
LoadA <= '1';
else LoadA <= '0';
end if;
-- Read Byte from Rx
if (STB_I = '1' and WE_I = '0' and ADR_I = "00") then
-- DAT_O <= RxData; -- Out Data to Bus
-- Async receive buffer Read signal connects to ReadA input of Receiver
ReadA <= '1'; -- Signal is used to read buffer, ReadA=1 =>
Read
else ReadA <= '0';
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
---
ACK_O <= STB_I;
DAT_O <=
RxData when ADR_I = "00" else -- Read Byte from Rx
SReg when ADR_I = "01" else -- Read Status Reg
"00000000";
end Behaviour;
-------------------------------------- Rx.vhd---------------------------
--
-------------------------------------------------------------
-- Title : UART ---
-- Project : UART ---
-- Clock : 50MHz ---
-- Author : Pham Tuan Hai ---
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity Rx is
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
ReadA : in Std_logic;
RxD : in std_logic;
RxAv : out std_logic;
DataO : out std_logic_vector(7 downto 0));
end Rx;
----------------------------------------------------------------------------
---
architecture Behaviour of Rx is
signal RReg : std_logic_vector(7 downto 0);
signal RRegL: std_logic;
begin
------------------------- RxAv process----------------------------
RxAvProc : process(RRegL,Reset,ReadA)
 14

begin
if ReadA = '1' or Reset = '1' then
RxAv <= '0';
elsif Rising_Edge(RRegL) then
RxAv <= '1';
end if;
end process;
----------------------- Rx Process---------------------------------
RxProc : process(Clk,Reset,Enable,RxD,RReg)
variable BitPos : INTEGER range 0 to 10;
variable SampleCnt : INTEGER range 0 to 3;
begin
if Reset = '1' then
RRegL <= '0';
BitPos := 0;
elsif Rising_Edge(Clk) then
if Enable = '1' then
case BitPos is
when 0 =>
RRegL <= '0';
if RxD = '0' then
SampleCnt := 0;
BitPos := 1;
end if;
when 10 =>
BitPos := 0;
RRegL <= '1';
DataO <= RReg;
when others =>
if (SampleCnt = 1 and BitPos >= 2) then
RReg(BitPos-2)<=RxD ;
end if;
if SampleCnt = 3 then
BitPos := BitPos + 1;
end if;
end case;
--
if SampleCnt = 3 then
SampleCnt := 0;
else
sampleCnt := SampleCnt + 1;
end if;
--
end if;
end if;
end process;
end Behaviour;
------------------------------------ Tx.vhd-----------------------------
---
-------------------------------------------------------------
-- Title : UART ---
-- Project : UART ---
-- Clock : 50MHz ---
-- Author : Pham Tuan Hai ---
-------------------------------------------------------------
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Tx is
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
 15

LoadA : in std_logic;
TxD : out std_logic;
Busy : out std_logic;
DataI : in std_logic_vector(7 downto 0));
end Tx;
---------------------------------------------------------------------
architecture Behaviour of Tx is
---------------------------------------------------------------------
component synchroniser
port (
C1 : in std_logic;
C : in std_logic;
O : out Std_logic);
end component;
signal TBuff : std_logic_vector(7 downto 0);
signal TReg : std_logic_vector(7 downto 0);
signal TBufL : std_logic;
signal LoadS : std_logic;
----------------------------------------------------------------------------
---begin

-- Begin of Architech
-- Synchronise Load on Clk
SyncLoad : Synchroniser port map (LoadA, Clk, LoadS);
Busy <= LoadS or TBufL;
-- Tx process
-----------------------------------------------------------------
TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
variable BitPos : INTEGER range 0 to 10;
begin
if Reset = '1' then
TBufL <= '0';
BitPos := 0;
TxD <= '1';
elsif Rising_Edge(Clk) then
if LoadS = '1' then
TBuff <= DataI;
TBufL <= '1';
end if;
if Enable = '1' then
case BitPos is
when 0 =>
TxD <= '1';
if TBufL = '1' then
TReg <= TBuff;
TBufL <= '0';
BitPos := 1;
end if;
when 1 =>
TxD <= '0';
BitPos := 2;
when others =>
TxD <= TReg(BitPos-2); -- Serialisation of TReg
BitPos := BitPos + 1;
end case;
if BitPos = 10 then -- bit8. next is stop bit
BitPos := 0;
end if;
end if;
end if;
end process;
end Behaviour;
------------------------------- COUNTER.vhd---------------------------
 16

--
-------------------------------------------------------------
-- Title : UART ---
-- Project : UART ---
-- Clock : 50MHz ---
-- Author : Pham Tuan Hai ---
-------------------------------------------------------------
-------------------------------------------------------------
library IEEE,STD;
use IEEE.std_logic_1164.all;

entity Counter is
generic(Count: INTEGER range 0 to 65535); -- Count revolution
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
O : out std_logic); -- Output
end Counter;
----------------------------------------------------------------
----------------------------------------------------------------
architecture Behaviour of Counter is
begin
counter : process(Clk,Reset)
-- Variable Cnt is using temple count variable
variable Cnt : INTEGER range 0 to Count-1;
begin
if Reset = '1' then
Cnt := Count - 1;
O <= '0';
elsif Rising_Edge(Clk) then
if CE = '1' then
--
if Cnt = 0 then
O <= '1';
Cnt := Count - 1;
else
O <= '0';
Cnt := Cnt - 1;
end if;
--
else O <= '0';
end if;
end if;
end process;
end Behaviour;
-------------------------- Synchroniser.vhd------------------
-------------------------------------------------------------
-- Title : UART ---
-- Project : UART ---
-- Clock : 50MHz ---
-- Author : Pham Tuan Hai ---
-------------------------------------------------------------
-------------------------------------------------------------
library IEEE,STD;
use IEEE.std_logic_1164.all;

entity synchroniser is
port (
C1: in std_logic; -- Asynchronous signal
C : in std_logic; -- Clock
O : out std_logic); -- Synchronised signal
end synchroniser;
 17

-------------------------------------------------------------------
architecture Behaviour of synchroniser is
signal C1A : std_logic;
signal C1S : std_logic;
signal R : std_logic;
begin
RiseC1A : process(C1,R)
begin
if Rising_Edge(C1) then
C1A <= '1';
end if;
if (R = '1') then
C1A <= '0';
end if;
end process;
-------------------------------------------------------------------
SyncP : process(C,R)
begin
if Rising_Edge(C) then
if (C1A = '1') then
C1S <= '1';
else C1S <= '0';
end if;

if (C1S = '1') then

R <= '1';
else R <= '0';
end if;
end if;

if (R = '1') then
C1S <= '0';
end if;
end process;
O <= C1S;
end Behaviour;
 18

Ti liu tham kho

1. Nguyn Tng Cng, Phan Quc Thng, V Hu Ngh (2002), Cu trc
my tnh, Hc vin k thut qun s, H Ni.
2. Nguyn Tng Cng, Phan Quc Thng, Trn Vn Hp (2002), Cu trc
cc h x l tn hiu s, Hc vin k thut qun s, H Ni
3. Nguyn Tng Cng, Phan Quc Thng (2003), Cu trc v lp trnh h
vi iu khin 8051, Hc vin k thut qun s, H Ni.
4. Vn Th Minh (1998), K thut vi x l, NXB Gio dc, H Ni
5. Xun Tin (1991), K thut vi x l, Hc vin k thut qun s, H
Ni.
6. David Harris (1955) Structural Design With Verilog Harvey Mudd
College.
7. Donnamaie E. White (2002), Logic Design for Array-Based Circuits,
Original Hardcover Still, London.
8. Don Davis (Winter 2002), Architectural Synthesis: Unleashing the
Power of FPGA System-Level Design, Xcell Journal, (Issue 44),
pages 3034, Xilinx, United States of America.
9. Giovanni De Micheli, Rajesh K. Gupta (3/1997), Hardware/Software
Co-Design, Proceedings of the IEEE, (Vol. 85, No 3),
pages 349 64.
10. Daniel Tabak (1995), Advanced Microprocesors, McGraw-Hill, United
States of America.
11. Donnamaie E. White (2002), Logic Design for Array-Based Circuits,
Original Hardcover Still, London.
12. Don Davis (Winter 2002), Architectural Synthesis: Unleashing the
Power of FPGA System-Level Design, (Issue 44), pages 30 34,
13. Michael John Sebastian Smith (1997), Application-Specific Integrated
Circuits, Hardcover (www.Amazon.com), United States of
America.
 19

14. Peter J.Ashenden (1990), The VHDL CooKBook, University of Adelaide,

South Australia.
15. Roger Lipsett & Carl Schaefer (1989), VHDL: Hardware Description
and Design, Kluwer Academic Publishers, United States of
America.
16. Ngun tham kho t Internet
http://support.xilinx.com/support/techsup/tutorials/index.htm
http://support.xilinx.com/ xlnx/xil_ans_brower.jsp
http://support.xilinx.com/apps/appsweb.htm
http://support.xilinx.com/ xlnx/xweb/xil_publications_index.jsp