krishna gaihre

FPGA Research Lead

gaihrekrishna@gmail.com

Summary
FPGA Design with Xilinx VIVADO and ISE Design Suit for Xilinx Ultrascale and 7 Series Boards.
Embedded design with Microprocessors and Microcontrollers.
Hardware and Designing Solutions.
Project Accomplished:
--PCIe based Design (PCIe 3.0 IPI, PCIe DMA TRD)
--Tcl Scripting for IPI design creation of PCIe Streamming Core for 7 series and Ultrascale Board.
--XDMA (DMA Subsystem for PCIe 3.0) Targeted Reference Design for Kintex Ultrascale FPGA.
--Video Streaming and Processing with Zynq (Zybo) FPGA.
--Image Enhancement with Zynq FPGA.
--Verilog Course Design for Online Learning Site.
--AXI PCIe MIG Design Simulation and Implementation in Xilinx 7 Series and Ultrascale FPGA.
--Implementation of Scatter Gather List (SGL Preparaion and Submission Block)

Conducted Training's on (for Professional and Academicians):

-- Embedded System Design with Zynq FPGA and VIVADO (Xilinx Training Syllabus)
--System Level Design with Zynq and VIVADO (RTOS and FSB Design)(Xilinx Training Syllabus)

Trainer on : Faculty Training

--FPGA Design with Zybo FPGA and VIVADO, Kantipur Engineering College
--FPGA Design with VIVADO Design Suit, Khwopa College of Engineering
Student Training
--FPGA Design with Xilinx ISE Design Suit, Himalaya College of Engineering

Research Outcomes (Paper, Proceedings and Articles) on:

--Very High Speed Packet Processing with FPGA and Custom Hardware (few Gbps to several Gbps)
--Packet Processing with heterogenous hardware: Herterogenous Computing
--RISC Processor Design
--Data Center based IP Design

Market Research:
--FPGA Market Review on Telecom, Medical and Automotive Market Segment.

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Short Reviews on:
--Packet Processing with OpenCL : Review
--SDN Implementation on FPGA
--SDR Implementation on FPGA.

Lab Instruction (for Universities/Colleges) on:

--Embedded System Design with FPGA, Designing Custom 8 bit Processor and Implementing FSM.
--HDL implementation on Digital Design, Digital Logic
--Computer Architecture Design with Verilog HDL.

Experience
FPGA Research Lead and Program Coordinator at Digitronix Nepal
March 2015 - Present (2 years)
Digitronix Nepal has a vision of to be an "IP designing company in Nepal", for achieving this vision there
are number of research labs on different engineering colleges which is directed by Digitronix Nepal.Those
research centers are also Xilinx University Program Centers which have basic resources for FPGA Design
including Licenses of VIVADO and 7 Series FPGA's. As a research Lead of the FPGA research and
development in Nepal, We have designed some basic type of IP's based on Xilinx VIVADO design suit and
targeted for 7 series and Ultrascale FPGA's. Currently we are working on IP development for Multemedia
Processing including Design and Verification on HDL and RTL.

Lecturer (Part-Time) at Kathford Int'l College of Engineering and Management

May 2015 - Present (1 year 10 months)
Conducting Labs on Embedded System, Digital Logic, Electronics Device and Circuits, Microprocessor,
Numerical Method for B.E Electronics and Computer Engineering.

Embedded system devlopment via different microcontroller(8051,PIC,Aurdino,AVR and ARM) and

FPGA at Digitronix Nepal
January 2012 - Present (5 years 2 months)
Embedded system development at
https://www.facebook.com/DigitronixNepal
http://www.digitronixnepal.com

Lecturer (Part-Time) at Himalaya College of Engineering

November 2015 - September 2016 (11 months)
Conducting Labs on Embedded System, Computer Organization and Architecture for B.E Electronics and
Computer Engineering.

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Projects
GSM Based Smart Home System
February 2013 to September 2013
Members:krishna gaihre, Kamal Pokharel, laxman chettri, pawan upadhaya
Our system can control and inform the house owner with his/her house appliances (electrical and other)
automatically and manual (Via SMS) and in some emergency case (theft, fire) this system can informed
police and fire fighting automatically.which is important for the home security.
Inauguration Robot-Smartphone Based Curtain Control System
February 2015 to March 2015
Members:krishna gaihre, Er. Saban Kumar KC, Rabin Dhakal, Rupen Aryal
Inauguration Robot-Smartphone based curtain control system for inauguration of old citizen care center at
Sunderdham, Najarpur, Rauthat.
Inaugurated Successfully by the President of Nepal Dr. Ram Baran Yadav on Feb 25, 2015 at Sunderdham,
Najarpur, Rauthat,Nepal.

Image Processing in Zybo (Zynq 7000) FPGA

May 2016 to August 2016
Members:krishna gaihre
Image processing (including some image enhancement features) in Zybo FPGA.The implementation is done
in VHDL in Xilinx VIVADO Design Suit 2015.4. The Image is initially converted in to HEX format by
the Visual Studio Program (others can also do JPEG into HEX) and then the HEX value of image (RGB) is
processed with Zybo and returned back to original location initailly. The second phase consists of processing
iimage (HEX) and displaying processed image into VGA.
SDN Implementation on FPGA
April 2016 to Present
Members:krishna gaihre
Software Defined Networking (SDN) implementation is done on Xilinx FPGA-Zynq 7000. SDN is designed
on the basis of OpenFlow (openflow.org) Protocol , it comprises of OpenFlow Controller, OpenFlow Switch
and Flow table inside switch. This SDN differentiates the Network Control Plane and Data Plane instead
of traditional routers. SDN is preferred in FPGA for getting high speed and flexible system. NetFPGA
(netfpga.org) is a SDN implementable FPGA developed initially at Stanford University this FPGA is highly
utilized for SDN implementation in Academic and Industry. While Zynq 7000 (ZedBoard) family from
Xilinx is also highly used for low cost and flexible design implementation. This project's objective is to
create a OpenFlow Switch on FPGA which flow table is updated from OpenFlow controller in the Linux
Host Machine. The switch transact the packet according to the flow table and if new type of address/packet
arrives in the switch then it request the controller for the updates/instructions. This is one of the heavily
funded project in Universities and companies world widely.
High Speed Packet Processing in FPGA
May 2015 to September 2015

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Members:krishna gaihre
High speed packet processing which is Range of few Gbps (40 Gbps) to few hundred Gbps (400 Gbps)
has been achieved in FPGA. The project done a survey on high speed packet processing implementation
on FPGA and implemented a model for getting few Gbps rate of Packet processing. The Survey type
of Research paper in on publication. The highest speed achieved is 400 Gbps by Michael Attig and
Gordon Brebner at Xilinx Research Lab (https://www.xilinx.com/programmable/about/research-labs/
ANCS_final.pdf).
Undergraduate Project Supervision on " Gesture Controlled Device
July 2015 to September 2015
Members:krishna gaihre
Gesture Control Device is based on the Hand Gesture targeted for Automation for Unable and able peoples.
This system is designed based on AVR Microcontrollers (AVR 32). Most of Interfacing task on AVR
Microcontrollers has been used for increase project efficiency for targeted people.
Modifications for Targeted Reference Design (KCU105 PCI Express Streaming Data Plane TRD, UG
920)
August 2016 to October 2016
Members:krishna gaihre
Modification of Targeted reference design's base design and user extension design with replacement of third
party ip (NWL Expresso DMA) with VIVADO's IP for DMA.
Project Supervised for " FPGA Based High Precision Stepper Motor Control"
August 2016 to Present
Members:krishna gaihre
FPGA Based High Precision Stepper Motor Control is project based on Spartan 3e FPGA. Where the User
Interfaced control is provided from NI-LabView GUI and speed Stepper Motor is controlled by Sartan
FPGA.
External Project Examiner for B.E in Electronics and Communication Engineering
November 2015 to Present
Members:krishna gaihre
Four Automation and Communication based Project Examined at Khwopa Engineering College (Bhaktapur ,
Nepal). Four Automation based project supervised at Nepal Engineering College.
Creating Custom AXI IP on VHDL in VIVADO Design Suit for ZedBoard
January 2017 to Present
Members:krishna gaihre
Creating a custom AXI IP in VHDL which have been done at Xilinx VIVADO Design Suit and targeted for
Zedboard FPGA.
Running Vivado Tcl Scripts of Different Version of VIVADO and Zedboard DMA Audio Demo
January 2017 to Present
Members:krishna gaihre

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 This Project completed with preparation of tutorial on how to run Tcl scripts generated on different version
of VIVADO Design suit. Generally running the Tcl scripts might get complication so we need to edit some
parameters on the Tcl scripts. However there might have some minor warnings on Running Tcl scripts after
editing, some IP on the IP catlogue of VIVADO might have been updated but we can reject the up-gradation
of IP on current design.

Languages
English
Nepali
Hindi

Skills & Expertise

Embedded Systems
C++
C
FPGA
HTML
Teamwork
Java
Matlab
Microsoft Word
PCB layout design
ARM
PowerPoint
Microsoft Excel
Photoshop
Social Media
Windows
English
Image Processing
ARM7
Android Development
Microsoft SQL Server
Microcontroller Based Embedded system
devlopment
Customer Service
Public Speaking
Illustrator
SQL
VHDL
Verilog
Tcl-Tk
Embedded Linux
SDK development

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Deep Packet Inspection
OpenCL
SystemVerilog
SystemC
High Speed Bus Interfacing in FPGA, PCIe, AXI
Microsoft PowerPoint
Field-Programmable Gate Arrays (FPGA)

Education
IOE Pulchowk Campus
M.Sc Engineering In Technology and Innovation, 2013 - 2015
IOE Western Region Campus
Bachelor's degree, Electronics and Communications Engineering, 2009 - 2013

Interests
Embedded System Design with FPGA and ARM Technologies, Avionics,Satellite Communication, Artificial
Intelligence (Machine Learning/Vision, NLP).

Publications
ARM Based Computing Technology for Sustainable Development (Performance Analysis on E-Learning)
Proceedings of IOE Graduate Conference December 2015
Authors: krishna gaihre
E-learning is implemented and granted all over the world by many government, NGO and INGOs. Education
with ICT has improve the learning methods and techniques with more interactive, student oriented and
effective ICT based learning environment. In Nepal, OLE Nepal has implemented E-Learning project
in association with OLPC and some other organizations. This research aims to finding out the relative
performance of ARM Processor based OLPC which was deployed in public schools of some district in Nepal
by OLE Nepal. So that either it is
very effective to Nepalese students or students are not able to grabbing more knowledge and skills from this
ARM based computing devices -OLPC. This learning methodology utilizes and harvest computing power
from
ARM based processors with custom build laptop which utilize less power than the traditional x86-64 bit
processor.
Which is the part of sustainable energy consumption and development. This research used qualitative
research
methodology with survey type of research method to determining the relative performance of e learning.
After
analysis the Nepalese scenario of this learning and teaching methodology, performance analysis and
effectiveness

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 of E-Learning with some direct/ indirect benefits will identified. Necessary improvement on the E-learning
process
and systems based on OLPC will suggested so that the overall performance of the student on E-learning will
increased or improved.
ARM Based Processor Computing Technology For Sustainable Development (Performance Analysis on
E-Learning)
www.researchgate.ne
Authors: krishna gaihre

Organizations
Nepal Engineers Association

Certifications
FPGA Designer
Xilinx University Program

Volunteer Experience
Research Lead at Digitronix Nepal
February 2013 - Present

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krishna gaihre
FPGA Research Lead
gaihrekrishna@gmail.com

Contact krishna on LinkedIn

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