VHDL Tutorial

By:Shahed Shahir
Email: sshahir@engmail.uwaterloo.ca
 Outline
VHDL Quick Look
Entity
Architecture
Component
HalfAdder
FullAdd
Generate if Statement
Selected Signal Assignment
Generics
How to develop VHDL code using Xilinx Project
Navigator
 VHDL Quick Look

Entity
Architecture

All the available signal types and functions can be imported by adding :
In C:
Library ieee;
#include <stdio.h>
 Entity
entity < entity_identifier>is
Port(
<signal identifier> : <mode> <type>; mode type

In Std_logic

<signal identifier> : <mode> <type>; Out

Boolean
Integer
Inout
String
buffer
<signal identifier> : <mode> <type>); character

end < entity_identifier >; Boolean STD_logic

W(Week Unknown)
U(Uninitialized)
Example: X(Unknown)
entity QuarterAdder is - (Dont Care)

port(
L (Week Low)
i_a : in std_logic;
i_b : in std_logic; H (Weak High)
Z (High impedance)
o_s : out std_logic);
end QuarterAdder ;
 Architecture
architecture <architecture_name> of <entity_identifier> is
[ architecture_declarative_part]
begin
<architecture_statement> ;
<architecture_statement> ;
Concurrent statements

<architecture_statement> ;
end <architecture_name>;

Example:
architecture main of QuarterAdder is
begin Int main (void)
o_s <= i_a xor i_b;
{
end main;
Printf(Hello World);
}
 Component
Component < entity_identifier>
Port(
<signal identifier> : <mode> <type>;
<signal identifier> : <mode> <type>;

<signal identifier> : <mode> <type>);
end Component;
VHDL Code For HalfAdder
entity HalfAdder is
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic;
o_c : out std_logic);
end HalfAdder ;

architecture main of HalfAdder is

component QuarterAdder
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic);
end component;

begin
o_c <= i_a and i_b;
QuarterAdder port map( i_a, i_b, o_s);
end main;
 FullAdd
Library iieee;
Use ieee
Entity FullAdd is
port (
i_a, i_b,i_c : in std_logic;
o_s,o_c : out std_logic);
End FullAdd;

Architecture main of FullAdd is

Beging
o_s<=i_c xor i_a xor i_b;
o_c<=(i_c and ( i_a or i_b)) or (i_a and i_b);
End main;
 Generate-If Statement
Library ieee;
Use ieee
Entity adder is
Port (
! "# $ downto
% "# $ downto
o_c: out std_logic);
End adder;
Architecture main of adder is
Component fulladd
Port(
i_a, i_b, i_c : in std_logic;
o_s,o_c : out std_logic);
End component;
Component halfadd
Port(
i_a,i_b :in std_logic;
o_s,o_c : out std_logic);
End component;
& ! $$' "# $ downto := ;
& ! "# $ downto ):= ; Signal initialization
 Generate-If Statement (cont)
Begin
($ ! downto #!#$ #
) * + #!#$ #
* halfadd --Label
, $- . $$'
End generate;
) *+ #!#$ #
(% fulladd Generate with if
, $- . $$'
End generate;
) * /+ ! / + #!#$ #
Fulladdi : fulladd
Port map(a(i), b(i), carry(i- $$'
End generate;
End generate;
Concurrent statements
a<=i_a;
o_s<=s;
End main;
 Selected Signal Assignment
With <expression> select
<target> <= <waveform> when <choice>;
< waveform > when <choice>;
< waveform > when others;
Example:
Library ieee;
0 # ###
Entity muxone is
,$ !
! "# $ downto
o_q:out std_logic);
End muxone;
Architecture main of muxone is
Begin
With i_c select
12+ #! ;
#! ;
#! ;
#! #$
End main;
 Generics
345657 $# 6&
! !
port(clk,r: IN std_logic;
64 "# $ width - );
1805 "# $ width - ));
#! $#

9:; 653;50:3 !*#$ *$# 6&

...
* $+<< #!12+ others => );

End infer
LIBRARY IEEE;

port(clk,r: IN std_logic;
downto !"
# $ downto !""
%

&'( ' & )

*+ % %
generic(width:positive;
reset_value : positive);
port(
clk,r: IN std_logic;
d:IN std_logic_vector(width- downto !"
q:OUT std_logic_vector(width- downto !"
);
end component;

begin
, generic map (reset_value -. / width -. " + *,+
(clk/ / /# "
%
How To Develop VHDL Code
Using Xilinx Project Navigator
 This brief tutorial will help you on how to start a VHDL
project on Xilinx ,$ = # 4" $ #. ' #.
 new project
Select a Name for the project
Select Schematic as the project type
Click Next
 Select the device properties
Click Next
 Click on New Source
Select a name for your VHDL code
Choose VHDL module
Click Next and click next
Click finish
 Click next
Click next
Click finish
Any question or Comment?