Comparative study of different low power adder
structure to build low power high performance
VLSI system: a review
SUKANYA SINGH1, ADITI SHARMA2
Dept. VLSI design and System
Graphic Era University
Dehradun, India
sukanyasingh18@gmail.com
aditi.sharma059@gmail.com
Abstract - This paper demonstrates designing of
low power adder structures with different logic
styles which emphasis on reducing the transistor
count and without degrading the performance.
This paper includes eight different style adders
which are compared on number of transistor,
power, total delay and power delay product.
Simulation result reveals that 8transistor full
adder have the least power and delay and hence
the least power delay product further these 1bit
full adders are employed for implementation of
carry propagation adder and hence concluded it
the best suitable structure for the application of
large VLSI unit which apply the adder structure
in their design like multipliers, floating units
Key Words: XOR gate, Full adder, Transistor
count
I. INTRODUCTION
The rapid increase in the usage of portable devices
like mobiles, notebooks, portable communication
systems and personal digital assistant as well as the
shrinkage of transistor size on an IC has extensively
amplified the need for research in Low power VLSI
design. The major challenge that the world is facing
today is on the grounds of performance and area. energy require by the gate for shifting output voltage
Researchers are evolving new designs that require
minimum area and have high throughput .In general,
small area and high performance are the Reducing the number of transistors can reduced
conflicting constraints [3] The IC designer activities
should involve trade off between these constraints.
The common attributes of a high-throughput chip are
high device density, high speed and high clock
frequency [3] which results in large power dissipation
and hence it result in increases temperature of a
device. Therefore heat must be removed effectively
to keep the device cool and work properly. For this
problem one need to Optimize the device by
employing low power methods which can differ from
circuit level to system level to process level. One bit
Abhay Sharma3
Graphic Era Hill University
Dehradun, India
abhay.ece.gehu@gmail.com
Full adder is one of the foremost valuable and
efficient parts of a processor [3], as it utilized in
arithmetic logic unit, the floating unit [3, 4]. As we
know the full adder cell is a basic building-block in
binary addition [4] therefore upgrading the
performance of one bit full adder is significantly
good aspect which has attracted much attention in
past. This paper presents a comparative study of the
different low power adder which uses different logic
styles to implement low transistor count adder. It
discusses the eight different adder structure including
the conventional 28Transistor full adder, pseudo
NMOS 18Transistor full adder, 14Transistor full
adder, multiplexer based 12transistorT full adder,
10Transistornoval XOR/XNOR full adder and
minimum 8Transistor full adder based on 3Transistor
noval XOR gate comparative analysis has been done
on power and it has been found that 8Transistor
consumes 33%less power compares with
conventional adder similarly it has the least PDP of
23% compares with other full adder.
Power delay product of a circuit is defined as the
product of a average power consumption and
significant path delay PDP is consider when
optimizing both power and performance its the most
from one state to a different logic state . [10].
PDP =Power * DELAY
power but sometime may not improve the
performance. As die area depends on number of
transistors and routing complexity [2].All these
aspects of full adder vary from one logic design to
other logic design.
This paper presents different full adders which are
compared at circuit level using 180nm CMOS
technology. The rest of the paper organized as
follows section 2 reviews the different adder structure
designed on the minimum transistor count or the
minimum basic XOR gate. Section 3 discusses the
power dissipation, energy consumption and power
delay product of the following adders. We provide
the theoretical analysis and correctness of our
approach section 4 conclude the paper

II. LOW POWER ADDER STRUCTURE

A. Traditional 28t CMOS full adder
An ideal design of standard static CMOS full adder
has dual (PMOS) network and equivalent NMOS
network. It uses 28 transistors to implement
respective sum and carry function due to this it has
full swing output. At the same time existence of
PMOS block in static CMOS circuit full adder can
have large silicon area consumption due to its low
mobility as compared with NMOS. Hence, there is a
need for optimization in existing structures to get
desired performance.
Fig: 2 Pseudo NMOS 18T full adder
C. 14T full swing voltage adder
14 transistor full adder circuits is designed using six
transistor XOR gate. This XOR gate is realized using
cross-coupled PMOS and NMOS. Due to this cross-
coupling it does not achieve output when both the
input signals A and B are high for this a feedback is
provided on PMOS and NMOS shown with * in fig 3
below [5]. This feedback has considerably helped in
reducing threshold voltage. Due to reduced number
of transistor this adder results in low power
dissipation than single logic adders. The disadvantage
of this adder is low driving capability and low noise
immunity.

Fig1: conventional full adder using28T [1]

B. Pseudo NMOS full adder

This full adder circuit is designed on pseudo-NMOS
logic (rationed logic) which uses 18transistors to .
build full adder the (PMOS) pull-up arrangement is Fig: 3 six transistor based XOR /XNOR circuit [5]
replaced by a individual PMOS transistor with its
gate grounded. Since in this structure the PMOS
source is always connected to the VDD it is always
on as it is not driven by the input signals applied to
the circuit while NMOS transistor is turned on on
the application of input signals this creates the direct
path between supply and ground hence the static
power will be drawn to achieve the required output.
As the pseudo NMOS logic is build on usage of total
NMOS transistor it has less transistor count and high
speed compare with the conventional.

Fig: 4 14T full adder [5]

D.12T full adder designed on noval multiplexer
This full adder is realized using noval low power
multiplexer design. These individual multiplexer
circuits are designed using 6transistor and in total 12
transistors are used in making full adder circuit. This
circuit works on charge recycling capability and due
to which it has low short circuit current .As shown in
fig5 MBA-12T adder is not connected directly with
VDD or VSS port this has lead to reduction in
positive voltage supply to ground during switching
activity this ultimately leads to reduction in power
consume during short circuit curent.MBA-12T adder
has high speed because the internal nodes are directly
connected with input signal as the input signal arrives
at the internal node at the same instinct when the
input is applied to the circuit this has resulted in
faster output with less transistor count comparing
with logic styles.
Fig: 5 MBA-12T full adders [6]
E. 8T Novel full adder
This full adder is realized using 3 transistor XOR
gate. The final full adder is build using the 8
transistor. The circuit of 3transistor is shown below
Fig: 6 noval 3TXOR/XNOR circuits [7]
This XOR gate uses the conventional CMOS inverter
design and one pass transistor. When the input B is at
the low logic the inverter gets in high impedance
stage while at the same time transistor M3 gets
enabled which helps in getting same logic as on A to
the output Y. While on the other hand when input B
is at high logic the CMOS inventor behaves like
normal inverter and output gets the complemented
value of input A.
The working of whole circuit is analogous to the
normal XOR gate. However when one of the gates
input is high and other input is low circuit shows
corrupted output due to voltage degradation
occurring at the transistor M3 due to threshold
voltage drop [7].This complication has been resolved
by scaling width by length ratio of transistor M3.For
the finale full adder circuit the width by length ratio
of transistor M1 and M6 are kept2/1 and 1/1
respectively. While the W/L ratios of transistors M7
and M8 are kept as 5/1. The 3 transistor XOR gate
has much less delay and consumes much less power
when compared with conventional structures. Full
adder using this noval XOR gate has been
implemented.
Fig7:8T full adder [7]
F. low power full adder design applicable for tree
structure [8]
This low power full adder is designed for tree
structure application. This is realized by applying
opposite signal at input, buffer inverter at the output
of transmission gates. To increase the driving
capability of these adders additional buffers are used
at the outputs which makes them suitable for tree
structure designing. In this design Ci is used s
complementary signal. The reworked full adder
Boolean expressions are
S = PB + PB
Co =PB +PA
P=A Ci [7]
Addition of buffers at the output also makes the
circuit suitable in cascade structures as it helps in
matching the complementary signal at input with the
output.
 Fig: 10 10T full adder style1 [9]
Fig: 8 20T type full adder [8]

G. 10T full adder based on novel XOR and XNOR

Before presenting new 10T full adder structure we
introduce a noval XOR and XNOR circuit this noval
XOR circuit is also called powerless XOR or PXOR
.this is because new XOR gate involve no power. It is
similar to the inverter-based XOR but the
dissimilarity is given in context with the VDD
connected to input A in new inverter based XOR
[9]. Similarly for noval XNOR there is no direct
connection to the ground it is called groundless
XNOR.
For designing of full adder we use three modules in
module 1 and module 2 can be exclusive OR or
exclusiveNOR gates and module COUT can be as a
PMOS or doubleNMOS transistor or multiplexer
circuit. Sum is generated by cascading module 1 and
module 2.if module 1 and module 2 are XOR gate
then module COUT have configuration shown in fig
a and if module 1 consist of XNOR gate the COUT
can have the configuration shown in fig b respective
structures of new full adders are given as
Fig: 11 10T full adder style2 [9]
III. THEORETICAL ANALYSIS AND
JUSTIFICATION
These complete adder structures are designed in
Cadence Virtuoso Environment using180nm
Technology GPDK Toolkit, with Threshold Voltage
of 0.9v and voltage delivery of one.8V,.these
structures are analyzed on the idea of transistor count,
delay related with individual input given to (sum and
carry),as well as power consumption. Energy
consumption, power delay product as shown in
following tabular columns

A. full adders designed in respect of number of

Transistors
The table1, and furthermore Figure1 2 gives
examination between various full adder structures on
its Transistors Count, which will in a roundabout
way, gives us data about the die size or silicon area
consumed .More the number of Transistors, Higher is
a
the area consumed, and other way around.

Table: 1 number of transistors in different full adders

FULL ADDER NUMBER OF
TYPE TRANSISTORS
28T CMOS Full Adder 28
20T type full adder 20
18T NMN Full Adder 18
14T Full Adder 14
b 12T Full Adder 12
10T(9A) Full Adder 10
10T(13A)Full Adder 10
8T Full Adder 8
 Power(u watts)
NUMBER OF TRANSISTORS USED
1.50E+00
30
1.00E+00
20
5.00E-01
10 0.00E+00
0

Fig: 14 power consumed in full adders

Fig: 12 transistor count of different full adders
D. full adders designed in respect of energy
B. Full adders designed in respect of sum and carry consumption
delay Energy dissipated is mainly related to the loss of
The Tables 2 shows the different Adder types and energy due to generation of unwanted heat in
there Delays with respect to the inputs given to sum electronic circuit. This gives us the desired
and carry respectively. More the Delay less will be its performance and efficiency of the circuit with respect
speed of operation, and vice versa. to specific design parameters
Table: 2 propagation delay in different full adders Table: 4 energy dissipation in full adders
FULL ADDER Sum delay Carry delay FULL ADDER TYPE Energy consumption(joules)
TYPE 28T CMOS Full Adder 77.92E-9
28T CMOS Full Adder 5.7750E-8 5.3729E-8 20T type full adder 90.17E-9
20T type full adder 2.57E-8 4.57E-8 18T NMN Full Adder 109.2E-9
18T NMN Full Adder 2.83382E-8 5.36656E-8 14T Full Adder 123E-9
14T Full Adder 4.85105E-8 5.378202e-8 12T Full Adder 952.2E-9
12T Full Adder 4.853251E-8 6.322387E-8 10T(9A) Full Adder 90.17E-9
10T(9A) Full Adder 4.7905E-8 1.716008E-7 10T(13A)Full Adder 100.7E-9
10T(13A)Full Adder 6.220156E-8 4.614164e-8 10TNovalXOR/XNOR 52.24E-9
8T Full Adder 4.65481E-8 4.6636E-8 8T Full Adder 80.07E-9

2.00E-07
Energy consumption(joules)
1.50E-07
1.50E-07
1.00E-07
sum 1.00E-07
5.00E-08 5.00E-08
carry
0.00E+00 0.00E+00

Fig: 13 propagation delay in full adders Fig: 15energy dissipation of different adder structure

C. Full adders Designed as far as power dissipation E. Full adder in terms of their power delay product
The full adders are determined in terms of power PDP is a significant parameter to measure quality
dissipation, and the results is as shown in table3 performance of a circuit. It is designed to realize
digital(computational) functions; in digital circuits
Table: 3 full adders with power signaling in response to the signal either on or
FULL ADDER TYPE Power(u watts) off;designed to assure as fast as possible switch of
28T CMOS Full Adder 779.23E-3
20T type full adder 907.7E-3 output signal from on to off state(and vice versa)
18T NMN Full Adder 1.092 with little energy required. In alternate words its a
14T Full Adder 1.23 foresaid to be figure of advantage that corresponds to
12T Full Adder 1.168 the energy potency of a circuit. It is given because the
10T(9A) Full Adder 539.9E-3 product of average power during change activity
10T(13A)Full Adder 1.007
8T Full Adder 488.8E-3
times the delay. The derogation of power delay
product is considered for low power and elite
application [10].
 V. CONCLUSION
Design and simulation results shows that lower the
power delay product
transistor count decrease the delay and power
8.00E-08
power consumption. We get 10% delay less in 8T full adder.
6.00E-08 It consume 33%less power than conventional adder
4.00E-08
2.00E-08 and 5% speedier than the 12T and 10T full adder

10T(1
10T(1
0.00E+00
therefore it suitable for the application of low power
28T
18T
14T
12T

20T
10T(9A)

8T
high performance VLSI system. These new full adder
can be the perfect candidates to build large systems
Fig: 16 power delay product of full adders
like multipliers, floating units, these small areas
adders can significantly reduce the system build on
IV. CARRY PROPAGATION ADDER them. The described full adder structures were
IMPLEMENTATION employed for the implementation of carry
Parallel adder employing the adder structure propagation adder or parallel adder. From the
discussed above (28T, 18T, 14T, 12T, 10T, 8T) was simulation result it was observed that 8T full adder
implemented to observe the implications derived consumes the least power when took in relative to
which discussed the mentioned structure. other adder structure reason for this comparison can
Implementation was cadence virtuoso IC156.5.5 and be consider transistor count.
simulation waveform for the same is shown in fig18
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