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335883
335883
Zehra Glru AM
HAZRAN 2013
STANBUL TEKNK NVERSTES FEN BLMLER ENSTTS
Zehra Glru AM
(504111224)
HAZRAN 2013
T, Fen Bilimleri Enstitsnn 504111224 numaral Yksek Lisans rencisi
Zehra Glru AM, ilgili ynetmeliklerin belirledii gerekli tm artlar yerine
getirdikten sonra hazrlad GR IKI UYUMLU, YKSEK DNAMK
ARALIKLI, Si-Ge TRANZSTORLU RF KARITIRICI TASARIMI balkl
tezini aada imzalar olan jri nnde baar ile sunmutur.
iii
iv
NSZ
v
vi
NDEKLER
Sayfa
NSZ ........................................................................................................................ v
NDEKLER ........................................................................................................ vii
KISALTMALAR ...................................................................................................... ix
ZELGE LSTES ................................................................................................. xii
EKL LSTES ..................................................................................................... xiiii
ZET......................................................................................................................... xv
SUMMARY ........................................................................................................... xviii
1. GR ...................................................................................................................... 1
1.1 Tezin Amac ....................................................................................................... 2
1.2 Tezin Organizasyonu .......................................................................................... 2
2. KARITIRICININ ANALZ .............................................................................. 3
2.1 Dorusal Olmayan zellik le Kartrma.......................................................... 4
2.2 Anahtarlamal Devreli Kartrclar ................................................................... 5
2.3 Dntrc Kazanc ......................................................................................... 9
2.4 Kartrc Grlt Says ................................................................................. 12
2.5 Dorusallk ....................................................................................................... 18
3.KARITIRICI DEVRESNN TASARIMI ....................................................... 21
3.1 Kuramsal Hesaplamalar ................................................................................... 21
3.2 Grlt Hesaplamalar ..................................................................................... 26
3.3 Devrenin Benzetimi.......................................................................................... 33
4. SONULAR ......................................................................................................... 41
KAYNAKLAR ......................................................................................................... 43
ZGEM .............................................................................................................. 45
vii
viii
KISALTMALAR
AF : Ara Frekans
AS : Ara Sklk
BGS : Bant Geiren Szge
GS : Grlt Says
IP3 : nc Derece Kesiim Noktas
RF : Radyo Frekans
Si-Ge : Silisyum-Germanyum
OB : Ortak Baz
OE : Ortak Emetr
YO : Yerel Osilatr
ix
x
ZELGE LSTES
Sayfa
xi
xii
EKL LSTES
Sayfa
xiii
ekil 3.23 : Benzetim iin kullanlan devrenin tam hali ............................................ 40
xiv
GR IKI UYUMLU, YKSEK DNAMK ARALIKLI, Si-Ge
TRANZSTORLU RF KARITIRICI TASARIMI
ZET
xv
xvi
SIMULTANEOUSLY MATCHED SIGE TRANSISTOR RF MIXER DESIGN
WITH HIGH DYNAMIC RANGE
SUMMARY
An active mixer which is operating at 2.15 GHz and based on the Gilbert Mixer
topology is designed by using 200 GHz fT, 0.25 m SiGe technology. Mixeris
simulated with AWR software environment. The circuit exhibits an Output IP3 of
24.7 dBm and the conversion gain of 3 dB with the local oscillator power of -2.5
dBm. DC power supply voltage is5V. The noise figure of the circuit is simulated as
11.75 dB.
Mixers are key components in both receivers and transmitters. Mixers translate
signals from one frequency band to another. The output of the mixer consists of
multiple images of the mixers input signal where each image is shifted up or down
by multiples of the local oscillator (LO) frequency. The most important mixer output
signals are usually the signals translated up and down by one LO frequency.
The voltage conversion gain is the ratio of the root mean square voltages of the IF
and RF signals. The power conversion gain is the ratio of the power delivered to the
load and the available RF input power. The 3rd order intercept point (IP3) is the
point where the third-order term as extrapolated from small-signal conditions crosses
the extrapolated power of the fundamental.
Basically mixers are classified as active and passive mixers. Although passive mixers
have conversion gain less than one (lossy) and has noise figures bigger than active
mixers, they present less intermodulation distortion (the bigger OIP3 values). An
important advantage of passive mixers over their active counterparts is their much
lower output flicker noise. However, the low gain of passive mixers makes the 1/f
noise contribution of the subsequent stage critical. Additionally mixers are
categorized as single-balanced and double-balanced topologies. Double-balanced
topologies are more preferable than single-balanced mixers because of their isolation
between ports, suppressing the unwanted signals and linearity specialities. One
advantage of double-balanced mixers over their single-balanced counterparts stems
from their rejection of amplitude noise in the LO waveform.
The proposed mixer circuit is designed for to be used as the second mixer stage in a
RF receiver IC. The performance requirements are specified as; 3 dB Conversion
Gain, Output Third Order Intercept Point (OIP3) of minimum 20 dBm, and the noise
figure of maximum 12dB. The mixer is consists of a modified Gilbert Cell topology
where the input voltage current converting stage is realized by using CB and CE
stages which operate interactively to provide matching at the input. The IF output
amplifying stage with reasonably high dynamic range is arranged as the combination
of the inverting and non-inverting stages to provide the power doubling at the
output. Gilbert Cell is the most common double balanced mixer switching topology
which is used in various RFIC applications. It is quite convenient to obtain the high
gain with high dynamic range and low power consumption by using this circuit.
xvii
The modified version of this circuit which is presented in this work eliminates the
use of any passive baluns at the both ports and provides very broadband impedance
matching at the both ports.
At the input stage, an active balun topology is used. The feed-forward connection
from the CE to a CB stage with capacitive voltage divider is used for to provide
impedance matching at the input. This technique provides highly broadband input
matching with the additional advantages of good linearity and less noise-figure than
the other techniques. For a certain RF input power, all element values and ratio of
capacitors which is used as voltage divider are calculated.
At the switching transistors, a small change on the switching voltage can modulate
the switching time and creates distortion on the differential current waveform.
Therefore, the circuit elements are selected as to provide the rapid tranition of the
toggling transistors. The first significant part of the total noise figure is coming from
the switching transistor. Second, the noise source is transistors at the gain stage and
the third is the source resistors.
Noise is measured using the noisegure (NF) definition, which is a measure of how
much noise the mixer adds to the signal relative to the noise that is already present at
the input signal. The noise figure of 0 dB is ideal, meaning that the mixer adds no
noise. The NF of 3 dB implies that the mixer adds an amount of noise equal to that
alreadypresent in the signal. For a mixer alone, a NF of 10-12 dB is typical.There are
there different frequency bands which must be considered during mixer NF analysis.
Firstly, transistors and resistors at the circuit produce noise at intermediate frequency
(IF). Some of these noise, for example IF noise produced by collector resistors
occurs at the output. Secondly, noise produced at RF and the image frequency, mixes
with local oscillator at the mixer and they seen at frequency IF at the output.
Collector shot noise at the gain stage is an example for this type of noise. Lastly,
noises produced by LO can be transmitted to the IF output. Noise power which is
transmitted to the IF output is not constant through the LO period. At the higher LO
values, the dominant noise comes from the gain stage transistors. It is an expected
behavior because LO causes the differential pair transistors to switch between
saturation and cut off regions. At both of two stages there is no gain at the transistors,
they contribute very little noise. Also, gain through the input is maximum in these
conditions. So a sharply switching high amplitude LO signal is needed to obtain a
high signal-to-noise ratio.
However, during finite fall and rise time, for square or sinusoidal local oscillator
signal, local oscillator has zero crossings. During this time, switching transistors
operate at active region. In this region, transistors act as amplifiers and noise
produced at switching transistors and local oscillator, such as thermal noise due to
base resistors and collector shot noises become dominant.
Flicker-noise is one the critical issues in the direct conversion mixers. There are two
major mechanisms that generate the flicker noise of the switching pair devices. The
first one is the direct mechanism, due to the finite slope of the switching pair
transitions. In order to decrease flicker noise in the direct mechanism, the size of the
switching pairs needs to be increased, and large switching devices increase the
parasitic capacitance of the switching pairs, resulting in the flicker noise indirectly
translating to the output. The second mechanism that generates flicker-noise is the
indirect mechanism, flicker-noise mainly depends on the tail capacitance (Cp) at the
node between the LO switches and RF transconductance stage. In order to decrease
xviii
the flicker-noise in CMOS active mixers, the bias current of the local oscillator (LO)
switches should be small enough to lower the height of the noise pulses. The static
current injection technique was proposed to reduce the bias current of the LO
switches. However, the impedance of the LO switches as seen from the RF stage is
increased as we reduce the bias current of the LO switches. In addition, RF leakage
current flows through the injection circuit, which decreases conversion gain and also
allows more RF current to be shunted by the tail capacitance (Cp) at the node
between the LO switches and RF transconductance stage.
The shot- noise coming to the output from the switching transistors, which is stated
as is proportional with the transistor collector current. However the noise
coming to the output from the input stage, which is stated as
is inversely proportional with the collector current. To reduce the shot- noise coming
from the Gilbert Cell, the currents which flow through the load resistors and
switching transistors is decreased by injecting a current to the connection point of
Gilbert Cell through resistors. In this way, collector current which flows through
input transistors remains constant, and collector current which flows through
switching transistors decreases. So, the collector currents become independent from
each others. Noise figure is decreased by this current reduction technique. To obtain
the same conversion gain, load resistors of the Gilbert Cell are increased with the
current reduction ratio. Therefore,because of this increased resistor value, decreasing
in the noise figure is not as high as prediction.
All noise sources which are both thermal and shot at the circuit is determined and
calculated. The noise components of interest lie in the RF range before
downconversion and in the IF range after downconversion. Noise sources at the
circuit are RF and IF noise coming from switching transistors, source noise, noise
coming from active balun topology including thermal noise of resistors and the shot
noise of transistors.Another shot noise mechanism in active mixers arises from the
finite capacitance at tail node of Gilbert Cell. Noise voltage which is at emitter of
switching transistor creates a noise current because of parasitic capacitor C p. The
source of noise voltage at this node is shot- noise at the switching transistors. This
noise contains both RF and IF components. To estimate the input-referred noise
voltage, for each source of noise, a conversion gain is determined to the IF output;
the magnitude of each noise is multiplied by the corresponding gain and add up all of
the resulting powers, thus the total noise at the IF output is obtained; the output noise
is divided by the overall conversion gain of the mixer to refer it to the input.
Noise figure is the ratio of this total noise power and noise power coming from the
source. The terms in the total noise power statement is weighted bearing in mind that
when all switching transistors are on, noise coming from amplifying stage is
cancelled due to differential output. On the other hand, noise produced at switching
transistors can be negligible when input stage and Gilbert Cell act as a cascade
amplifier. So, the time when all switching transistors are on was calculated and noise
figure equation is obtained.
Lastly, different ratios of current reduction is tried and circuits simulated.
Simulations shows that when the ratio of current reduction increases, the noise figure
decreases. Input reflection coefficient has a decreasing behavior by decreasing the
collector current. Output third order intercept point shows great rise with decreasing
the collector current but operating point changes. Optimum values are obtained with
%50 current reduction and -2.5dBm local oscillator power.
xix
xx
1. GR
X Y Z
BGS BGS BGS
Dk Grltl
Kuvvetlendirici
YO1 Dk Grltl
Kuvvetlendirici
YO2
1
X
0
YO1
Y01
Y 0-Y01
YO2 Y02
Z
0-Y01-Y02
Bu almada tasarlanan devre, bir alc katnn ikinci kat kartrcs olarak
istenmitir. Kartrcnn isterleri, 3 dB dntrc kazanc, en az 20 dBm k
nc derece kesiim noktas, en fazla 13 dB grlt says ve 50 giri iin
empedans uyumu olarak belirtilmitir. Giri iaretinin skl 2.15 GHz, istenen k
ara skl ise 200 MHzdir.
2
2. KARITIRICININ ANALZ
a(t ) b(t )
AB
cos1 2 t 1 2 cos1 2 t 1 2 (2.4)
2
eklinde yazlabilir [1]. Devrenin kullanm amacna gre, oluan bu iki iaretten biri,
devre kna yerletirilen BGS ile szlr.
3
Kartrclarn tanmlanmasnda kullanlan belirli parametreler vardr. Grlt
Says(GS), giriteki iaret ve grlt glerinin oran ile kta oluan iaret ve
grlt glerinin orannn oran olarak tanmlanr. Uygulamalarda kartrc
devreleri alc katnn ilk ya da ikinci kat olarak kullanldklarndan, alc devresinin
duyarll asndan grlt saysnn olabildiince dk tutulmas amalanr.
Dntrc G Kazanc, AS k gcnn kaynaktan elde edilebilir RS giri
gcne oran olarak tanmlanr. Kartrcnn giriine uygulanabilecek g aral,
dinamik aralk olarak tanmlanr [3].
Temel olarak kartrclar etkin ve edilgen olmak zere iki farkl bekte
deerlendirilirler. Edilgen kartrclarn dntrc kazanlar birden
kk(kaypl) ve grlt saylar da etkin kartrclardan daha yksek olmasna
karn, i-modlasyon bozulumlar daha azdr (daha yksek OIP3 deerleri).
Kartrclar ayrca Tek-Dengeli ve ift-Dengeli yaplar olarak da
deerlendirilmektedirler. Kaplar arasndaki yaltm, istenmeyen iaretlerin
bastrlmas ve dorusallk asndan ift-Dengeli kartrclar, Tek-Dengelilere gre
stnlk gsterirler [1].
4
bantsyla verilebilir [3]. Eleman zerindeki gerilimin dardan uygulanan
v1 (t ) V1 cos(1t ) ve v2 (t ) V2 cos(2t ) iaretlerinin toplam olmas durumunda bu
akm;
Giri kapsna ayn anda sklklar ve olan iki farkl iaret uygulandnda,
kta sklklarnda kartrma rnleri ortaya kar. Bunlar
ki-Ton i-modlasyon rnleri olarak adlandrlrlar [3]. Bu rnlerden en nemlisi:
IM 3 1 (221 22 ) (2.7)
5
ekil 2.1 : a. Temel anahtarlamal kartrc devresi b. k akm dalga ekli [4]
I0
i1 v2
1 e VT
(2.8)
I0
i2 v2
1 e VT
1 1 v2
i0 i1 i2 I 0 v2
v2 I 0 tanh (2.9)
2VT
1 e VT
1 e VT
v2
i0 I 0 (2.10)
2VT
6
Ancak, kartrc uygulamalar iin genelde v2 VT seildiinden, (2.9) bants
v2 nin deerinine bal olarak i0 I 0 olacaktr. Kuyruk akm sabit bir I 0 deeri
v2 v v
i0 I 0 g mc v1 tanh I 0 tanh 2 g mc v1 tanh 2 (2.11)
2VT 2VT 2VT
v0 g mc v1RC x S (t ) (2.12)
olarak yazlabilir. Burada S(t); temel skl peryodik olarak deien v2 iaretinin
sklna eit olan Simetrik Anahtarlama Fonksiyonudur. Bu tr kartrclar kazan
kat (Gei-letkenlii Kuvvetlendiricisi) ve anahtarlama kat olarak adlandrlan iki
ksmdan oluur. Bu trden kartrcnn ematik yaps ekil 2.2de
gsterilmitir. (2.11) bantsndan grlebilecei gibi, v2 giriiyle orantl bir
7
ekil 2.3 : Gilbert Hcresi [6]
Tek dengeli yapnn iki tanesi kullanlarak oluturulan ve v1 girilerinin dengeli
(simetrik) olarak uyguland yap kaynakalarda Gilbert Hcresi (ekil 2.3) olarak
anlmaktadr. Buradaki v2 girilerine dengeli yerel osilatr iareti uygulanr. VYO1
geriliminin yeterince byk, VYO2 iaretinin ise yeterince kk olduu anda, Q3 ve
Q5 tranzistorlar iletimde, Q4 ve Q6 tranzistorlar ise kesimdedir. Bu durumda Q3 ve
Q5 kapal anahtarlar olarak alarak Q1in akmnn R1 ve Q2nin akmnn R2
zerinden akmasna neden olur ve bu durum da AS ularndan kn ald farksal
kuvvetlendirici yaps olutururlar. VYO2 geriliminin yeterince byk, VYO1
geriliminin ise yeterince kk olduu an dnldnde, Q4 ve Q6 tranzistorlar
iletimde, Q3 ve Q5 tranzistorlar ise kesimdedir. Bu durumda da bir farksal
kuvvetlendiricisi yaps olumutur ancak, nceki duruma gre k -1 ile arplm
durumdadr. Sonuta Gilbert hcresi knda, RS giri iareti temel skl yerel
osilatr sklnda olan ve zaman domenine gre +1 ve -1 deerlerini alan simetrik
kare dalga (anahtarlama fonksiyonu) ile arplarak olumaktadr [6].
RS giri geriliminin ;
8
eklinde deitii varsaylabilir. Simetrik Anahtarlama Fonksiyonu Fourier serisine
aldnda,
4 cos(3YO t ) cos(5YO t )
S (t ) cos(YO t ) ... (2.14)
3 5
ekil 2.4teki devre gz nne alndnda, T2 anahtar RS iaret akm IRSi 0 ile 1
ise IRS i S (t ) nin 1800 telenmii olan S (t TYO / 2) ile arparak I2 akmn
9
oluturur [7]. Bu iki fonksiyonun fark S (t ) S (t ) S (t TYO / 2) Simetrik
Anahtarlama Fonksiyonu olup, Fourier Serisi olarak yazldnda;
4 1 1
S (t ) CosYOt Cos3YOt Cos5YOt ... (2.16)
3 5
k akmlar;
I1 (t ) I RS (t ) x S (t ) (2.17)
TYO
I 2 (t ) I RS (t ) x S (t ) (2.18)
2
VIKI (t ) I RS (t ) x RC S (t ) (2.20)
4 1
VIKI (t ) I RF (t ) x RC (cos YOt . cos 3YOt....). (2.21)
3
bulunur. I RF (t ) iin;
2
VAS (t ) g m1 RCVRS cos (RS YO )t (2.23)
10
VAS 2
AV g m1RC
VRC (2.24)
Anahtarlama fonksiyonu olarak gerek kare dalga yerine, ekil 2.5de gsterilen
sinusoidal olarak deien bir yerel osilatr iareti uygulandnda, T sresi boyunca
her iki tranzistor da iletimde olacandan T1 tranzistoru tarafndan retilecek akm
ikiye ayrlr ve ortak iaretler artacandan kta bunlar grnemez. Dolaysyla, bu
sreye bal olarak kazan decektir. T gecikme sresi gz nne alndnda
(2.25) bants;.
2 2T
AV g m1 RC 1 (2.25)
TYO
Kazancn azalmasna neden olan dier etken, giri tranzistorunun kollektr ucundan
grlen toplam kapasitedir. ekil 2.6daki P dmnde grlen kapasite;
11
ekil 2.6 : Cp zerinden RS akmnn kayb
2 2T g m2
AV g m1 RC 1
TYO C p 2 g m2 2
2 (2.27)
P0top ( AS )
F
P0 kaynak ( AS ) (2.28)
12
grltye rnek olarak verilebilir. Son olarak da YO tarafndan retilen grltlerde
AS kna aktarlabilmektedir [8]. YO periyodu boyunca AS kna aktarlan
grlt gleri sabit deildir. ekil 2.7de grld zere, YO gerilimin yksek
olduu deerlerde, baskn grlt kazan katndaki tranzistorlardan gelir [8]. YO
farksal ift tranzistorlarnn kesim ve saturasyon blgeleri arasnda anahtarlanmasn
salad iin bu beklenen bir davrantr. ki durumda da tranzistorlarda kazan
olmad iin grltye ok az katkda bulunurlar. Ayrca RS giriten itibaren kazan
bu koullarda en fazladr. Bu yzden keskin ekilde anahtarlanan yksek genlikli YO
iareti, yksek iaret grlt oran elde etmek iin gereklidir [9].
Fakat sonlu ykselme ve dme sresi boyunca kare dalga eklinde ya da sinusoidal
yerel osilatr iaretleri iin, yerel osilatr gerilimi sfrdan geer. Bu sre boyunca
anahtarlama tranzistorlar etkin blgede alrlar. Bu blgede tranzistorlar
kuvvetlendirici olarak alr ve kollektr sama grlts, baz direnlerinden
kaynaklanan sl grlt gibi yerel osilatr ve anahtarlama trasistrlerinde oluan
grlt baskn hale gelir [10].
13
ekil 2.8 : Grlt analizi iin kullanlacak etken kartrc
Keskin bir yerel osilatr iaretinin yarm periyot sresince kartrc devresine
uygulanmas durumunu ekil 2.8de gsterilmitir. Cpparazitik kapasitesi,
olarak ifade edilebilir [7]. Bu durumda devre, ekil 2.9da grld gibi P
dmnde Cp byklnde bir kapasiteye sahip kaskod yapya dnr. T2
tranzistorunun rettii grlt akm Vn,T2CpSe eittir. Bu grlt ve T1
tranzistorunun rettii grlt 0 ile 1 arasnda deien kare dalga ile arplarak ka
iletilir. Dier yar YO periyodunda ise T3 tranzistoru baskn rol oynayarak grlt
oluumuna sebep olur.
Daha gereki bir yaklamla, keskin olmayan bir yerel osilatr iareti devreye
uygulandnda T2 ve T3 tranzistorlar belli bir sre ayn anda iletimde olurlar. Bu
durumda ekil 2.10 da grld gibi, T1 tranzistorunun oluturduu grlt farksal
k sebebiyle ortak iaret olduu iin kta grlmeyecek, fakat T2 ve T3
tranzistorlarnn sebep olduu grlt kuvvetlendirilerek ka iletilecektir [7].
14
ekil 2.9 : Bir tranzistor kesimdeyken grlt etkisi ve edeer devresi
15
ekil 2.11 : Giri katnn ve bir anahtarlama tranzistorunun grlt etkisi
Vn2, X
2
1 2
I n,T 1 Vn2,T 2C p2 2 RL2 4kTRL (2.30)
2 gm2
AV g m1RL
C p2 2 g m2 2 (2.31)
2kT 2 2 2
2kTgm1 C p RL 8kTRL
Vn2,gir g m2
2 (2.32)
4 2 2 g m2
g m1 RL 2 2
2 C p g m2 2
Vn2, farksal 2 2kTgm 2 RL2 4kTRL (2.33)
2T C p2 2 2
R L 8kTRL 1 2T
8kT 0.5 xg m 2 R R L
2
L TYO
2kT g m1
g m2 TYO
V n2, gir 2
2T
2
4 g m2 (2.34)
2
g R 2
1
C g
2 m1 L 2 2 2
p m2 TYO
ekil 2.12 : Grlt hesab iin kullanlan ksmi dorusal dalga ekli
17
Anahtarlama tranzistorlarnn oluturduu ile belirlenen sama grlts
akm kollektr akmnn azaltlmasyla azalr. Tersine, RS kattaki tranzistorlarn
Vcc
RL RL
Is
YO
Cp
V_RS Rs
2.5 Dorusallk
18
IM rnlerinin sklklar YO (2 RS 1 RS 2 ) ve YO (2 RS 2 RS 1 ) olup, kta
19
20
3. KARITIRICI DEVRESNN TASARIMI
ekil 3.1de tasarlanan devrenin blok diyagram verilmitir. Giri gei iletkenlii
kat olarak bir etkin balun tasarlanmtr. Balun kndan alnan farksal k Gilbert
Hcresinin farksal giriine uygulanmtr. Gilbert Hcresinin k dallarndan alnan
akmlar ayn evreye getirilerek toplanm, devrenin kna da bir alak geiren
szge yerletirilerek ara sklk k iareti elde edilmitir.
F
k Alak Eviren Evirmeyen
AS k iareti Geiren + Kuvvetlendirici Gilbert Kuvvetlendirici
Szge G E Kat D Hcresi C Kat
A B
Giri Gei
RS giri letkenlii Kat
iareti Etkin Balun
Yaps
2
VRS
Pgiri (3.1)
4R S
ekil 3.2de OE l devrenin baz akm gz ard edildiinde giri akmnn tepe deeri
iin;
21
A B
R2
T1
Vcc
Ri
Cg T2 R1
C1
C2
Rin
RS Giri Kaps
RE
RE2
1 1 1
(3.3)
R in R E R
22
eitsizliinin salanmas gerekir. Bu sonu (3.2)de kullanldnda, RE direnci 170
olarak hesaplanabilir. Bu durumda OBl devrenin giriinden grlmesi gerekli giri
direnci, Rin= 50 alnarak (3.3) bantsndan Ri= 71 olarak hesaplanr.
Gilbert hcresine giden kollardan (3.5)te grld gibi eit DC deerde akm
gemektedir. IQ, T1 ve T2 tranzistorlarnn emetr akm olmak zere;
1 VT
re
g mQ IQ (3.6)
Giri empedans uyumunun salanmas iin kapasitif gerilim blc ile ileri-besleme
uyguland belirtilmiti. Gerilim blcnn diren yerine kapasite ile
gereklenmesi, bu yapnn devrenin grlt saysna etkisini en aza ekmitir.
Ayrca, ileri ynde zt besleme yntemi kullanld iin devrenin dinamii de
arttrlmtr.
Kapasitif gerilim blc iin OBl devrenin giriinden akacak olan akm (3.7)de
gsterildii gibi yazlabilir;
C2 1
vin vin g mQ vin (3.7)
C1 C 2 R
v C C2 1
R in 1 (3.8)
iin C1 g mQ
23
Yerel osilatr gerilimi, devrenin kutuplama koullar nedeniyle 3.5 V DC deerin
zerinde salnacaktr. Gilbert hcresindeki anahtarlama tranzistorlarnn yeterince
iletimde olmas iin, 0.1V genlikli yerel osilatr gerilimine gereksinim
bulunmaktadr. Bu nedenle, tranzistorlarn kollektr gerilimleri 3.6Vdan dk
olmamaldr. Gilbert hcresinin yk direnleri de bu dnceden yola klarak
RL=155 hesaplanr.
Vcc
R12
R8 R10
F
T9
C6
T8
C R11
C5
R13
R7
R9
24
Vcc
R5
C3 R6
C4
E
T7
D
R4
R3
L2 L1 L2
G
Cc Cc
AS k areti
Szge s parametreleri
5 5
0 2
Araya girme kayb (dB)
-10 -4
Loss(dB)
-20 -10
Insertion Loss
kayb
-30 -16
Return
Geri dn
-40 -22
-50 -28
-60 -34
-70 -40
0 200 400 600 800
Sklk (MHz)
Frequency (MHz)
25
3.2 Grlt Hesaplamalar
Kaynak grlts
Kuvvetlendirici
katndan gelen
grlt. OBl
R R tranzistor ve RE1
direncinden oluur.
Anahtarlama
tranzistoru T2den
gelen AS grlts
Kuvvetlendirici
katndan gelen
grlt. OBl
tranzistor ve RE2
direncinden oluur.
Anahtarlama
tranzistoru T3den
gelen AS grlts
Yani,
1
Z in
2
2C P (3.10)
2 2
g mst
26
olarak belirlenmiti. Anahtarlama tranzistorunun emetrnde grlen
grlt gerilimi, parazitik kapasite Cp dolaysyla bir grlt akm olumasna sebep
olur. Bu noktadaki grlt geriliminin kayna anahtarlama tranzistorlarnda oluan
kpram grltsdr. Bu grlt hem AS hem de RS bileen iermektedir. OBl
ksmdaki tranzistorlar da bu iki sklk bileenine sahiptirler. Bu yzden ve
toplam grlt fonksiyonunda iki kez yer alrlar. Devrenin bir yarsnn grlt
kaynaklar ekil 3.7da gsterilmitir.
2 g m st 2 RS 2 C P 2 2 4
RS 2 C P 2 R L 2 2
g m st R L
2
1 1
vn2 4kTRL v S
2 2
g m st RS C P 4 R
2 2 2 2 2
4
2 2 2
1 g m st R L 1 RL (3.11)
in 2
2
v nRF
2
RS C P R L in 2
2 2 2 2
g m st RS C P
2 2 2 2
2
4
RS 2 C P 2 R L 2 2
g m st R L
2
1 1
vn3 vS
2 2
g m st RS C P 4 R
2 2 2 2 2
4
Vcc
RL RL
Vn2
T2 T3
Vn3
Cp in1
Gei
letkenlii Kat
ekil 3.7 : Devrenin bir yarsnn grlt kaynaklar
27
2 2
g m st RL
2
1 1
vS
g mst RS C P 4 R
2 2 2 2 2
PNS ,k 2 2 2
(3.12)
g mst RL 1 1
vS g
2
2 4 R 2
m st RS C P
2 2 2
i1 2kTgm alt
2
(3.14)
A B
in1 in2
i1 T1
R1 R2
Vcc
Cg i2
Ri
T2 C1
C2
Rin
RS Giri Kaps
ie1 RE
ie2
RE2
olumasna neden olur. Ri emetrden grlen direntir ve (3.15) ile gsterilen bir
grlt olumasna sebep olur.
28
2 2
R 1 2 R 1
2
i 1, T i1 S i1 i1 S 1 (3.15)
2 R 2 R
RE1 (3.16)
2
RS 1
ie21,T ie1
2
4 R 2 (3.17)
2
1 2
ie 2
2
R E 2 // g m alt ie 2 2 (3.19)
g m alt
2
1
i 2 R E 2 // g m alt 1 0
2
(3.20)
g m alt
1
in 2 ie 2 4kT
2 2
RE 2 (3.21)
29
Vcc
RL RL
C4
C
D C5
Rn Rn
T3 T4 T5 T6
Cs Cs
3.5V DC
Yerel Osilatr Girii
A B
katndan gelen grlt ile, anahtarlama katndan gelen grlt ise ile
30
1
2
g m st R L
2
2T
PNT ,k i n1
2
1
g m st RS C P
2 2 2 2
TYO
1 2T 2 R
2
2T
v nRS
2
RS 2 C P 2 R L 2 i n1 L 1
2
TYO 4 TYO
RS 2 C P 2 R L 2 2T
vn2 4kTRL
2
4 TYO
2 2T
2 2
g m st R L 1 1
v S 1
TYO g m st RS C P 2 4 R 2
2 2 2
(3.22)
2T 1 2
g m st R L
2
in 2
2
1 2
TYO g m st 2 RS 2 C P 2
1 2T 2 R
2
2T
v nRS
2
RS 2 C P 2 R L 2 in 2 L 1
2
TYO 4 TYO
RS 2 C P 2 R L 2 2T
vn3
2
4 TYO
2 2T
2 2
g m st R L 1 1
v S 1
TYO g m st RS C P 2 4 R 2
2 2 2
2 2
g m st RL
2
1 1
vS
2T g m st RS C P 4 R
2 2 2 2 2
PNS ,k 21
TYO 2
g m st RL
2
1 1
(3.23)
vS g
2
2 4 R 2
m st RS C P
2 2 2
PNT ,k (3.24)
GS 10 log
P
NS ,k
31
ekil 3.10 : Anahtarlama tranzistorlarnn tmnn ak olduu zaman
VP cos Vp 0.05 (3.25)
2
ekil 3.11da gsterildii gibi, denklem (3.25)den yaklak olarak 0.05 radian
Bu hesaplamalar ile devrenin grlt saysnn akm azaltma ileminden nce 16.3
dB olarak hesaplanr. Gei iletkenlii katndaki ikinci tranzistorda oluan grlt,
gerilim blc yapsndaki kapasitenin zerinden ilk tranzistordaki grltye
eklenerek bu grltye azaltc etki yapar. Yukardaki hesaplarda bu korelasyon
32
dikkate alnmad iin devrenin grlt saysnn 16.3 dBden az olmas
beklenmektedir.
s11 (dB)
s11 parameter
-17.8
-17.9
-18
-18.1
p1
-18.2
-18.3
1.9 2 2.1 2.2 2.3 2.4
Frequency (GHz)
sklk (GHz)
33
GS
NF(dB)
12.2
12.1
12
11.9
11.8
11.7
p1
11.6
-6 -4 -2 0
Power (dBm)
Yerel Osilatr Gc (dBm)
2.96
2.94
2.92
2.9
-5 -4 -3 -2 -1 -0.8
Yerel Osilatr Gc (dBm)
Power (dBm)
34
OIP3
OIP3 (dBm)
30
25
20
15
10
p1
5
-5 -4 -3 -2 -1 0
YerelPower
Osilatr
(dBm)Gc (dBm)
Akm azaltma ilemi uygulanmadan nce ve sonra elde edilen benzetim sonular
ekil 3.16, ekil 3.17, ekil 3.18 ve ekil 3.19de verilmitir.
DntrcKazanc
Kazanc (dB)DB(|LSSnm(PORT_3,PORT_1,-1_1,1_0)|)[X,1]
akim azaltmadan once
4 DB(|LSSnm(PORT_3,PORT_1,-1_1,1_0)|)[X,13]
akim azaltmadan sonra
p2
0
p1
-1
2.1 2.12 2.14 2.16 2.18 2.2
sklk (GHz)
Frequency (GHz)
35
DB(|S(1,1)|)[X,13]
s11parametresi
s11 (dB) akim azaltmadan sonra
-16.5
-16.6 DB(|S(1,1)|)[X,13]
akim azaltmadan once
-16.8
-17
-17.2 p1
-17.4
-17.6
-17.8
-18 p2
-18.2
2.1 2.12 2.14 2.16 2.18 2.2
sklk (GHz)
Frequency (GHz)
DB(NF_SSB0(0,2,1,2,0))[1,X]
GS GS
(dB) GS_akim azaltmadan once.$F_SPEC
18 DB(NF_SSB0(0,2,1,2,0))[1,X]
GS_akim azaltmadan sonra.$F_SPEC
16
14
12 p2
p1
10
-6 -4 -2 0
Yerel Osilatr Gc
Power (dBm) (dBm)
36
OIPN(PORT_3,-1_0_1,1_-2_1,3)[1,X] (dBm)
ip3_once
OIP3OIP3
(dBm)
OIPN(PORT_3,-1_0_1,1_-2_1,3)[1,X] (dBm)
30 ip3_sonra
20
10
p2
p1
0
-10
-5 -4 -3 -2 -1 0
Yerel Osilatr
PowerGc
(dBm) (dBm)
Farkl akm azaltma oranlarnda elde edilen sonular ekil 3.20, ekil 3.21 ve ekil
3.22de verilmitir. Kullanlan oranlar %50, %60 ve %70tir.
Dntrc Kazanc
Kazanc (dB)
DB(|LSSnm(PORT_3,PORT_1,-1_1,1_0)|)[X,11]
akim azaltmadan once
4 DB(|LSSnm(PORT_3,PORT_1,-1_1,1_0)|)[X,11]
akim azaltmadan sonra
DB(|LSSnm(PORT_3,PORT_1,-1_1,1_0)|)[X,11]
akim azaltmadan sonra_350
p2 DB(|LSSnm(PORT_3,PORT_1,-1_1,1_0)|)[X,11]
p3
p1
p4
3 akim azaltmadan sonra_450
-1
2.1 2.12 2.14 2.16 2.18 2.2
sklk (GHz)
Frequency (GHz)
ekil 3.20 : Farkl akm azaltma oranlarnda yk direncinin deitirilmesi ile elde
edilen kazan
37
DB(|S(1,1)|)[X,13] DB(|S(1,1)|)[X,4]
akim azaltmadan sonra akim azaltmadan sonra_350
DB(|S(1,1)|)[X,2]
akim azaltmadan once
DB(|S(1,1)|)[X,4]
akim azaltmadan sonra_450
s11
s11 (dB)
parametresi
-17
p1
-17.5
p4
-18 p2
-18.5 p3
-19
2.1 2.12 2.14 2.16 2.18 2.2
sklk (GHz)
Frequency (GHz)
ekil 3.21 : Farkl akm azaltma oranlarnda giri yansma katsaysnn deiimi
DB(NF_SSB0(0,2,1,2,0))[1,X]
GS_akim azaltmadan once.$F_SPEC
GS GS
(dB) DB(NF_SSB0(0,2,1,2,0))[1,X]
18 GS_akim azaltmadan sonra.$F_SPEC
DB(NF_SSB0(0,2,1,2,0))[1,X]
GS_akim azaltmadan sonra_450.$F_SPEC
DB(NF_SSB0(0,2,1,2,0))[1,X]
GS_akim azaltmadan sonra_350.$F_SPEC
16
14
12 p4
p2
p3
p1
10
-6 -4 -2 0
Yerel Osilatr Gc (dBm)
Power (dBm)
38
izelge 3.2 : Benzetimde kullanlan eleman deerleri
Eleman Deeri
Cs 2 pF
155
RL
Vcc 5V
C4, C5 5pF
Rn 400
C1 0.02 pF
C2 0.09 pF
RE 170
RE2 71
R1 10K
R2 18K
Cs, C3 20 pF
R7 7K
R8 15K
R9 100
R10 110
R11, R4 1.4K
R12,R6 3.5K
R13,R3 50
R5 70
L1 50.20 nH
L2 24.07 nH
Cc 16.6 pF
39
ekil 3.23 : Benzetim iin kullanlan devrenin tam hali
40
4. SONULAR
Tez almas kapsamnda Gilbert Hcresi yapsn temel alan bir kartrc devresi
tasarlanmtr. Devreye ait grlt saysnn matematiksel ifadesi karlm ve
benzetim sonucu ile hesaplanan deerin uyumlu olduu grlmtr. Devrenin
grlt saysnn azaltlmas iin anahtarlama tranzistorlarnn kollektr akmlarnn
azaltlmas yntemi denenmi, bunun iin Gilbert Hcresinin giri dallarna
dorudan sabit direnler zerinden akm eklenmitir. %50, %60 ve %70 akm
azaltma oranlar iin benzetimler yaplmtr. Grlt saysnn kollektr akm ile
doru orantl olarak azald grlm ve denenen yntemin baarl olduu
sonucuna ulalmtr. k nc dereceden kesiim noktasnn da farkl
kutuplama deerleri iin bu yntemle iyi sonu verdii grlmektedir. Giri yansma
katsays da akm azaltma orannn arttrlmas ile iyilemitir. Benzetim sonularna
gre, hesaplanan eleman deerlerinin optimizasyonu ile amalanan deerlere ok
yakn sonular elde edilmitir. 2.15 GHzlik RS iaretinin, -2.5 dBm gcnde ve 2.37
GHz sklndaki yerel osilatr iareti kullanlarak %60 orannda akm azaltma ile
200 MHz k ara sklk aktarmnda kullanlan kartrc devresinin baarm
parametreleri izelge 4.1de gsterilmitir.
3.0dB
evrim kazanc 3.0dB
Grlt says 15.2dB 11.75dB
Giri yansma katsays
-17.2dB -18.1dB
(s11)
k nc derece
4.2dBm 25.1dBm
kesiim noktas
41
42
KAYNAKLAR
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kartrc tasarm, (yksek lisans tezi), T.
[2] Ordu, M. T., (1995). kinci harmonik savaktan pompalamal dalm
parametreli kartrc tasarm,(yksek lisans tezi), T.
[3] Erdodu, M., (1994). Tek yan band yukar kartrc tasarm, (yksek lisans
tezi), T.
[4] Rogers, J. and Plett, C. (2003). Radio Frequency Integrated Circuit Design,
Artech House, 396.
[5] Gilmore, R. and Besser, L., (2003). Practical RF Circuit Design For Modern
Wireless Systems, Artech House, Vol. 2, 480.
[6] Whites, K. W., (2010).Mixers, Gilbert Cells, (27. ders notu), South Dokato
University of Mines and Technology.
[7] Razavi, B. (2012). RF Microelectronics, Prentice Hall, Srm 2.
[8] Razavi, B. (1998). RF Microelectronics, Prentice Hall, Srm 1.
[9] Abdelghany, M. A. , Pokharel, R. K. , Kanaya, H. and Yoshida, K., (2009).
A Low Flicker-Noise High Conversion Gain RF-CMOS Mixer with
Differential Active Inductor, Korea-Japan MicroWave Conference
(KJMW-2009) Proceedings.
[10] Guerber, J., (2010). Design and Analysis of a Self Biased Flicker Noise
Cancelling CMOS Direct Conversion Mixer, ECE 621.
[11] Lee, T.H., (1998). The design of CMOS radio frequency integrated
circuits,Cambridge University Press,Srm 2.
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ZGEM
E-Posta: zehragulrucam@gmail.com
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