878 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO.
5, MAY 2012
Single Cycle Access Structure for Logic Test
Tobias Strauch
AbstractThis paper proposes a new single cycle access test
structure for logic test. It eliminates the peak power consumption
problem of conventional shift-based scan chains and reduces the
activity during shift and capture cycles. This leads to more real-
istic circuit behavior during stuck-at and at-speed tests. It enables
the complete test to run at much higher frequencies equal or
close to the one in functional mode. It will be shown, that a lesser
number of test cycles can be achieved compared to other published
solutions. The test cycles per net based on a simple test pattern
generator algorithm without test pattern compression is below 1
for larger designs and is independent of the design size. Results are
compared to other published solutions on ISCAS89 netlists. The
structure allows an additional on-chip debugging signal visibility
for each register. The method is backward compatible to full scan
designs and existing test pattern generators and simulators can
be used with a minor enhancement. It is shown how to combine
the proposed solution with built-in self test (BIST) and massive
parallel scan chains.
Index TermsAt-speed testing, low-power testing, on-chip
signal visibility, switching activity during test, test-time reduction.
I. INTRODUCTION
HE production test costs of chips become more and more
T dominant. The standard shift scan (SS) method is the most
popular test implementation within the last decades. It has been
tried to improve this approach in terms of test time, test data
volume and test power by optimizing the scan pattern, using
different scan chain structures, different scan support logic, or a
combination of these modifications.
Automatic test pattern generation (ATPG) for sequential
VLSI circuits is an NP-complete problem with an exponential
complexity. The complexity of combinatorial logic varies. Less
complex logic is tested within a few capture cycles, generating
an immense number of dont cares during the rest of the test,
even when test compression methods are used. Complex and
hard to test logic needs to be stimulated and captured quite
often but the pattern need to be shifted throughout the complete
scan chain. One approach to reduce test time is to use parallel
scan chain. This leads to a massive increase of parallel scan
chains to reduce the length of the scan chains. In order to further
reduce test data volume, a built-in-self-test (BIST) mechanism
is used. One example is embedded deterministic test (EDT)
proposed by Rajski et al. [1], which combines parallel scan
Manuscript received September 13, 2010; revised December 14, 2010 and
February 10, 2011; accepted February 28, 2011. Date of publication April 21,
2011; date of current version April 06, 2012.
The author is with R&D, EDAptability e.K., Munich 80538, Germany
(e-mail: tobias@edaptability.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2011.2134875
1063-8210/$26.00 2011 IEEE
chains with BIST and further proposes solutions to reduce
power by using a controller to allow a given scan chain to
be driven by a power-aware EDT-decompressor in [2] or to
reduce transitions in scan chains by using a ring generator in
[3]. However, the number of test cycles can still be reasonable
improved and parallel shift scan chains generate critical peak
power so that each shift cycle must be slowed down.
The aspect test time can be reduced by optimizing the test
pattern. Pomeranz et al. [4] demonstrate this by using limited
scan operations and transfer sequences. Chen et al. [5] combine
different pattern optimization techniques and a clock disabling
scheme to further reduce switching activity. Test pattern opti-
mization to reduce power consumption during test is another
aspect. A test pattern generation technique, which concentrates
solely on minimizing switching activity during scan test by as-
signing optimized values to dont care bits to limit transactions
is shown by Wang et al. in [6]. Almukhaizim et al. [7] pro-
pose dynamic scan chain partitioning and inserting delays in the
clock tree. Al-Yamini et al. [8] use segmented addressable scan
and disabling complete subtrees of the clock to solve the power
consumption problem. Lin et al. [9] reduce power consumption
during shift by a multilayer data copy scheme. However, most
of these methods require a large computational effort and are
therefore not applicable for multimillion gate designs or do not
simultaneous reduce switching activity and test time.
Another critical aspect of SS implementations is at-speed
testing. The high peak power during shift leads to an excessive
current due to high switching activity, which can lead to a
miss-classification of the circuit under test (CUT). This is
demonstrated by Sde-Paz et al. in [10]. The pattern reduction
for at-speed tests is proposed by Pomeranz et al. in [11] by test
compaction based on non-scan test sequences and the removal
of transfer sequences. The problem of a slow global scan enable
signal in SS is discussed by Ahmed et al. in [12] and solved
by implementing a pipelined global scan enable tree. However,
none of the methods fundamentally solve the problem of high
switching activity, a high number of test cycles and a slow
global scan enable signal simultaneously.
The aspects test power, test data volume and test time can
be simultaneously reduced with a modified hardware structure
known as random access scan (RAS). The enhanced hardware
allows the read and write of selected registers or set of selected
registers, which reduces the power problems during shift and
test time. Based on the initial idea in 1980 by Ando [13], three
major groups of RAS schemes can be found.
The first group uses basically one single address-decoder to
select each individual register in the design and an additional el-
ement (multiplexer, MUX) per register cell enables a hold mode
of each register. Baik et al. [14] show how test power, test data
volume and test application time can be reduced. Lin et al. [15]
present a two phase approach how to optimize the pattern based
STRAUCH: SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST 879

on bit flipping. A test pattern generation scheme based on seg- implementation can improve the bring-up-time and in-system
ment fixing counter reseeding is demonstrated in [16]. However, tests.
the fact that each cell needs to be accessed individually gener-
ates an unaffordable routing overhead. II. CONTRIBUTION AND PAPER ORGANIZATION
The second group addresses each register individually by
This paper presents a novel scan cell register for logic tests
using an (or row) and a (or column) address decoder with
combined with a novel scan cell routing architecture. The struc-
an additional combinatorial element (for instance AND gate)
ture allows a single cycle access (SCA) to individual register
per register cell. The cell values can be individually read by an
sets. This access scheme is fundamentally different to SS. It can
additional signal driven by a tristate logic added to each register
be compared to a memory with single cycle synchronous write
cell. Hu et al. propose a variable-to-fixed run-length decoding
and asynchronous read functionality, whereas the remaining
technique applied on RAS in [17] and a clustered RAS structure
memory content (registers) does not change. Unlike with a cer-
in [18]. A modified T-Flip-Flop is shown in [19] to allow the
tain number of shift cycles in shift-scan designs, the values can
overlap of the test response read out with the loading of the next
be read and written within one single cycle. It will be shown,
test input patterns within the same memory addressing cycle. A
that this method can easily be integrated in todays standard
very similar modified scan register is proposed by Mudlapur et
flows. The structure needs less test cycles to reach a certain or
al. in [20] to reduce area overhead of the RAS. However, these
full coverage and the power consumption during tests is in the
proposals have in common, that the - and -line select routing
range of the one in functional mode. This allows higher test
is unaffordable, the individual register cells are enhanced by
frequencies and leads to more realistic test conditions closer to
multiple logic elements which generates an unaffordable area
the functional chip behavior during stuck-at and at-speed tests.
overhead and the readout is done using tristate logic.
The proposed structure is applicable for pattern driven tests
The third group uses a row decoder and a column decoder to
and for BIST. The paper provides reasonable data but is not
address individual registers. Additionally the read/write mech-
limited to a frozen solution. It also discusses various trade-offs
anism is enhanced with two signals per column, driven by a
of different alternatives. Logic test is a wide field and different
tristate driver, connected to the internal latch cells of the reg-
users have different preferences. A reference example based on
isters via tristate logic and an individual sense amplifier per
992 registers is used and should guide through the paper.
column. Different variations are discussed. Hu et al. propose
This paper is structured as follows. In Section III, SCAh-
a single read/write signal in [21] called localized random ac-
Structure with Hold Mode the single cycle access test structure
cess scan. Saluja et al. [22] take advantage of basis vectors and
is explained. The feasibility, area, test cycles, power consump-
linear algebra to further significantly optimize test application in
tion, and debugging capabilities of this solution is compared to
RAS by performing the write operations on multiple bits con-
alternative state-of-the-art methods. In Section IV, SCA-Struc-
secutively. They also propose partitioned grid random access
ture without Hold Mode demonstrates further solutions to over-
scan in [23], progressive random scan in [24] and further mini-
come the area disadvantage of the proposed method. The ad-
mize test application time in [25]. Based on this, Voyiatzis et al.
vantages of the SCAh-structure and the lower area overhead of
present an output response compaction scheme which results in
the SCA-structure are combined and presented in Section V,
lower hardware overhead, while at the same time eliminates the
Gated SCA-Structure. Sections VI, Running Page Tests in
problem of unknown values in [26]. Baik et al. [27] enhance the
Parallel and VII, Address Controlled BIST, discuss solutions
register with a latch structure to test for path-delay faults. How-
which can be applied to todays test requirements. The num-
ever, next to the routing and area overhead compared to standard
bers in Section VIII, Results, demonstrate the advantage of
scan approaches, the enhanced read and write mechanism with
the lower test cycles per net resulting from the proposed solu-
tristate drivers, cell internal tristate logic, and sense amplifier
tion and Sections IX, Discussion, and X, Conclusion, finish
per column is very timing sensitive. This massive use of tristate
the paper.
logic connected to internal register cell-nets and sense ampli-
fiers generate timing critical signal slopes and is not easy to in-
tegrate in todays static timing analysis flows for multimillion III. SCAh-STRUCTURE WITH HOLD MODE
gate designs. Further on, launch-on-shift (LOS) based at-speed
testing is not possible for this group of RAS implementations. A. SCAh-FF
Built-in-self-test (BIST) is a solution to reduce test data The key element of the single cycle access structure with hold
volume and can further on reduce the test access pins for the mode (SCAhS) is the signal cycle access register (Flip-Flop,
CUT dramatically. The embedded logic test (EDT, [1]) method FF) with hold mode (SCAh-FF). It is based on a standard scan
is a well established method. BIST based on a RAS is examined register (S-FF) and uses two more 2-to-1 multiplexers. The new
by Yao et al. in [28]. A new test implementation must therefore SCAh-FF can be seen in Fig. 1.
be useable in a BIST environment. The SCAh-FF has one more input and one more output com-
Next to the aspects already mentioned, the debug capabilities pared to the standard shift register (S-FF). The inputs clock
of chips can have an impact on the bring-up-time and in-system {clk}, data-in {di}, and scan-in {si} still exists. The scan-enable
tests. Some techniques combine the test structure with debug is now a 2 bit bus {se[0:1]}. An additional scan output pin {so}
features, as shown in commercial available products [29]. How- is added. The reset input and inverse output pins are not shown.
ever, additional features for debugging provided by a new test The internal logic enables the register to run in one additional
880 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 5, MAY 2012
Fig. 1. SCAh-FF based on an S-FF.
TABLE I
TRUTH TABLE OF SCAh-FF
hold mode, whereas the additional output multiplexer can by-
pass the register to directly drive the value of {si}. The resulting
functionality is best explained by a truth table (see Table I).
In functional mode , the register cap-
tures and { } follows { } (usually stable). In read mode
{ } has the value of { } so that { } can be read out asyn-
chronously. In the event of the relevant clock edge, the register
captures { }. In hold mode, { } follows { }, and the reg-
ister remains in the state { }, capturing its own value. When
, the registers captures { } and { }
changes to the new value of { } (sync. write/read mode).
The slave latch of a FF is usually connected to the output
driver of the data-out pin and/or an inverting driver for the
inverse-data-out pin. The internal multiplexer for the SCAh-FF
(shown in Fig. 1) can also be driven by this slave latch output.
The fan-out number of the data-out pin (or inverse-data-out
pin) refers to the number of input pins which are driven by the
SCAh-FF data output drivers.
B. SCAh-FF Connectivity
Fig. 2 shows the SCAh-FF and its connectivity. The two
major differences are, that the scan-in { } is now connected to
a dedicated scan-out { } of the preceding register in the scan
chain and the register { } inputs on the same scan depth are
connected to the same line-select { } signal, which is driven
by a 1 out of decoder. SCAh-FF connected to the same
line-select signal are considered to be on one line. If { } is
0, no line is selected. { } of each SCAh-FF is connected to
the global scan enable signal { } (comparable to the global
scan enable signal of shift-scan structures). The output of the
address decoder is connected to the { } pin of the registers
on one particular line. Instead of shifting the data through the
scan chain, all registers on the same scan depth, enabled by
the same line-select signal can be read or written with a single
cycle access. Additionally, unselected registers remain in hold
mode.
From this structure four different kinds of cycle modes result.
Fig. 2. SCAhS connectivity.
1) When { } is low and { } is 0, the design works in
normal functional mode (Table I, line 2).
2) If a specific address is given (asynchronous read), the reg-
ister values on the selected line are passed to the scan-out
bus { }. This mode is called asynchronous read mode
(Table I, line 3).
3) When { } is high and { } is 0 (no line selected), the
design remains in hold mode and no register value changes
during an clock edge (Table I, line 4).
4) If a specific address is given at a relevant clock edge
and { } is high, the scan-in values { } are captured
by the registers on the selected line (synchronous write)
and scan-out { } is driven by the captured register
value (read). This mode is called synchronous write/read
(Table I, line 5).
The structure is backward compatible to known shift scan
operations if { } is set to 1 at the beginning and automatically
incremented after each shift cycle. The shift-in data can be
written continuously throughout the scan area and the scan-out
data can be read at the same time. A capture cycle can also be
applied to all registers at the same clock edge (functional mode).
The setup time of the SCAh-FF equals the one of the S-FF,
because no additional logic is added to the relevant timing path
through { }. The fan-out of { } is reduced by one because
{ } does not drive the { } of the succeeding register, which
is usually the case in SS. The new scan-out { } drives the { }
of the succeeding register in the scan chain and has a constant
fan-out of 1. The scan chain is decoupled from the functional
logic.
C. SCAh-FF Page Organization
The SCAhS enables single cycle read/write accesses to the
individual register line. The test structure is now organized in
pages to achieve a read/write access at design speed or at a
reasonable test speed. The page depth equals the scan chain
depth (SD = number of SCAh-FF connected to one chain on
one page). Assuming it is 31. Multiplied with the scan width
(SW = number of scan chains on one page, for instance 32), the
resulting number of SCAh-FF is 992 per page.
STRAUCH: SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST 881

In this rather extreme compact case, the page uses a global TABLE II
1-out-of-31 address line decoder. A page selector { } selects CELLS AND AREA OF CORES WITHOUT TEST INSERTION
the individual page and drives the scan input bus signals and
line select { } signals (AND-ed) only of this particular page.
{ } can be driven by a register which is set by a dedicated
test control logic. If not selected, the page remains inactive to
reduce activity. The scan output buses of all pages { } are
bit-wise XOR-ed with the { } of other pages to generate the
global scan-out bus { }. If the page is inactive, the XOR-tree
passes the value of previous pages unchanged since all { } bits
of an unselected page are 0.
With the page organization, the relevant timing paths become
clear. During a read, the registers are selected by the line-se-
lect signal and drive the scan-out bus { } through a multi-
plexer chain of the succeeding registers and the page-scan-out TABLE III
bus { } through the XOR-tree. During a write, the scan-in bus AREA AND CELL PINS PER LOGIC UNIT OF CORES WITH TEST INSERTION
{ } values are passed through the AND-selector and the multi-
plexer chain of the trailing register to the registers of the selected
line.
In order to achieve a high test speed, the test implementation
can be pipelined. The scan-in bus { } and the line-select { }
outputs of the global address-decoder can be registered. Also
the XOR-tree can be pipelined with buried register sets. For eight
pages a logic depth of three XOR-cells can be reached. If an op-
timal test speed cannot be achieved, the scan-depth SD can be
reduced (to any number). It is important to notice, that there is no
timing path between adjacent registers on the scan chain during
test mode ({ } { }). Therefore, no hold time problems ex-
ists, which are known from shift-scan-test, and no buffers must
be inserted for hold time fixes.
E. Area
The areas of various cores (see Table II) with the standard
D. Feasibility scan implementation and the areas of the cores with the pro-
posed structure are compared (see Table III) using the lsi10k
It can be assumed, that in todays standard flows, the chip is library. The cores are processors (CPU, OR1200), a DMA-core
designed without scan test insertion. The test structure is imple- and peripherals (AES, ETHER, PCI). They are taken from [30].
mented during the place and route (P&R) step. At that time, the For the calculation of the standard shift (SS) area, each reg-
standard registers (FF) are replaced with scan FF (S-FF) and the ister (FF) is replaced with the corresponding scan FF (S-FF). A
additional routing for the scan-in and scan-enable pins is done. FF with an area of nine logic units (lu) is replace with a S-FF
Supporting test logic (as in EDT, [1]) needs a parallel synthesis of 11 logic units as defined in the lsi10k library. The two addi-
step, but this task can be considered as unproblematic in todays tional pins and the 2-to-1 multiplexer result in an area difference
flows. of two logic units. The resulting core area includes a buffered
The flow for the proposed structure differs only slightly from scan-enable tree and a simple XOR-tree for scan-out decompres-
the one of SS. The standard FF is replaced by an SCAh-FF (in- sion and is listed in of Table III. Buffers for hold time
stead of an S-FF). The global scan-enable signal is identical. fixes of the scan chain are not considered.
The scan connection between registers is now done between the The page support area of an SCAh-FF based implementation
scan-in and the dedicated scan-out of the predecessor (compared for each core is listed in of Table III. This includes
to the data-out pin at the standard flow). The address wires of the XOR-tree and the two AND-selectors for scan-in and line-se-
the individual register lines must be routed from the address de- lect. Additionally one buffer per six registers is added for each
coder. The support logic such as the address decoder can be syn- line-select signal. The area for an SCAh-FF is set to 14 logic
thesized in a parallel task, but since they have are very regular units. Compared to an S-FF it has two more pins and two more
structure, they can also be elaborated during the test insertion 2-to-1 MUX, which results in an area difference of three logic
step. A scan reordering during the P&R step can be done without units. The calculations consider the buffered scan-enable tree
limitations within one page. for SCAhS and SS. As can be seen in Table III, the resulting
The proposed structure can therefore be implemented with area generates an area overhead of 33.78% compared
acceptable modifications to state-of-the-art P&R tools and is to non-test area ( ) and 17.27% compared to
feasible for todays standard design flows with standard STA the SS area ( ) of the core logic. It does not con-
tools. No tristate logic is used. sider memories, MBIST-logic, power-wells, spare-cells and pad
882 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 5, MAY 2012
Fig. 3. SCAh-page, global scan enable not shown.
logic. The number of cell pins per logic unit decreases from 1.25
to 1.18, indicating less congestion than in an SS-based design.
An average of 1375 registers (see Table II) generate an average
SCAhS area of 33.150 lu (see Table III). It is assumed, that a
page with 992 registers has an estimated average area of 23.916
lu. Adding a standard register (9 lu) to a page increases the area
by 0.037%. An example is shown in Fig. 3.
F. Test Cycles and TPG
The number of test cycles (TC) to achieve a reasonable
stuck-at coverage (COV) is another criteria to compare var-
ious test implementation structures. Assuming the method of
shifting data through the scan chain followed by a capture
cycle is used. Then for each capture cycle the test cycles are
determined by the full scan chain length and therefore define
the test set (TS). Trivial logic can be tested very easily but it
generates a huge amount of dont cares for the remaining test
sets. Someone can argue, that the most complicated and hard
to test combinatorial logic determines the number of TS, even
when compression methods are used.
The proposed structure has the advantage of a single cycle
write and a single cycle read of selected register lines. This al-
lows the test method to concentrate on uncovered areas of the
combinatorial logic. The number of dont cares and test cycles
are dramatically reduced.
Another aspect of shift based testing is, that the registers are
overwritten at each scan shift by default. This means, each TS
can be seen independently. Applying multiple consecutive cap-
ture cycles results in the loss of coverage of the trailing cycles,
if the coverage is not propagated.
The proposed structure can apply multiple capture cycles,
since it can asynchronously read register lines in-between them.
This means, while the logic remains in a hold state after a cap-
ture cycle (by stopping the clock or setting the registers in hold
mode) the test procedure can read multiple lines asynchronously
without modifying the register content. Additionally, an optimal
Fig. 4. S-FF outputs toggle at clock edge.
Fig. 5. SCAh-FF chain, propagated scan data toggle, and selected register
output toggle at clock edge.
number of capture cycles (random fill) can follow with an op-
timal set of asynchronous reads.
In order to compare the effectiveness of the test structure, the
indicator test cycles per net [TCPN(COV)] for a certain cov-
erage (COV) is introduced. It is the number of test cycles di-
vided by the number of nets (NETS) of the given netlist [see
(1)]. If COV is not mentioned it is defined as 100%
(1)
This indicator can be used to compare different test methods
and algorithms in terms of number of test cycles for equal design
sizes. More important, it shows if and to which extent a test
method is dependent on the design size. If the TCPN on small
designs is low but increases dramatically when the design size
starts getting bigger than 10 k nets, it is questionable if the test is
useful for multimillion gate designs considering the often very
high computation time which comes with optimized TS.
In this paper, a simple algorithm is used to generate the TS for
the SCAhS. An existing TS is used, which has 100% coverage
and is based on a full-scan structure. To generate the reduced
TS for the SCAhS, the test pattern simulator needs to be mod-
ified. When simulating the TS, the stuck-at coverage is propa-
gated through the combinatorial logic. In the modified version,
the cone input indexes of the relevant logic cones must be prop-
agated as well, if they are relevant for the fault propagation. The
cone inputs can be sequential elements or design inputs. Only if
their values are relevant (cares) and if their values have changed
since the last capture cycle, they are added to the new TS. The
simulator dumps then the test pattern for the write and read cy-
cles as reduced TS for the SCAhS. Additional capture cycles
can be simulated to check if further coverage can be read. TS
which do not add coverage can be skipped.
Due to the single cycle access structure, the test cycles of an
SCAh-FF-based test implementation are always equal or lower
compared to a full shift scan-based technique.
G. Peak Power
The peak power consumption is another serious problem
during shift scan. When data is shifted through the scan chain,
the output of the register toggle with a certain probability (see
Fig. 4). This signal change is then propagated through the ad-
jacent logic. At each clock edge, the power consumption rises
therefore to a level, which is much higher than in functional
STRAUCH: SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST
TABLE IV
ACTIVITY OVERVIEW OF VARIOUS CORES
mode and has the potential to destroy the device due to high
current and heat generation. This problem is discussed in the
literature. For instance Almukhaizim et al. [7] propose a peak
shift power reduction technique via dynamically partitioning
the scan chains into multiple groups. As Sde-Paz et al. [10]
show, the peak power consumption during shift has a reasonable
impact on the capture cycle for at-speed testing. The excessive
current during shift edge leads to an excessive IR-drop, an un-
realistic delay measurement and the CUTs miss-classification.
In the proposed SCAhS, the scan-in data and the scan-out
data toggle asynchronously through a multiplexer chain and
are therefore naturally propagated throughout the complete test
cycle (see Fig. 5). Only a certain number of signals potentially
change at a time which is equal to the number of SW (for
instance 32). The scan data is decoupled from the functional
logic. Only in case of a write the registers on the selected line
potentially change their output value, which is then propagated
only to the adjacent logic of the relevant registers. For a cap-
ture cycle, only some register inputs have changed since the
last capture cycle so that the activity can be limited easily.
In functional mode, the scan chain does not toggle. It can
therefore be assumed, that the peak power is not higher than
in functional mode. It is therefore impossible to destroy or
harm the circuit due to peak power consumption and the circuit
behavior is closer to the functional behavior during test. This
can be achieved without any major computational effort during
pattern optimizations.
H. Power Consumption
The power consumption of a digital sequential circuit can be
simplified in the sense, that the power consumption is directly
related to the activity (ACT) on the chip (zero delay model). In
this paper the activity is defined as the number of nets in a netlist,
which have changed at the end of a clock cycle compared to the
end of the previous cycle.
In order to compare the different power consumptions of the
standard shift scan test implementation and the SCAhS, the ac-
tivity of both solutions is measured during a netlist simulation on
various cores. Also the activity of the cores in functional mode
is extracted. Fig. 6 shows an example. Table IV lists the max-
imum and average activity in functional mode, SCAh-test, and
shift-scan-test of the cores.
883
TABLE V
ACTIVITY RELATIONS
Table V sets the activities listed in Table IV in relation. The
maximum and average activities of the SCAhS is compared to
the equivalent numbers in function mode and shift-scan-test.
For both test implementations a random TS is simulated.
The SCAhS has only a 164% maximum activity compared
to functional mode, and a 358% average activity during test.
The ETHER-core handles a serial datastream and is therefore
relative inactive in functional mode. If this core is not consid-
ered, the activity during SCAhS based tests is only 197% of
the one in functional mode. The maximum activity compared
to SS is only 18% and 12% in average. A circuit with an
SCAhS generates much less activity during stuck-at test than
an S-FF-based implementation. If the average or maximum
activity is problematic, the test speed can be reduced compared
to functional mode or the TS pattern can be optimized.
If multiple pages are tested at the same time, the activity can
be scheduled with the page selection logic. During write cycles
the order of scan-in cycles can be optimized to reduce activity.
Since the average activity of the SCAhS is only 12% (or 18%
maximal) of the shift based design, a larger area can be tested at
the same time during BIST.
The shift-scan test has a reasonable impact on the capture
cycle for at-speed testing and on the behavior of the design itself
[10]. A reasonable lower activity of the test logic leads to more
realistic functional chip behavior during test.
I. Debugging
In a tester environment, the CUT can be stimulated with con-
trolled clock signals. Most tests can be repeated cycle accurate.
To view internal register values of a S-FF-based test insertion in
normal operation (at-speed), the test is stopped after a defined
number of clock cycles and the register values are shifted out
(one test per cycle). This procedure is repeated by adding one
cycle at a time [29]. The SCAhS supports this procedure.
With the SCAhS one particular line can be selected and con-
tinuously read out (one test per line). SW register values can
directly be streamed out during one test. In other words, the
SCAhS gives the same debug visibility as the shift structure,
but allows the user to concentrate on selected signals when de-
bugging extensive tests without stopping the test run.
884 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 5, MAY 2012
Fig. 6. Activity of PCI core.
TABLE VI
TRUTH TABLE OF SCA-FF
This becomes a major advantage during functional debugging
of a chip embedded in a system or board, which is even more
challenging. Almost all cases do not allow to rerun scenarios
cycle accurate. Additionally, the failure could possibly appear
only after a very long run-time. If the S-FF based chip fails on a
board or within a system and must be debugged, register values
can be shifted out (snap-shot) but hardly accumulated to a con-
tinues waveform. The SCAhS has the same snap-shot capability
but additionally allows a continuous at-speed readout of one par-
ticular register line. This feature is sometimes embedded in the
functionality (processor debugging) but is now already imple-
mented in the SCAhS and works for any set of SW registers.
The continuously data stream can then be used by on-/off-chip
trigger units or stored in waveform files.
The asynchronous read feature of the SCAhS can become part
of the chips functionality. The SCAhS organizes the registers
like a memory which can be read by a processor for instance.
Also write cycles can be done if the remaining registers of a
page accept a hold cycle by selecting page-select { }.
The asynchronous continuously read feature of the SCAhS
can already be implemented in a field-programmable gate array
(FPGA) debugging tool used for system prototyping. The ex-
perienced gained with register streaming during system proto-
typing can be shared with the test group.
IV. SCA-STRUCTURE WITHOUT HOLD MODE
A. SCA-FF
In order to reduce the area overhead of a SCAhS, a simpler
SCA-FF is discussed. It adds only one 2-to-1 MUX to the stan-
dard S-FF (see Fig. 7). The truth table is shown in Table VI. It
only has one { } input, which is connected to the individual
line-select signal. The pin which is connected to the global en-
able signal in the SCAhS is removed, so that the complete global
scan enable tree becomes obsolete. The SCA-structure (SCAS)
connectivity and page organization equals the one of the SCAhS
(see Figs. 2 and 3) without the global scan enable { }.
Fig. 7. SCA-FF based on an S-FF.
TABLE VII
AREA OF CORES WITH TEST INSERTION
B. Area
The area of the SCAS is calculated in Table VII and com-
pared to a standard S-FF based implementation. The area of a
register (FF) is nine logic unit. The corresponding area of a S-FF
is 11 logic units and the area of a SCA-FF is set to 13 logic
units. The support area of the SCAS equals the one
of a SCAhS without the buffered scan-enable tree. The SCAS
area is calculated and the area overhead compared to
non-test is 26.02% ( ) and compared to a S-FF
based implementation ( ) in average 10.51%. The
cell pins per logic unit index drops from 1.25 for the SS design
to 1.12 for the SCAS. An average of 1375 registers (see Table II)
generate an average SCAS area of 31.316 lu (see Table VII). It
is assumed, that a page with 992 registers has an estimated av-
erage area of 22.593 lu. Adding a standard register (9 lu) to a
page increases the area by 0.039%.
C. Test Cycles and TPG
The SCAS basically has the advantages of a single cycle syn-
chronous write and a single cycle asynchronous read of a reg-
ister line. The pSCAhS and the SCAS have in common, that a
majority (pSCAhS) or all (SCAS) of the registers do not have
a hold mode and automatically capture the new value if a write
to a register line is done. This fact makes the TPG an extremely
complex task. Therefore, the TCPN for the SCAS are purely
based on random pattern generation and does not always reach
100% coverage.
D. Debugging
One aspect for debugging is particular important. How many
if not all register values can be directly probed and read out.
Usually a scenario is created by running a test in functional
STRAUCH: SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST
Fig. 8. gSCAS connectivity.
mode which is then stopped at a certain point of time. In the
SCAS all registers values can then asynchronously be read. The
missing feature is that a certain test scenario cannot be accom-
plished by scanning in data through a scan chain as someone
can do it with full scan to set the CUT in a predefined state. The
additional feature of continuously tracing a register line in func-
tional mode on the tester or in-system as discussed in the SCAh
section still exists. Also the potential to combine this feature
with the chips functionality is doable.
V. GATED SCA-STRUCTURE
This section discusses the gated SCAS (gSCAS), which has
all the benefits of the SCAhS but only has the area overhead
of the SCAS. The hold function of the SCAh-FF is missing in
the SCA-FF. It is instead built into the gated clock tree of the
gSCAS. Fig. 8 shows the connectivity of the gSCA. The scan
path reaches from the scan-in AND-selector over the SCA-FF
chain (by connecting the scan-out pins of each SCA-FF with the
scan-in pins of the succeeding SCA-FF) and is connected with
the input of the XOR-tree. The individual line-select signals { }
are connected with the { } input of the SCA-FF in the rele-
vant line. All SCA-FF on a line are clocked by a gated clock
element (gcl). The gcl is driven by the clock and the line-select
signal. The gated clock element can be enhanced, if a clock en-
able signal { } generated by combinatorial logic exists. The
global scan enable signal is connected with each gcl, which is
already the case in SS if gated clock elements are used to prop-
agate the clock during shift.
The gated clock gcl elements functionality is shown in
Table VIII. If the global scan enable pin { } is deselected,
the clock is propagated depending on the clock enable signal
(functional mode, Table VIII, line 2 and line 3). In test mode
, the clock is only propagated, if the address
line is selected. This allows a hold function if { } is not se-
lected (hold mode, Table VIII, line 4) and a synchronous write
if the address line is selected (write mode, Table VIII, line 5).
A. gSCAArea
Since the gSCAS uses an SCA-FF, the area overhead equals
the one of the SCAS, which is 10.51%, or more precisely, if
the area for the gated clock logic is added, 11.14% compared to
885
TABLE VIII
TRUTH TABLE OF GATED CLOCK LOGIC
SS. One additional standard register increases the page area by
approximately .
Serious area improvements can be made, if the SCA-FF (13
lu) uses an inverting MUX (SCA-FF-I, 12.5 lu), which has a
lower area and only generates a gSCAS area overhead of 8.61%
compared to SS. The TPG must then consider the inverting
scan-chain. Also a two transistor MUX can be used (SCA-FF-P,
12 lu, 6.07% area overhead), which has the disadvantage of a
degrading slope over multiple pass transistors. A mixture of a
few SCA-FF-P followed by a SCA-FF-I is applicable and an
area overhead of 7% can be assumed.
B. gSCAFeasibility, TCPN, Power, Debugging
In Section III, SCAh-Structure with Hold Mode, various as-
pects are discussed. Most of them are also valid for the gSCAS.
The insertion of gated clock logic is standard and any existing
static timing analysis tool can be used (feasibility). The TCPN
number is identical to the one of the SCAhS, because these two
implementations of the single cycle access method are func-
tionally identical. Any ATPG algorithm for SS can be used as
starting point and the TS is optimized for the single cycle access
technique. The problems peak power and the power consump-
tion during tests are eliminated by using the gSCAS. The ad-
vantages of streaming out internal registers during testing and
debugging are discussed in Section III, SCAh-Structure with
Hold Mode, I. Debugging. The same arguments can be made
for the gSCAS.
C. gSCA-Routing
This section compares the routing effort of the SS with the one
of the gSCAS. The following differences of the routing effort
can be observed.
In SS the data-out { } is connected to the scan-in { } of
the succeeding register in the scan chain. The SCA-FF has now
a new output scan-out { } for that. The pin { } is connected
to the { } of the succeeding register in the scan chain. It can be
assumed, that this modification has only a minor impact on the
routing effort.
The global scan enable signal in the SS structure can be seen
as a signal tree, which is connected to all S-FF in the design and
to all gated clock elements if they exist. The fan-out of this tree
can be calculated as number of S-FF plus the number of gated
clock elements .
In the gSCAS, the global signal enable signal is only con-
nected to the gated clock elements but not to each
SCA-FF. The local line select signals { } must be connected
to each register on their register line and the
gated clock element . They generate small local trees (see
886 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 5, MAY 2012
Fig. 9. Global scan enable routing in SS and global scan enable and line select
routing in gSCAS.
Fig. 9). The fan-out of the global select in SS
is only slightly lower compared to the sum of the fan-out
of the global select and line select signals in the gSCAS
. activity gSCAS on two pages implies two registers for page
The gSCAS uses an AND-selector for the line select and the
scan-in data for each page. The AND-selector is only needed if
at-speed data streaming during debugging is used, if the activity
during test should extremely be reduced or if at-speed test sce-
narios can be generated more efficiently by a more specific reg-
ister write. For stuck-at testing, it is recommended to test pages
in parallel setting all AND-selectors to pass the scan-in data. In
case a page has a SW of 31 and a SD of 32, the page has 992
registers and approximately 4747 combinatorial cells (consid-
ering the fact, that in Table II an average of 1375 registers have
6581 combinatorial cells). The page selector adds one register
per page and the AND-selector uses 63 AND-cells per page, which
are all connected to the page select signal. The additional net
{ } connected to 65 cells does not limit the routing of a page
with 992 registers and 4747 combinatorial cells. If each page
uses an individual address-decoder, the AND-selector can also
be located at the input of the address-decoder (5 bits), reducing
the number of used AND-cells to in the given ex-
ample.
It is important to mention, that the overall structure of the
routing does not change, because the global scan enable signal
is now basically replaced with local line select signals and the
global scan select is already routed to gated clock elements, if
exist. Regarding the congestion, the pins per area drop from 1.25
in the SS to 1.12 in the SCAS, which is almost identical to the
one of the gSCAS. This number indicates, that the gSCAS does
not lead to additional congestion problems.
D. gSCASTiming
The gSCAS is used to evaluate the timing for testing and de-
bugging of the proposed single cycle access methods discussed
in this paper. Fig. 8 shows the relevant timing arcs of the pro-
posed test implementation. ta1 is the timing arc from the line
decoder to the individual registers on the line. These local trees
can be very efficiently optimized and are therefore extremely
fast. The area overhead estimations for the gSCAS include 6
buffers per 32 registers. ta2 is the timing arc from a global
scan enable register to the gated clock elements of the gSCAS.
This tree can efficiently be pipelined as discussed in [12], if nec-
essary. ta3 is the timing arc through the MUX in the SCA-FF
chain. The chain depth can be adapted to the target test speed.
The scan-in can be pipelined before the AND-selector (if exists)
and the XOR-tree can be pipelined within the XOR tree logic.
The most critical feature in terms of timing is the at-speed
data streaming of internal data values during debugging. If this
feature is used, ta3 must cope with the design speed.
In SS-based designs, the shift cycle timing is reduced to avoid
heat dissipation due to high activity. The peak power problem
and the power consumption due to high activity is solved in the
gSCAS. If pattern are streamed through the IOs of the design,
the limiting factor can be the automatic test equipment (ATE).
The critical timing arc ta3 can be optimized for the ATE to
achieve the fastest possible test speed. In gSCAS-based BIST,
the test speed can also be reasonable improved, due the absence
of power problems. If ta3 is fast enough, the BIST speed can
run at design speed.
A realistic ultra fast high speed test implementation of a low
select, one register for scan enable, 5 registers for the address
bus, 32 registers for the scan-bus-in, and 32 registers for the
scan-bus-out. With 72 registers, two pages can be extremely
pipelined. One additional standard register increases the area
by approximately , which results in a 1.4% area
increase of a single page. This extreme case can be suggestively
reduced based on users test preferences.
E. gSCAAt-Speed Testing
During at-speed tests, the path delay of critical paths is tested.
In SS the patterns are scanned in to generate a certain stimuli
scenario, followed by one or two capture cycles, and a scan out
of the captured data. The last capture cycle is executed at func-
tional speed to measure the path delay. Two problems are dis-
cussed.
First, the power problem during shift which can result in
wrong delay measurements. A scan in shift cycle usually re-
sults in an excessive current due to the high toggling rate of
the register values. An excessive IR-drop can lead to an exces-
sive delay and therefore to a miss-classification of the CUT. For
gSCAS, the same stimuli scenario can be generated but the last
write is limited to the registers on the selected line, all other
registers remain in hold mode. This eliminates the peak power
and power consumption problem due to high activity during
at-speed testing as well, allowing a more precise measurement
of the critical path.
Second, the slow global scan enable { } signal generates
an extended test cycle delay for each test. The scan enable
signal must be disabled to enable a capture cycle. Fig. 10 shows
the timing. Therefore, the value of the global scan enable signal
must change during the at-speed capture cycle (Tlos). The
method is called launch-on-scan (LOS), because the signal of
the path-delay starts to be measured with the last scan cycle.
This high speed approach requires a balanced global scan en-
able signal and is therefore very area intensive. The workaround
is to add an additional capture cycle to the test method. This
allows the { } to be propagated through a slow global scan
enable tree (Fig. 10, Tloc) followed by two capture cycles. This
method is called launch-on-capture (LOC), because the signal
of the path-delay starts to be measured at an additional capture
cycle, which results in a more complex TPG process.
Since the gSCAS is backward compatible to SS, the same pat-
tern can be applied to gSCAS as for the SS, for example LOC
STRAUCH: SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST
Fig. 10. LOC, LOS timing.
at-speed pattern. The difference to the SS is that the gSCAS pro-
vides an extremely fast scan-enable functionality. The global
scan enable signal is only connected to the gcl and can there-
fore be much better balanced. The relevant timing arc ta2 in
Fig. 8 can be as fast as the test speed, otherwise it can easily
be pipelined as discussed in [12]. Each standard FF adds only
0.039% area overhead per page. The second relevant timing is
the delay of the line select signals. These are only small and local
trees and can therefore cope with the design speed. The relevant
timing arc ta1 is shown in Fig. 8. The line select is driven by
the address decoder. The inputs can be driven by a pipelined ad-
dress select, similar to the method discussed in [12]. A pipelined
address bus (5-bits) adds only 0.19% area overhead per page.
Even if the timing requirements for LOS cannot be achieved,
the timing for LOC is reasonable improved.
In SS the pattern must be scanned in to generate a certain
stimuli scenario. The gSCAS allows a selective single cycle read
and a selective single cycle write to achieve the same result. A
consecutive sequence of a single cycle write, a capture cycle
and single cycle read is doable to toggle and measure the inverse
path within a few cycles. The gSCAS reduces the at-speed TS or
allows more tests within the same time. With a pipelined support
logic, the at-speed tests can be examined on a low-cost tester.
VI. RUNNING PAGE TESTS IN PARALLEL
A common approach to reduce the TCPN is the method
to partition the scan chain into multiple parallel and there-
fore shorter scan chains [1]. The problem of peak power
consumption and high activity during scan shift requires ad-
ditional enhancements. Especially peak power consumption
cannot be eliminated easily in shift-scan based designs. For
SCAhS/gSCAS based designs, peak power consumption and
activity during test is unproblematic.
The same approach of testing with a higher number of par-
allel scan chains can be used in single cycle access structures,
when multiple pages are enabled at the same time. The write is
then done with the same write value to the same line index of
each enabled page. Also the same line is read at each enabled
page and the results are then passed through the XOR tree to the
output. The activity during the write or read cycles can be ad-
justed by enabling only an optimal set of pages if it needs to be
reduced at all. An example of testing the five largest ISCAS89
designs (s9234, s13207, s15850, s38417, and s38584) in par-
allel is given.
VII. ADDRESS CONTROLLED BIST
A problem in testing is the high test data volume for the
ATE. This test amount is reduced by BIST implementations.
887
Fig. 11. Address controlled BIST.
Since SCAhS and gSCAS are backward compatible to shift
scan implementations (by automatically incrementing the ad-
dress during shift), existing BIST solutions can be used on
them as well. An additional problem is the high number of test
pins for testing. In this section a method is proposed to reduce
the pin count of the test IOs on an address controlled SCAhS-
or gSCAS-BIST.
The principle idea of BIST is not to apply write values to the
DUT by the tester but instead taking them from the scan-out
values of the DUT internally. These deterministic pattern gen-
erated by the DUT are used with or without (de-)compression
logic as the stimuli of the DUT itself.
This BIST mechanism is used in the proposed structure. Only
the address signals { } are controlled to optimize the process.
With an address controlled read the internal values of a partic-
ular line of the enabled pages are then propagated through the
XOR tree to the scan output. The scan-out pattern can also be
used as scan-in pattern and an address controlled write can be
done.
The address controlled BIST structure is as follows (see
Fig. 11). An on-chip test controller can be accessed by the ATE.
The controller can enable and disable individual pages. It also
controls the register mode (functional/capture, write, read and
hold) by applying the right values to { }, { }, and { }.
The page scan-in data are taken from the scan-out data of the
XOR tree. The second XOR tree minimizes the scan output to a
single bit, which is then read by the ATE. The individual page
select register can be set by a shift register.
The controller has two modes. In the special mode, the { },
{ }, and { } can be set and { } can be read through the
ATE interface (ATE-IF) to have full control for special tests and
debugging. In the BIST mode, the information address and reg-
ister mode are passed through the ATE-IF. These roughly 8 bits
(control- and address bits) are then passed through a data multi-
plexed (double edged signal) ATE-IF. The resulting test inputs
are then 4 bits and 1 bit for the XOR-tree output. An example
of testing the five largest ISCAS89 designs (s9234, s13207,
s15850, s38417, and s38584) using address controlled BIST is
given.
VIII. RESULTS
This section lists the results of different implementations dis-
cussed in the previous sections. In Table IX, the numbers of reg-
isters, combinatorial cells, design input, and design outputs as
well as the numbers of nets are listed. This is done for ISCAS89
888 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 5, MAY 2012

TABLE IX
NET COUNT AND TCPN FOR ISCAS89 AND VARIOUS CORES

designs and example cores taken from [30] using the lsi10k li-
brary. Table IX also shows the TCPN extracted from various [4],
[5], [11], [31].
In [11] test compaction for at-speed testing is used in order
to reduce the test application time. The test cycles TC are taken
from Table III of [11] to calculate the TCPN. The algorithm in
[31] reduces switching activity during scan testing (test vectors
of Table III of [31] are taken) and simultaneous test time and
power reduction are shown in [5] (see Table II, TA1 is used).
In [4] the reduction of test application time using limited scan
operations is shown. The numbers of Table IV (column: pro-
cedure 3.5) in [4] are taken. The test cycles listed in the refer-
ences are all calculated based on a single scan chain .
Table IX lists the TCPN which can be achieved with SCAhS
(gSCAS) and an SCAS using the algorithm shown in Section III,
SCAh-Structure with Hold Mode. F. Test Cycles and TPG.
All TCPN are extracted using a scan width of in order
to compare the results with the [4], [5], [11], [31]. A write to
a primary input or a read to a primary output also results in an
additional test cycle.
Fig. 12 shows the TCPN over the number of nets listed in
Table IX. Whereas the TCPN rises dramatically with increasing
design sizes (NETS) for alternative approaches, the TCPN of the
proposed structures are independent of the design size and tend
STRAUCH: SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST
Fig. 12. TCPN with SW = 1 over nets.
TABLE X
COVERAGE AND TCPN OF VARIOUS SCAS IMPLEMENTATIONS
to decreases with rising design sizes. For smaller designs the
TCPN of the proposed structures are not very much favorable
because a simple TPG algorithm is used. The advantage of the
single cycle access technique over shift scan-based structures
becomes obvious for larger designs.
All results listed so far are related to a single scan chain
. This is particular useful for the comparison of
standard scan implementations and to directly calculate the test
amount (TA). The TCPN for any single cycle access structure as
well as for the shift based structure will decrease with a higher
SW. The number of input address bits of the address decoder is
defined as ABIT. For any SCA structure, the TA increases by
ABIT/SW. If SW is 32, which is a more realistic case, TA in-
creases by due to the additional address data.
If pages are tested in parallel (see Section VII, Running Page
Tests in Parallel) the TCPN further decreases. For a parallel test
of the five largest ISCAS89 designs (s9234, s13207, s15850,
s38417, and s38584), a TCPN(99.3%) of 0.088 is achieved with
a scan width of 32 (see Table X).
For address controlled BIST (see Section VIII, Address Con-
trolled BIST) a TCPN (98.9%) of 0.14 is achieved for the
ISCAS89 design set (see Table X).
IX. DISCUSSION
A. Summary of Single Cycles Access Implementations
As listed in Table XI, for the proposed solutions, the peak
power problem is eliminated and the activity for random stimuli
pattern is simulated with only 12% average activity compared to
shift based tests and 358% maximum activity compared to func-
tional mode on a single active page. This leads to more realistic
test results because the tests are executed under more realistic
conditions closer to the chip behavior in functional mode.
889
The TCPN indicator of gSCAS is reasonable lower for large
designs than the one of shift-scan-based solutions and is in-
dependent of the design size. The higher test frequency and
the lower TCPN of the proposed single cycle access structures
clearly dominate the shift-scan based implementations by one
or two orders of magnitude. Assuming the production test can
run with a five times higher test frequency and the test cycles are
five times less than shift-scan based designs, the runtime advan-
tage would be .
The logic area overhead for non partial solutions is 17.27%
higher in the SCAhS but only 10.51% (11.14%) higher for the
SCAS or gSCAS compared to SS. The area overhead is related
to the core logic. If memories, power wells and pad area are
considered and make up 50% of the die, the area overhead is
reduced to 8.64% and 5.26% (gSCAS: 5.57%) respectively. If
test costs due to test time becomes more and more dominant
over area costs, the area overhead becomes less critical.
The SCAhS and gSCAS are backward compatible to shift-
scan implementations, so that all known tests can be executed
on the proposed structure. A relative minor change to the test
simulator must be done to extract the single cycle access ori-
ented TS. They can also be used together with BIST methods.
Further on they do have additional features for debugging the
silicon on- and off-chip.
B. Selecting the Best Single Cycles Access Implementation
Two cases must be considered. The first case implies that the
area overhead is acceptable. As can be seen in Table XI, gSCAS
is the most preferable solution to replace an SS. The area over-
head of 11.14% for the gSCAS can be reduced, if a SCA-FF with
an inverting MUX is used (8.61%) or a MUX with 2 pass-tran-
sistors is used (6.07%). The numbers refer to the test relevant
logic. They do not consider memories, power wells, pad cells,
etc., so that the area overhead relative to the die size is reason-
able less. The gSCAS has the following three differences to SS:
1) one additional MUX per register and a new scan-out pin; 2)
the global scan enable is only routed to the gated clock elements;
and 3) an address decoder selects the register on a line and the
gated clock element.
The second case implies, that the area overhead is not ac-
ceptable and a partial implementation should be used. This and
other reasons such as limited test IOs for instance can lead to
a BIST implementation. Table IX shows that the address con-
trolled BIST achieves a reasonable TCPN.
C. gSCAS Compared to RAS
This section compares the gSCAS with various RAS
schemes. Three different RAS schemes can be identified. The
first group uses basically one single address-decoder to select
each individual register in the design and an additional element
(MUX) per register cell enables a hold mode of each register.
The fact that each cell can be accessed individually generates
an unaffordable routing overhead compared to gSCAS, which
has almost the same routing requirements as SS.
The second group addresses each register individually by
using an (or row) and a (or column) address decoder with
an additional combinatorial element (for instance AND gate)
per register cell. The cell values can be individually read by
890 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 5, MAY 2012
TABLE XI
OVERVIEW OF VARIOUS SINGLE CYCLE ACCESS STRUCTURES
an additional signal driven by a tristate logic added to each
register cell. These proposals have in common, that the - and
-line select routing is unaffordable. The individual register
cells are enhanced by multiple logic elements which generate
an unaffordable area overhead compared to gSCAS, which
only adds one multiplexer to each register. The readout is done
using tristate logic, which is problematic in todays standard
design flows. The gSCAS uses no tristate logic.
The third group uses a row decoder and a column decoder to
address individual registers. Additionally the read/write mecha-
nism is enhanced with two signals per column, driven by tristate
drives connected to the internal latch cells of the registers via
tristate logic and an individual sense amplifier per column. The
routing is an overhead compared to gSCAS, if two signals per
column are used. The enhanced read and write mechanism with
tristate drivers, cell internal tristate logic and sense amplifier
per column is very timing sensitive. A few registers on a single
row generate an immense area overhead due to the individual
sense amplifier per tristate signal. A higher amount of registers
on a single tristate signal, driven from the internal register logic
through a pass transistor generate an unacceptable slope of the
signal during a read cycle. During a write cycle the latch-like
timing is also very timing critical. The tristate data signals must
hold their values until the row select signal is disabled. The re-
quirement to balance all row select signals of the already crit-
ical routing structure is hard to achieve and generates therefore
a complex timing scenario. This sensitive tristate logic has been
successively removed in the last decade from standard logic li-
braries and is not applicable for todays well established static
timing analysis, which is key to achieve sign-off quality for in-
dustrial test implementations for multimillion gate designs. The
gSCAS fits easily in todays STA flows. Further on, LOS-based
at-speed testing is not possible for this group of RAS imple-
mentations, whereas the gSCAS supports LOC and LOS based
at-speed testing due to its synchronous write capabilities and
faster scan enable logic.
X. CONCLUSION
A single cycle access structure is discussed. Various imple-
mentations with and without hold mode as well as gated and
partial implementation methods are presented. The aspects fea-
sibility, peak power consumption, switching activity during test,
area, test cycles, at-speed testing and debugging features are
compared. A guide is given how to select the best implemen-
tation. The best solution (gSCAS) is compared to RAS imple-
mentations and is superior to all known RAS solutions. If BIST
is preferable due to limited chip IOs or partial scan implemen-
tation, an address controlled BIST is discussed.
The ATPG algorithms can be enhanced with the same
methods SS implementations are optimized. Future work is
related to algorithms for reducing the test cycles per net itself,
register reordering, pattern optimization for activity reduction
and de-/compression methods for BIST using the gSCAS.
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Tobias Strauch received the Diploma (FH) from the
University of Applied Science (FH), Furtwangen,
Germany, in 1998.
He is with EDAptability, Munich, Germany. His
field of interests include hardware assisted verifica-
tion, TLM, high level ATPG, FPGA debugging, and
wave-based data transfer.