A Brief Proposal for the Ph.

D work

Introduction:

Reversible computing has been studied since Rolf Landauer in 1961 advanced the argument that
has come to be known as Landauer's principle. This principle states that there is no minimum
energy dissipation for logic operations in reversible computing, because it is not accompanied by
reductions in information entropy.

Reversible logic is a one of the promising computing design paradigm which presents a method
for constructing digital systems that produce approximately no power dissipation. Reversible
computing emerged as a result of the application of quantum mechanics principles towards the
development of a universal computing machine. Specifically, the fundamentals of reversible
computing are based on the relationship between entropy, heat transfer between molecules in a
system, the probability of a quantum particle occupying a particular state at any given time, and
the quantum electrodynamics between electrons when they are in close proximity. The basic
principle of reversible computing is that a bijective device with an identical number of input and
output lines will produce a computing environment where the electrodynamics of the system
allow for prediction of all future states based on known past states, and the system reaches every
possible state, resulting in no heat dissipation.

Reversible Logic Gate:

In the existing literature, there are several reversible gates such as the Feynman gate and the
Fredkin gate, HNG, PERES, MUX gate etc. On the basis of less quantum cost, less garbage
values and other parameters, the researcher has to select the gates. The number of 1x1 and 2x2
reversible gates needed to design a 3x3 reversible gate from 1x1 and 2x2 reversible gates is
called the quantum cost of that gate & numbers of unused I/p and o/p are called garbage i/p and
garbage o/ps .
So, Far various logical circuits has been implemented in the reversible literatures like adder,
subtractor, multiplier , counter etc at logical level implementation.
At the circuit level implementation, CMOS technology & Adiabatic gates like 2PASCL and
CMOS logics are available in literature which consume low power at the circuit level and
generally used to implement the reversible gates. But due to the huge numbers of CMOS
transistors, the sub threshold leakage exist which also increases the power consumption and
broke the law of reversibility at the physical level design. So, It is necessary to design a suitable
circuit level design for the reversible gates to reduce not only the power consumption but also the
complexity of the structure also.

The sub threshold leakage which is also present in the adiabatic gates can be avoided by using
Power gating structure where we use an extra NMOS OR PMOS with the structure to reduce this
leakage.
The Power gating structure has already been introduced in the reversible adiabatic gates
literature but the Gate diffusion cell (GDI cell) and other stacked structure has not been
introduced in the literature so far.

So, In the next study , The candidate wish to work with the Low power design of the Adiabatic
reversible gates by using various design techniques like Power Gating, GDI cell, Hybrid GDI
cell and also by using artificial intelligence for the VLSI design.

The work will not be only upto the design of the structure by above said technique. It also
included the Analysis of each parameter, Node reduction, Reduction of Quantum Cost at logical
level and definitely power consumption reduction with less delay and high speed.

Reference:

1) B.V. Praveen Kumar, K.N. Muralidhara, Design of Control unit for Low
Power ALU Using Reversible Logic, Procedia Engineering, Volume 30, 2012,
Pages 631-638

2) Guoqiang Hang, Hangzhou, Adiabatic CMOS gate and adiabatic circuit design for low-
power applications Proceedings of the 2005 Asia and South Pacific Design Automation
Conference Pages 803-808

3) Y. Yamanashi & N. Yoshikawa, Reversible logic gate using adiabatic superconducting

devicesScientific Reports 4- Nature, Article number: 6354 (2014)

4) Samer Houri, Alexandre Valentian, Herv Fanet, Comparing CMOS-Based and NEMS-
Based Adiabatic Logic Circuits Reversible Computation - SpringerVolume 7948

5) Mariam Zomorodi Moghadam, Keivan Navi, Ultra-area-efficient reversible

multiplierMicroelectronics Journal,Volume 43, Issue 6, June 2012, Pages 377385

6) Samer Houri ; Gerard Billiot ; Marc Belleville ; Alexandre Valentian ; Herv

Fanet, Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic
Logic Applications, IEEE Transactions on Circuits and Systems I: Regular
Papers ( Volume: 62, Issue: 6, June 2015 )