Professional Documents
Culture Documents
Decoders
ROMs (LUTs)
Preferred symbol
A 0
A 0
Q Q
B 1 B 1
S
S
“Select” input
A 0 A 0 A 0
Q Q Q
B 1 B 1 B 1
S 0 1
S A B Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
S A B Q AB
0 0 0 0 S 00 01 11 10
0 0 1 0 0
0 1 0 1 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
S A B Q AB
0 0 0 0 S 00 01 11 10
0 0 1 0 0 1 1
0 1 0 1 1 1 1
0 1 1 1
1 0 0 0 Q = S’A + SB
1 0 1 1
1 1 0 0 A
1 1 1 1 S
Q
{
I0
Data I1 4:1 Z
Inputs I2 MUX
I3
AB
{
Control Inputs
ABC
Control Inputs
I0
N Data I1 N:1 Z Output
Inputs … MUX
IN-1
…
sk-1…..s0
I0
Q = A’B’I0 + A’BI1 + AB’I2 I1
3:1 Q
MUX
I2
AB
BusA
00
bit 0 01 bit 0
10
11
BusB
Select control
lines
bit 0
BusC
bit 0
BusA
00
bit 1 01 bit 1
10
11
BusB
Select control
lines
bit 1
BusC
bit 1
BusA 00 00 00 00
Output
bit 15
BusB
bit 2
bit 0
01 01 bit 1 01 01
BusC 10 10 10 … 10
11 11 11 11
s1
s0
A B C F
0 0 0 0
0 0 1 0 A=0 part of the truth table
0 1 0 0 … when A=0, F=0 0 0
F
0 1 1 0 B+C 1
1 0 0 0
1 0 1 1 A=1 part of the truth table
1 1 0 1 … when A=1, F=B+C A
1 1 1 1
B A C F
0 0 0 0
0 0 1 0 B=0 part of the truth table
0 1 0 0 … when B=0, F=AC AC 0
0 1 1 1 F
A 1
1 0 0 0
1 0 1 0 B=1 part of the truth table
1 1 0 1 … when B=1, F=A B
1 1 1 1
C A B F
0 0 0 0
0 0 1 0 C=0 part of the truth table
0 1 0 0 … when C=0, F=AB AB 0
0 1 1 1 F
A 1
1 0 0 0
1 0 1 0 C=1 part of the truth table
1 1 0 1 … when C=1, F=A C
1 1 1 1
A B C F
0 0 0 0 AB=00 part of the truth table
0 0 1 0 … when AB=00, F=0 00
0 1 0 1 AB=01 part of the truth table
0
C’ 01
F
0 1 1 0 … when AB=01, F=C’ 1 10
1 0 0 1 AB=10 part of the truth table C 11
1 0 1 1 … when AB=10, F=1
1 1 0 0 AB=11 part of the truth table
… when AB=11, F=C AB
1 1 1 1
Can easily re-order truth table to use different MUX control inputs
A B F
0 0 1 1 00
0 1 1 1 01
F
0 10
1 0 0 1 11
1 1 1
AB
This shows that a large enough MUX can directly implement a truth table…
I0
AB
C 00 01 11 10 I1 4-to-1
MUX Z
0
I2
1
I3
A B
0 I0
AB
C 00 01 11 10 I1 4-to-1
MUX Z
0 0 1 1 0 I2
1 0 1 0 0
I3
0 I0
AB
C 00 01 11 10 1 I1 4-to-1
MUX Z
0 0 1 1 0 I2
1 0 1 0 0
I3
0 I0
AB
C 00 01 11 10 1 I1 4-to-1
MUX Z
0 0 1 1 0 0 I2
1 0 1 0 0
I3
0 I0
AB
C 00 01 11 10 1 I1 4-to-1
MUX Z
0 0 1 1 0 0 I2
1 0 1 0 0
C’ I3
0 I2
A=1 B=0 Z = 0•0 + 0•C’ = 0
C’ I3
A=1 B=1 Z = 0•1 + 1•C’ = C’
A B
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
00 X 1 X
0 4 12 8
01 1
1 5 13 9
11 13 7
115 111
10 X 1
2 6 14 10
A B C
A B C
A B C
A B C
A B C
A B C
A B C
A B C
A B C
A C D
A C D
A C D
A C D
A C D
A C D
A C D
A C D
A C D
00 X 1 X
I0
01 1 I1
I2
8-to-1 Z
11 1 1 1 I3 MUX
I4
10 X 1 I5
I6
Z = AC + AD’ + A’BC’ + B’CD I7
A C D
00 X 1 X
B I0
01 1 B I1
0 I2
8-to-1 Z
11 1 1 1 B’ I3 MUX
1 I4
10 X 1 0 I5
1 I6
Z = AC + AD’ + A’BC’ + B’CD 1 I7
A C D
0 0 0 Z = B Z = 0
0 0 1 Z = B Z = B Why
0 1 0 Z = 0 Z = 0 are
they
0 1 1 Z = B’ Z = B’
different?
1 0 0 Z = 1 Z = 1
1 0 1 Z = 0 Z = 0
1 1 0 Z = 1 Z = 1
1 1 1 Z = 1 Z = 1
01 1
11 1 1 1
10 X 1
01 1
11 1 1 1
10 X 1
01 1
11 1 1 1 Which is right??
10 X 1 They both are!!!!
Z = AC + AD’ + A’BC’ + B’CD
11 1 1 1 1 I3
10 X 1
A C
F = A’B’CD = (0)’B’(1)D = B’D
Same as before!
F0
I1 F1
I0 F2
F3
© 2003-2008
BYU
Decoder Behavior
F0 1 F0 0
0 I1 F1 0 0 I1 F1 1
0 I0 F2 0 1 I0 F2 0
F3 0 F3 0
F0 0 F0 0
1 I1 F1 0 1 I1 F1 0
0 I0 F2 1 1 I0 F2 0
F3 0 F3 1
© 2003-2008
BYU
2:4 Decoder
A B Q0 Q1 Q2 Q3
Q0
A 2:4 Q1 0 0
B Decoder Q2 0 1
Q3 1 0
1 1
A B Q0 Q1 Q2 Q3
Q0
A 2:4 Q1 0 0 1 0 0 0
B Decoder Q2 0 1 0 1 0 0
Q3 1 0 0 0 1 0
1 1 0 0 0 1
Q0 = A’B’ = m0
Q1 = A’B = m1
Q2 = AB’ = m2
Q3 = AB = m3
Q0 = A’B’C’ = m0
Q1 = A’B’C = m1
Q2 = A’BC’ = m2
… …
Q7 = ABC = m7
2:4
m2 F = Σ m(0, 2)
Decode
m1
2:4
m2 F = Π M(1, 2)
Decode
M0
2:4
F = Σ m(0, 3)
Decode
M3
ADD
SUB
op2 AND
3:8 XOR
op1
Decoder NOT
op0 LOAD
STORE
JUMP
Address Data
0 1
1 0
2 1
3 0 Addr 8x1 Data
4 0 In ROM Out
5 1
6 1
7 0
Address Data
0 0
1 7
2 2
Addr 8x5 Data
3 14
In ROM Out
4 26
5 0
6 18
7 22
• An addressable memory
– Send in address (addr)
– Receive data (d) stored addr2
8x5
addr1
at that location addr0
ROM
d4 d3 d2 d1 d0
A
A B C F B
0 0 0 0 F
B
0 0 1 0 C
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0 A
8x1
1 1 0 1 B ROM F
1 1 1 1 C
n Input n:2n .
.. Memory Array
Lines . decoder .
. 2n words x m bits
...
m Output Lines
m0=A’B’C’
m1=A’B’C
m2=A’BC’
A
3:8 m3=A’BC
B m4=AB’C’
Decoder
C m5=AB’C
m6=ABC’
m7=ABC
F0 = m0 + m3 F4 F3 F2 F1 F0
F1 = m2 + m7
F2 = m4 + m6 Diode - acts like a one-way
F3 = m0 + m1 + m2 + m5 conduit. Its presence causes the
F4 = m1 + m4 + m7 column to become ‘1’ when the
row is decoded.
m0=A’B’C’
m1=A’B’C
m2=A’BC’
A
3:8 m3=A’BC
B m4=AB’C’
Decoder
C m5=AB’C
m6=ABC’
m7=ABC
F4 F3 F2 F1 F0
A B C F4 F3 F2 F1 F0
0 0 0 0 1 0 0 1
0 0 1 1 1 0 0 0
0 1 0 0 1 0 1 0
0 1 1 0 0 0 0 1
1 0 0 1 0 1 0 0
1 0 1 0 1 0 0 0
1 1 0 0 0 1 0 0
ECEn 224 09 MUX © 2003-2008
1 1 1 1 0 0 1 0 Page 75 BYU
ROM Technologies:
Not Always Diode-Based
• PROM (Programmable Read Only Memory)
– Mask programmable
– Fusible Link
• EPROM (Erasable PROM)
– Can be erased with ultraviolet light
• EEPROM (Electronically Erasable PROM)
– Can be electrically erased
• Flash
– Can also be electronically erased
– Available in very high densities
– Used in cell phones, MP3 players, cameras, and more!
The details of these technologies are beyond the scope of this class.
F = AB + A’BC’ A B C F G H
G = A’B’C + C’ 0 0 0
H = AB’C’ + ABC’ + A’B’C 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F = AB + A’BC’ A B C F G H
G = A’B’C + C’ 0 0 0 0
H = AB’C’ + ABC’ + A’B’C 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
F = AB + A’BC’ A B C F G H
G = A’B’C + C’ 0 0 0 0 1 0
H = AB’C’ + ABC’ + A’B’C 0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 0 0
1 0 0 0 1 1
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 0 0 What size
ROM is this?
Just fill out the truth table