splc780D PDF

S P L C 780D
16COM/40SEG Controller/Driver
NOV. 04, 2004

Version 1.2
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Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product
may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC780D
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4

2. FEATURES.................................................................................................................................................................................................. 4
3. BLOCK DIAGRAM ...................................................................................................................................................................................... 4

4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5. COMPARISON OF SPLC780D AND SPLC780C ........................................................................................................................................ 5
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6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6
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6.1. OSCILLATOR .......................................................................................................................................................................................... 6
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6.2. CONTROL AND DISPLAY INSTRUCTIONS ................................................................................................................................................... 6
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6.3. INSTRUCTION TABLE............................................................................................................................................................................... 8
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6.4. 8-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET)................................................................................................ 9
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6.5. 4-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10
6.6. 8-BIT OPERATION AND 8-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10
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6.7. RESET FUNCTION .................................................................................................................................................................................11
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6.8. DISPLAY DATA RAM (DD RAM)............................................................................................................................................................ 13
6.9. TIMING GENERATION CIRCUIT............................................................................................................................................................... 13
C ER
6.10. LCD DRIVER CIRCUIT ....................................................................................................................................................................... 13
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6.11. CHARACTER GENERATOR ROM (CG ROM)....................................................................................................................................... 13
6.12. CHARACTER GENERATOR RAM (CG RAM)........................................................................................................................................ 13
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6.13. CURSOR/BLINK CONTROL CIRCUIT .................................................................................................................................................... 17
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6.14. INTERFACING TO MPU....................................................................................................................................................................... 18
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6.15. SUPPLY VOLTAGE FOR LCD DRIVE..................................................................................................................................................... 19
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6.16. REGISTER --- IR (INSTRUCTION REGISTER) AND DR (DATA REGISTER) ............................................................................................. 22
6.17. BUSY FLAG (BF) ............................................................................................................................................................................... 22
S AR
6.18. ADDRESS COUNTER (AC).................................................................................................................................................................. 22
6.19. I/O PORT CONFIGURATION ................................................................................................................................................................ 22
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7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 23
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 23
7.2. DC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) ..................................................................................................................... 23
F o
7.3. AC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) ..................................................................................................................... 24
7.4. DC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25)..................................................................................................................... 25
7.5. AC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25) ..................................................................................................................... 25
8. APPLICATION CIRCUITS ......................................................................................................................................................................... 27

8.1. R-OSCILLATOR .................................................................................................................................................................................... 27
8.2. INTERFACE TO MPU............................................................................................................................................................................. 27
8.3. SPLC780D APPLICATION CIRCUIT ....................................................................................................................................................... 27
8.4. APPLICATIONS FOR LCD ...................................................................................................................................................................... 27
9. CHARACTER GENERATOR ROM ........................................................................................................................................................... 27
9.1. SPLC780D - 01 .................................................................................................................................................................................. 27
9.2. SPLC780D - 02 .................................................................................................................................................................................. 27
9.3. SPLC780D - 03 .................................................................................................................................................................................. 27
9.4. SPLC780D - 08 .................................................................................................................................................................................. 27
9.5. SPLC780D - 11 .................................................................................................................................................................................. 27
Sunplus Technology Co., Ltd. 2 NOV. 04, 2004

Proprietary & Confidential Version: 1.2
SPLC780D
9.6. SPLC780D - 12 .................................................................................................................................................................................. 27

9.7. SPLC780D - 13 .................................................................................................................................................................................. 27
9.8. SPLC780D - 14 .................................................................................................................................................................................. 27
9.9. SPLC780D - 15 .................................................................................................................................................................................. 27
9.10. SPLC780D - 17 ............................................................................................................................................................................... 27
9.11. SPLC780D - 18 ............................................................................................................................................................................... 27
9.12. SPLC780D - 19 ............................................................................................................................................................................... 27
9.13. SPLC780D - 54 ............................................................................................................................................................................... 27
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10. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 27
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10.1. PAD ASSIGNMENT AND LOCATIONS ................................................................................................................................................... 27
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10.2. PACKAGE CONFIGURATION ................................................................................................................................................................ 27
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10.3. PACKAGE INFORMATION..................................................................................................................................................................... 27
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10.4. ORDERING INFORMATION................................................................................................................................................................... 27
11. DISCLAIMER............................................................................................................................................................................................. 27
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12. REVISION HISTORY ................................................................................................................................................................................. 27
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u IN
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S AR
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F o

SPLC780D
16COM/40SEG CONTROLLER/DRIVER
1. GENERAL DESCRIPTION 2. FEATURES

The SPLC780D, a dot-matrix LCD controller and driver from Character generator ROM: 10880 bits
SUNPLUS, is a unique design for displaying alpha-numeric, Character font 5 x 8 dots: 192 characters
Japanese-Kana characters and symbols. The SPLC780D Character font 5 x 10 dots: 64 characters
provides two types of interfaces to MPU: 4-bit and 8-bit interfaces. Character generator RAM: 512 bits
The transferring speed of 8-bit is twice faster than 4-bit. A single Character font 5 x 8 dots: 8 characters
Character font 5 x 10 dots: 4 characters
l
SPLC780D is able to display up to two 8-character lines. By
cascading with SPLC100 or SPLC063, the display capability can 4-bit or 8-bit MPU interfaces
be extended. The CMOS technology ensures the power saves in
ti a
Direct driver for LCD: 16 COMs x 40 SEGs
l y
the most efficient way and the performance keeps in the highest
rank.
Duty factor (selected by program):
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1/8 duty: 1 line of 5 x 8 dots
n
e
1/11 duty: 1 line of 5 x 10 dots
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if d se
1/16 duty: 2 lines of 5 x 8 dots / line
Built-in power on automatic reset circuit
n
Built-in oscillator circuit (with external resistor)
o U Support external clock operation

Low Power Consumption
C ER Package form: 80 QFP or bare chip available
s
u IN
3. BLOCK DIAGRAM
p l
OSC1
OSC2
u n T M Timing Generation Circuit

CL1,CL2
M
VDD
VSS
S AR Parallel to Serial Data Conversion Circuit
Busy Flag
5
Character
5
Character Cursor
40-bit
Shift
Register
D
DB0-DB3
r P Generator
ROM
Generator
RAM
Blink
Control
40
40
o
Circuit 40
8 8 Latch
DB4-DB7 8 Segments COM1-
Data
F
Circuit
Register x COM16
I/O 8
RS 16
7
R/W 7 Display 16-bit 16 Commons
Buffer
E Data RAM Shift
8 8 LCD
Instruction Instruction 80 Bytes Register
Power Register Decorder 7 Driver SEG1-
Supply SEG40
for LCD 7 Address
Drive :
Counter
(V1-V5)

SPLC780D
4. SIGNAL DESCRIPTIONS
Mnemonic PIN No. Type Description
VDD 33 I Power input
VSS 23 I Ground
OSC1 24 - Both OSC1 and OSC2 are connected to resistor for internal oscillator circuit. For
OSC2 25 external clock operation, the clock is input to OSC1.
V1 - V5 26 - 30 I Supply voltage for LCD driving.
E 38 I A start signal for reading or writing data.
R/W 37 I A signal for selecting read or write actions.
1: Read, 0: Write.
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RS 36 I A signal for selecting registers.
1: Data Register (for read and write)
0: Instruction Register (for write),
n n
Busy flag - Address Counter (for read).
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DB0 - DB3 39 - 42 I/O Low 4-bit data
DB4 - DB7 43 - 46 I/O High 4-bit data
CL1
CL2
M
31
32
34
o n U
O
O
O
Clock to latch serial data D.
Clock to shift serial data D.
Switch signal to convert LCD waveform to AC.
D 35
C ER O Sends character pattern data corresponding to each common signal serially.
SEG1 - SEG22
s
u IN
22 - 1 O
1: Selection, 0: Non-selection.
Segment signals for LCD.
SEG23 - SEG40
COM1 - COM16
p l
80 - 63
47 - 62 O Common signals for LCD.
u n T M
5. COMPARISON OF SPLC780D AND SPLC780C
Chip size
PAD Size
S AR SPLC780D
2860u*2450u
90u * 90u
SPLC780C
3140u*2690u
94u * 94u
Memo
Passivation Opening Window

Min. PAD Pitch
VIH@5V
r P 110u
2.5V
120u
2.2V
Note:
o
SPLC780D is very similar to SPLC780C. Because they are fabricated on the same foundry and user the same rule, they have the same DC/AC
characteristic and they are fully function compatible.

SPLC780D
6. FUNCTIONAL DESCRIPTIONS
6.1. Oscillator
SPLC780D oscillator supports not only the internal oscillator
S=1 I/D=1 It shifts the display to the left
operation, but also the external clock operation.
S=1 I/D=0 It shifts the display to the right
6.2. Control and Display Instructions

6.2.4. Display ON/OFF control
Control and display instructions are described in details as follows:
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
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6.2.1. Clear display
Code 0 0 0 0 0 0 1 D C B
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Code 0 0 0 0 0 0 0 0 0 1
D = 1: Display on, D = 0: Display off
It clears the entire display and sets Display Data RAM Address 0
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C = 1: Cursor on, C = 0: Cursor off
B = 1: Blinks on, B= 0: Blinks off
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in Address Counter.
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5 x 8 dot 5 x 10 dot
6.2.2. Return home
RS
o U
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
character font character font
Code 0 0 0 0
C ER
0 0 0 0 1 X
s
u IN
8th line
Cursor 11th line
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X: Do not care (0 or 1)
n p
It sets Display Data RAM Address 0 in Address Counter and the
M
display returns to its original position. The cursor or blink goes to
6.2.5. Cursor or display shift
displayed).
change.
u
S AR T
the most-left side of the display (to the 1st line if 2 lines are
The contents of the Display Data RAM do not
Without changing DD RAM data, it moves cursor and shifts
display.
Code 0 0 0 0 0 1 S/C R/L X X

6.2.3. Entry mode set
r P
During writing and reading data, it defines cursor moving direction
o
and shifts the display.
Code
RS
0 F
0 0 0 0 0 0 1 I/D S
Blink display alternately

I / D = 1: Increment, I / D = 0: Decrement.
S = 1: The display shift, S = 0: The display does not shift.
S/C R/L Description Address Counter

0 0 Shift cursor to the left AC = AC - 1
0 1 Shift cursor to the right AC = AC + 1
1 0 Shift display to the left. Cursor follows the display shift AC = AC
1 1 Shift display to the right. Cursor follows the display shift AC = AC

SPLC780D
6.2.6. Function set

Display data RAM can be read or written after this setting.
Code 0 0 0 0 1 DL N F X X
In one-line display (N = 0),
(aaaaaaa)2: (00)16 - (4F)16.
X: Do not care (0 or 1)
In two-line display (N = 1),
DL: It sets interface data length.
(aaaaaaa)2: (00)16 - (27)16 for the first line,
DL = 1: Data transferred with 8-bit length (DB7 - 0).
(aaaaaaa)2: (40)16 - (67)16 for the second line.
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DL = 0: Data transferred with 4-bit length (DB7 - 4).
y
It requires two times to accomplish data transferring.
N: It sets the number of the display line.
N = 0: One-line display.
6.2.9. Read busy flag and address
ti a n l
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N = 1: Two-line display.
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Code 0 1 BF a a a a a a a
F: It sets the character font.
e
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F = 0: 5 x 8 dots character font.
F = 1: 5 x 10 dots character font. When BF = 1, it indicates the system is busy now and it will not
N
0
F
0
No. of Display Lines
1
o n U
Character Font Duty Factor
5 x 8 dots 1/8
accept any instruction until not busy (BF = 0). At the same time,
the content of Address Counter (aaaaaaa)2 is read.
0 1 1
C ER 5 x 10 dots 1 / 11 6.2.10. Write data to character generator RAM or

display data RAM
s
1 X 2 5 x 8 dots 1 / 16
l u IN
It cannot display two lines with 5 x 10 dots character font.
Code
RS
1
0 d d d d d d d d
n p M
6.2.7. Set character generator RAM address
Code
RS
0 0
u 0 1 T
S AR
a a a a a a
It writes data (dddddddd)2 to character generator RAM or display
data RAM.
6.2.11. Read data from character generator RAM or
Address Counter.
r P
It sets Character Generator RAM Address (aaaaaa)2 to the display data RAM
o
Character Generator RAM data can be read or written after this
setting.
F
Code 1 1 d d d d d d d d
It reads data (dddddddd)2 from character generator RAM or

6.2.8. Set display data RAM address
display data RAM.
Code 0 0 1 a a a a a a a To read data correctly, do the following:

1). The address of the Character Generator RAM or Display Data
RAM or shift the cursor instruction.
It sets Display Data RAM Address (aaaaaaa)2 to the Address 2). The Read instruction.
Counter.

SPLC780D
6.3. Instruction Table
Execution time
Instruction Code
(Temp = 25)
Instruction Description
Fosc= Fosc= Fosc=
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
190KHz 270KHz 350KHz
Write "20H" to DDRAM
Clear Display 0 0 0 0 0 0 0 0 0 1 and set DDRAM address 2.16ms 1.52ms 1.18ms
to "00H" from AC
Set DDRAM address to
"00H" from AC and
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return cursor to its
Return Home 0 0 0 0 0 0 0 0 1 - 2.16ms 1.52ms 1.18ms
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original position if shifted.
e
are not changed.
Assign
n
The contents of DDRAM
cursor moving
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Entry Mode
0 0 0 0 0 0 0 1 I/D S direction and enable the 53s 38s 29s
Set
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shift of entire display
Set display
s
(D),
Display ON/
OFF Control
0 0
o0
C ER
0 0 0 1 D C B
cursor(C), and blinking of
cursor(B) on/off control
bit.
53s 38s 29s
s
Set cursor moving and
display shift control bit,
Cursor or
Display Shift
0
l
0
u IN 0 0 0 1 S/C R/L - - and the direction, without 53s 38s 29s
n p M
changing
data.
of DDRAM
T
Set interface data length
Function Set 0
u
S AR 0 0 0 1 DL N F - -
(DL: 8-bit/4-bit), numbers
of display line
2-line/1-line) and, display
(N:
53s 38s 29s
font type (F:5x10
Set CGRAM
0
r P 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0
dots/5x8 dots)
Set CGRAM address in
53s 38s 29s
o
Address address counter.
Set DDRAM Set DDRAM address in
Address
Read Busy Flag

F 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
address counter
Whether during internal
operation or not can be
53s 38s 29s
known by reading BF.

and Address 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
The contents of address
Counter
counter can also be
read.
Write Data to Write data into internal
1 0 D7 D6 D5 D4 D3 D2 D1 D0 53s 38s 29s
RAM RAM (DDRAM/CGRAM).
Read Data from Read data from internal
1 1 D7 D6 D5 D4 D3 D2 D1 D0 53s 38s 29s
RAM RAM (DDRAM/CGRAM).
Note1: --: dont care
Note2: In the operation condition under -20 ~ 75, the maximum execution time for majority of instruction sets is 100us, except two instructions, Clear
Display and Return Home, in which maximum execution time can take up to 4.1ms.

SPLC780D
6.4. 8-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. Instruction Display Operation

1 Power on. (SPLC780D starts initializing) Power on reset. No display.
2 Function set Set to 8-bit operation and select 1-line display line and character font.
0 0 0 0 1 1 0 0 X X
3 Display on / off control Display on.

_
0 0 0 0 0 0 1 1 1 0 Cursor appear.
l
4 Entry mode set Increase address by one.
_
a y
0 0 0 0 0 0 0 1 1 0 It will shift the cursor to the right when writing to the DD RAM/CG RAM.
5 Write data to CG RAM / DD RAM

Now the display has no shift.
Write " W ".
ti n l
6
1 0 0 1 0 1
Write data to CG RAM / DD RAM

0 1 1 1
W_
Write " E ".

e n
The cursor is incremented by one and shifted to the right.
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WE_
1 0 0 1 0 0 0 1 0 1 The cursor is incremented by one and shifted to the right.
7 : :
8 Write data to CG RAM / DD RAM
1 0 0 1 0 0
o
0 n 1
U
0 1
WELCOME_
Write " E ".
9 Entry mode set

0 0 0 0 0 0
C ER
0 1 1 1
WELCOME_
Set mode for display shift when writing
10
s
u IN ELCOME _
Write " "(space).
11
1 0 0 0 1
p l 0

0 0 0 0 The cursor is incremented by one and shifted to the right.
Write " C ".
M
LCOME C_
12
1 0 0 1 0
u n :
0
T
0 0 1 1
:
S AR
13 Write data to CG RAM / DD RAM Write " Y ".
COMPAMY_
14 Cursor or display shift Only shift the cursor's position to the left (Y).
COMPAMY_
15
0 0 0 0 0
r P
Cursor or display shift
1 0 0 X X
COMPAMY_
Only shift the cursor's position to the left (M).
o
0 0 0 0 0 1 0 0 X X
16
17
1 0 0
F
1 0
Cursor or display shift

0 0 0 0 0
0
1
1
1
1
1
1
X
0
X
OMPANY_
COMPAMY_
Write " N ".
The display moves to the left.
Shift the display and the cursor's position to the right.
18 Cursor or display shift Shift the display and the cursor's position to the right.
OMPANY_
0 0 0 0 0 1 0 1 X X
19 Write data to CG RAM / DD RAM Write " " (space).

COMPAMY_
20 : : :
21 Return home Both the display and the cursor return to the original position (address 0).
WELCOME_
0 0 0 0 0 0 0 0 1 0

SPLC780D

1 Power on. Power on reset. No display.
(SPLC780D starts initializing)
2 Function set Set to 4-bit operation.
RS R/W DB7 DB6 DB5 DB4
0 0 0 0 1 0
3 0 0 0 0 1 0 Set to 4-bit operation and select 1-line display line and character font.
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0 0 0 0 X X
4 0
0
0
0
0
1
0
1
0
1
0
0
_
Display on.
Cursor appears.
ti a l y
5 0 0 0 0 0 0 Increase address by one.
n n
0 0 0 1 1 0
_
e O
It will shift the cursor to the right when writing to the DD RAM / CG RAM.
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6 1 0 0 1 0 1 Write " W ".
W_
n
1 0 0 1 1 1 The cursor is incremented by one and shifted to the right.
o U
C ER

1 Power on.
s
u IN
Power on reset. No display.
2
(SPLC780D starts initializing)
Function set
p l Set to 8-bit operation and select 2-line display line and 5 x 8 dot
M
n
character font.
0 0 0 0 1 1 1 0 X X
4
Display on / off control
0 0
Entry mode set

0 u
S AR
0 0T 0 1 1 1 0
_ Display on.
Cursor appear.
Increase address by one.
P
0 0 0 0 0 0 0 1 1 0 _ It will shift the cursor to the right when writing to the DD RAM /
CG RAM.
o r
Write data to CG RAM / DD RAM W_
Write " W ".
6
7
1 0 0
F 1

0 1
:
0 1 1 1
WELCOME_
:
Write " E ".

:
8 Set DD RAM address WELCOME It sets DD RAM's address.

_
0 0 1 1 0 0 0 0 0 0 The cursor is moved to the beginning position of the 2nd line.
9 Write data to CG RAM / DD RAM WELCOME Write " T ".

T_
10 : : :
11 Write data to CG RAM / DD RAM WELCOME Write " T ".
TO PART_

SPLC780D

12 Entry mode set WELCOME When writing, it sets mode for the display shift.
0 0 0 0 0 0 0 1 1 1 TO PART_
13 Write data to CG RAM / DD RAM ELCOME Write " Y ".

O PARTY_
14 : : :
15 Return home WELCOME Both the display and the cursor return to the original position
TO PARTY
0 0 0 0 0 0 0 0 1 0 (address 0).
a l l y
ti
6.7. Reset Function
At power on, SPLC780D starts the internal auto-reset circuit and executes the initial instructions.
n n
The initial procedures are shown as
O
follows:
e
if d se
[ 8-Bit Interface ]
Power On
o n
W ait time > 15 ms
after VDD > 4.5V U W ait time > 40ms
After VDD > 2.7V
C ER
0 0 0 0 1 1
s
u IN
X X X X
BF cannot be checked before this instruction .
Function set ( Interface is 8 bits length . )
p l
W ait time > 4.1 ms
u
0 n 1 1
T M
0 0 0 X X X X
S ARW ait time > 100 us
0 0 0
r
0
P
1 1 X X X X
F o BF can be checked after the following

instructions .
Function set ( Interface is 8 bits length .
Specify the number of display lines and
character font . )
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 The number of display lines and character
0 0 0 0 1 1 N F X X font cannot be changed afterwards .
0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1
Display off
0 0 0 0 0 0 0 1 I/D S
Display clear
Initialization Ends Entry mode set

SPLC780D
[ 4-Bit Interface ]
Power On
W ait time > 15 ms W ait time > 40ms

after VDD > 4.5V After VDD > 2.7V
RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction .
0 0 0 0 1 1 Function set ( Interface is 8 bits length . )
W ait time > 4.1 ms
a l l y
n ti
n
0 0 0 0 1 1
e
O
if d se
W ait time > 100 us

0 0 0 0 1
o
1 n U BF cannot be checked before this instruction .
C ER
s
BF can be checked after the following
RS R/W DB7 DB6 DB5 DB4 instructions .
0 0 0 0
l u IN
1 0 Function set ( Set interface to be 4 bits length)
Interface is 8 bits length .
p
0 0 0 0 1 0
M
0 0 N F X X Function set ( Interface is 4 bits length .
0
0
0
0
u n 0
1
T
0
0
0
0
0
0
Specify the number of the display lines
and character font . )
0
0
0
S AR
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
The number of display lines and character
font cannot be changed afterwards .
Display off
0 0
r P 0 1 I/D S
Display clear
Entry mode set
F o Initialization Ends

SPLC780D
6.8. Display Data RAM (DD RAM)

The 80-bit DD RAM is normally used for storing display data. The relationships between Display Data RAM Address and LCDs
Those DD RAM not used for display data can be used as general position are depicted as follows.
data RAM. Its address is configured in the Address Counter.
1-line display , 80 display characters

1 2 3 4 5 6 79 80 Display position
Display data RAM
00 01 02 03 04 05 4E 4F
( Example ) 1-line display , 8 display characters
a l address
l y
1
00
2 3
01
4
02
5
03
6
04
7
05
8
06 07
Display position
Display data RAM
n ti n
O
address
e
( i ) Left shift
if d se
When the display shift operation is performed , the display data RAM's address moves as :
( ii ) Right shift
01 02 03 04
o n05
U06 06 07 08 4F 00 01 02 03 04 05 06
C ER
s
6.9. Timing Generation Circuit 6.11. Character Generator ROM (CG ROM)
the internal circuits.

l u IN
The timing generating circuit is able to generate timing signals to
In order to prevent the internal timing
Using 8-bit character code, the character generator ROM
generates 5 x 8 dots or 5 x 10 dots character patterns. It also
generated independently.
n p
interface, the MPU access timing and the RAM access timing are
M
can generate 192s 5 x 8 dots character patterns and 64s 5 x 10
dots character patterns.
6.10. LCD Driver Circuit u

S AR T
Total of 16 commons and 40 segments signal drivers are valid in
6.12. Character Generator RAM (CG RAM)
Users can easily change the character patterns in the character
generator RAM through program. It can be written to 5 x 8 dots,
the LCD driver circuit. When a program specifies the character
P
fonts and line numbers, the corresponding common signals output
r
drive-waveforms and the others still output unselected waveforms.
8-character patterns or 5 x 10 dots for 4-character patterns.
F o

SPLC780D
The following diagram shows the SPLC780D character patterns:

Correspondence between Character Codes and Character Patterns.
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0 1 2 3 4 5 6 7 8 9 A B C D E F
CG
0 RAM
(1)
l
CG
1 RAM
a y
(2)
2
CG
RAM
ti n l
n
(3)
3
CG
RAM
e O
if d se
(4)
CG
4 RAM
n
(5)
5
CG
RAM
(6)
o U
C ER
Lower 4-bit (D0 to D3) of Character Code (Hexadecimal)
CG
6 RAM
(7)
s
u IN
l
CG
7 RAM
(8)
8
CG
RAM
n p M
T
(1)
9
CG
RAM
(2)
CG
u
S AR
A RAM
P
(3)
B
CG
RAM
(4)
o r
F
CG
C RAM
(5)
CG
D RAM
(6)
CG
E RAM
(7)
CG
F RAM
(8)

SPLC780D
The relationships between Character Generator RAM Addresses, Character Generator RAM Data (character patterns), and Character
Codes are depicted as follows:
6.12.1. 5 x 8 dot character patterns
Character Code CG RAM Character Patterns

( DD RAM Data ) Address ( CG RAM Data )
b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 1 1 1 1 1
0 0 1 0 0 1 0
a l 0
Character
l y
ti
0 1 0 0 0 1 0 0 Pattern
0 0 0 0 X 0 0 0 0 0 0
0 1 1
X X X
0
n
0 1 0 0
n
Example (1)
O
1 0 0 0 0 1 0 0
1 0 1
e0 0 1 0 0
1
1
1
1
0
1 if d 0
0
0
0
1
0
s e
0
0
0
0
Cursor
Position
o n U 0
0
0
0
0
1
0
0
1
0
1
1
1
0
0
0
C ER
Character
0 1 0 0 0 1 0 0 Pattern
Example (2)
0 0 0 0 X
s0
u IN
0 1 0 0 1
0
1
1
0
1
0
X X X
0
0
0
0
1
1
0
0
0
0
p l 1 0 1 0 0 1 0 0
u n T M 1
1
1
1
0
1
0
0
1
0
1
0
1
0
0
0
S AR
Note1:
Note2:
r P
It means that the bit0~2 of the character code correspond to the bit3~5 of the CG RAM address.
These areas are not used for display, but can be used for the general data RAM.
o
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected.
Note4: " 1 ": Selected, " 0 " : No selected , " X " : Do not care (0 or 1).
F
Note5: For example (1), set character code (b2 = b1 = b0 = 0, b3 = 0 or 1, b7-b4 = 0) to display T .
display T character.
Note6: The bits 0-2 of the character code RAM is the character pattern line position.
That means character code (00) 16,and (08) 16 can
The 8th line is the cursor position and display is formed by logical OR
with the cursor.

SPLC780D
6.12.2. 5 X 10 dot character patterns
Character Code CG RAM Character Patterns

( DD RAM Data ) Address ( CG RAM Data )
b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 1 0 0 0 1
0 0 0 1 1 0 0 0 1
Character
0 0 1 0 1 0 0 0 1 Pattern
Example (1)
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
a
0
l 1
1
l y
0 0 0 0 X 0 0 X 0 0 0
0
1
1
0
1
1
0
X X X 1
1
n
0
0
0
0ti 0
0
1
1
n
0 1 1 1
e1 0 0 0 1
O
if d se
1 0 0 0 1 0 0 0 1
Cursor
1 0 0 1 1 1 1 1 1
Position
o n U
1
1
0
0
1
1
0
1
0 0 0 0 0
C ER 1 1 0 0
s
1 1 0 1 X X X X X X X X
u IN
1 1 1 0
p l 1 1 1 1
u n T M
Note1:
Note2:
S AR
It means that the bit1~2 of the character code correspond to the bit4~5 of the CG RAM address.
These areas are not used for display, but can be used for the general data RAM.
r P
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected.
Note4: " 1 : Selected, " 0 : No selected, " X : Do not care (0 or 1).
Note5: For example (1), set character code (b2 = b1 = 0, b3 = b0 = 0 or 1, b7-b4 = 0) to display U . That means all of the character codes (00) 16, (01) 16,
F
with the cursor. o
(08) 16,and (09) 16 can display U character.
Note6: The bits 0-3 of the character code RAM is the character pattern line position. The 11th line is the cursor position and display is formed by logical OR

SPLC780D
6.13. Cursor/Blink Control Circuit

This circuit generates the cursor or blink in the cursor / blink When the Address Counter is (07) 16, the cursor position is shown
control circuit. The cursor or the blink appears in the digit at the as belows:
Display Data RAM Address defined in the Address Counter.
b6 b5 b4 b3 b2 b1 b0
AC 0 0 0 0 1 1 1
In a 1-line display
a l l y
ti
digit 1 2 3 4 5 6 7 8 9 10 Display position
00 01 02 03 04 05 06 07 08 09
n
Display data RAM address
n
e
( Hexadecimal )
O
if d se
the cursor position
In a 2-line display
digit 1 2 3
o n 4
U5 6 7 8 9 10 Display position
1st line 00 01
C ER
02 03 04 05 06 07 08 09
Display data RAM address
2nd line 40 41
s42
u IN
43 44 45 46 47 48 49
( Hexadecimal )
p l the cursor position
u n T M
S AR
r P
F o

SPLC780D
6.14. Interfacing to MPU

There are two types of data operations: 4-bit and 8-bit operations. 4-busline (for 8-bit operation, DB7 to DB4). Secondly, the lower
Using 4-bit MPU, the interfacing 4-bit data is transferred by 4-bit data is transferred by 4-busline (for 8-bit operation, DB3 to
4-busline (DB4 to DB7). Thus, DB0 to DB3 bus lines are not DB0). For 8-bit MPU, the 8-bit data is transferred by 8-buslines
used. Using 4-bit MPU to interface 8-bit data requires two times (DB0 to DB7).
transferring. First, the higher 4-bit data is transferred by
RS
a l l y
R/W
n ti n
e O
if d se
E
Internal
operation
o n U Functioning
DB7 IR7
C ER IR3 Busy AC3
Not
AC3 D7 D3
s
busy
DB6 IR6
l u INIR2 AC6 AC2 AC6 AC2 D6 D2
DB5
n p
IR5
MIR1 AC5 AC1 AC5 AC1 D5 D1
DB4 u
S AR IR4 T IR0 AC4 AC0 AC4 AC0 D4 D0
r P
Instruction
Write
Busy flag
check
Busy flag
check
Data
Write
F o Example of 4-bit Data Transfer Timing Sequence

SPLC780D
RS
R/W
Internal
Functioning
operation
DB7 IR7 Busy Busy

Not
Busy
a l D7
l y
DB6 IR6 AC6 AC6
n
AC6
ti D6
n
DB5 IR5 AC5 AC5
e
AC5
O D5
DB4 IR4 AC4 AC4
if d AC4
s e D4
DB3
DB2
IR3
IR2
o n U
AC3
AC2
AC3
AC2
AC3
AC2
D3
D2
DB1 IR1
C ER AC1 AC1 AC1 D1
s
u IN
l
DB0 IR0 AC0 AC0 AC0 D0
n p
Instruction
Write
M
Busy flag
check
Busy flag
check
Busy flag
check
Data
Write
u
S AR T
6.15. Supply Voltage for LCD Drive
Example of 8-bit Data Transfer Timing Sequence
r P
Different voltages can be supplied to SPLC780Ds pins (V5 - 1) for obtaining LCD drive-waveform. The relationships between bias, duty
factor and supply voltages are shown as belows:
Supply
Voltage F o Duty Factor 1/8, 1/11
1/4
1/16
1/5
V1 VDD 1/4 VLCD VDD 1/5 VLCD

V5 VDD VLCD VDD VLCD

SPLC780D
6.15.1. The power connections for LCD (1/4 Bias, 1/5 Bias) are shown belows:
VDD ( +5.0V ) VDD ( +5.0V )
VDD
VDD
R R
V1 V1
R R
V2 V2
V3
V LCD
V3
a l VLCD
l y
ti
R R
V4 V4
n n
R
e R
O
if d se
V5 V5
VR VR
1 / 4 Bias
o
(1/8,1/11 Duty)
n U -V or Gnd
1 / 5 Bias
(1/16 Duty) -V or Gnd
C ER
The bypass-capacitor improves the LCD display quality.
s
u IN
p l VDD( +5.0V )
VDD
VDD( +5.0V )
M
VDD
u n T V1
R
C
V1
R
C
S AR V2
R
C
V2
R
C
r P V3
R
V3
R
C
F o V4
R
C
V4
R
R
C
C C
V5 V5
VR VR
1 / 4 Bias 1 / 5 Bias
(1/8,1/11 Duty) (1/16 Duty)
-V or Gnd -V or Gnd
The bias voltage must have the following relations:

VDD V1 V2 V3 V4 V5.

SPLC780D
6.15.2. The relationship between LCD frames frequency and oscillators frequency.
(Assume the oscillation frequency is 250KHz, 1 clock cycle time = 4.0s)
6.15.2.1. 1/8 Duty, TYPE-B waveform
400 clocks
1 2 7 8 1 2 7 8 1 2 7 8 1 2 7 8
VPP
V1
COM1 V2(V3)
V4
a l l y
ti
VSS
1 Frame 1 Frame
n n
1 frame = 4(s) x 400 x 8 = 12800(s) = 12.8ms
e O
if d se
1
Frame frequency 78.1(Hz)
12.8(ms)
o
6.15.2.2. 1/11 Duty, TYPE-B waveform n U
C ER 400 clocks
s
1 2 10 11 1 2 10 11 1 2
u IN
VPP
V1
l
COM1 V2(V3)
p
V4
u nVSS
T M 1 Frame 1 Frame
S AR1 frame = 4(s) x 400 x 11 = 17600(s) = 17.6ms
Frame frequency
1
17.6(ms)
5 6 .8(Hz)
r P
6.15.2.3. 1/16 Duty, TYPE-B waveform
F o 1 2
200 clocks
15 16 1 2 15 16 1 2
VPP
V1
COM1 V2
V3
V4
VSS
1 Frame 1 Frame
1 frame = 4(s) x 200 x 16 = 12800(s) = 12.8ms

1
Frame frequency 78.1(Hz)
12.8(ms)

SPLC780D
6.16. REGISTER --- IR (Instruction Register) and DR 6.19. I/O Port Configuration
(Data Register) 6.19.1. Input port: E
SPLC780D contains two 8-bit registers: Instruction Register (IR)
VDD
and Data Register (DR). Using combinations of the RS pin and
the R/W pin selects the IR and DR, see below:
PMOS
RS R/W Operation
sch
0 0 IR write (Display clear, etc.) NMOS
0 1 Read busy flag (DB7) and Address Counter

(DB0 - DB6)
a l l y
ti
1 0 DR write (DR to Display data RAM or
n
Character generator RAM) 6.19.2. Input port: R/W, RS
1 1 DR read (Display data RAM or Character
generator RAM to DR)
e n VDD
PMOS
O
VDD
if d se
PMOS
The IR can be written by MPU, but it cannot be read by MPU.

sch
6.17. Busy Flag (BF)
o n U
When RS = 0 and R/W = 1, the busy flag is output to DB7. As
NMOS
C ER
the busy flag =1, SPLC780D is in busy state and does not accept
6.19.3. Output port: CL1, CL2, M, D
s
any instruction until the busy flag = 0.
u IN
VDD
6.18. Address Counter (AC)
p l
The Address Counter assigns addresses to Display Data RAM PMOS
u n T M
and Character Generator RAM. When an instruction for address
is written in IR, the address information is sent from IR to AC.
After writing to/reading from Display Data RAM or Character
S AR
NMOS
Generator RAM, AC is automatically incremented by one (or
decremented by one). The contents of AC are output to DB0 -
DB6 when RS = 0 and R/W = 1.
r P
o
6.19.4. Input / Output port: DB7 - DB0
F VDD
VDD
VDD Enable
PMOS PMOS
sch
NMOS Data

SPLC780D
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics Symbol Ratings

Operating Voltage VDD -0.3V to +7.0V
Driver Supply Voltage VLCD VDD - 12V to VDD + 0.3V
Input Voltage Range VIN -0.3V to VDD + 0.3V
Operating Temperature TA -30 to +80
Storage Temperature TSTO -55 to +125
conditions see AC/DC Electrical Characteristics.
a l
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
l y
7.2. DC Characteristics (VDD = 2.7V to 4.5V, TA = 25)
n ti n
Characteristics Symbol
Limit
e
Unit
O
Test Condition
if d se
Min. Typ. Max.
Operating Current IDD - 0.2 0.4 mA External clock (Note)
n
Input High Voltage VIH1 0.7VDD - VDD V
Pins:(E, RS, R/W, DB0 - DB7)
Input Low Voltage
Input High Voltage
o U
VIL1
VIH2
-0.3
0.7VDD
-
-
0.55
VDD
V
V
Pin OSC1
Input Low Voltage
Input High Current C ER VIL2
IIH
-0.2
-1.0
-
-
0.2VDD
1.0
V
A Pins: (RS, R/W, DB0 - DB7)
Input Low Current
s
u IN
IIL -10.0 -50 -120 A VDD = 3.0V
Output High
Voltage (TTL)
p l VOH1 0.75VDD - - V
IOH = - 0.1mA
Pins: DB0 - DB7
Output Low
Voltage (TTL)
Output High
u n T M VOL1 - - 0.2VDD V
IOL = 0.1mA
Pins: DB0 - DB7
IOH = - 40A,
S AR
VOH2 0.8VDD - - V
Voltage (CMOS) Pins: CL1, CL2, M, D
Output Low IOL = 40A, Pins:
VOL2 - - 0.2VDD V
Voltage (CMOS) CL1, CL2, M, D
Driver ON Resistance
(COM)
r P RCOM - - 20 K
IO = 50A, VLCD = 4.0V
Pins: COM1 - COM16
(SEG)
LCD Voltage
F o
RSEG
VLCD
-
3.0
-
-
30
9.0
Note: FOSC = 250KHz, VDD = 3.0V, pin E = L, RS, R/W, DB0 - DB7 are open, all outputs are no loads.
K
V
IO = 50A, VLCD = 4.0V
Pins: SEG1 - SEG40
VDD-V5, 1/4 bias or 1/5 bias

SPLC780D
7.3. AC Characteristics (VDD = 2.7V to 4.5V, TA = 25)
7.3.1. Internal clock operation
Limit
Characteristics Symbol Unit Test Condition
Min. Typ. Max.
OSC Frequency FOSC1 190 270 350 KHz VDD = 3.0V, Rf = 75K2%
7.3.2. External clock operation
l
Limit
y
Min. Typ. Max.
External Frequency
Duty Cycle
FOSC2 125
45
250
50
350
55
KHz
%
ti a n l
Rise/Fall Time t r, t f - - 0.2 s
e n O
if d se
7.3.3. Write mode (Writing data from MPU to SPLC780D)
n
Limit
E Cycle Time
o
tC
UMin.
1000
Typ.
-
Max.
- ns Pin E
E Pulse Width
E Rise/Fall Time
C ER
tPW
tR , t F
450
-
-
-
-
25
ns
ns
Pin E
Pin E
Address Setup Time
s tSP1
u IN
60 - - ns Pins: RS, R/W, E
Address Hold Time
Data Setup Time
p l tHD1
tSP2
20
195
-
-
-
-
ns
ns
Pins: RS, R/W, E
Pins: DB0 - DB7
Data Hold Time
u n T M
tHD2 10
7.3.4. Read mode (Reading data from SPLC780D to MPU)

- - ns Pins: DB0 - DB7
S AR
Min.
Limit
Typ. Max.
Unit Test Condition
E Cycle Time
E Pulse Width
E Rise/Fall Time
r P tC
tW
tR , t F
1000
450
-
-
-
-
-
-
25
ns
ns
ns
Pin E
Pin E
Pin E
Address Setup Time
Address Hold Time
F o
Data Output Delay Time
tSP1
tHD1
tD
60
20
-
-
-
-
-
-
360
ns
ns
ns
Pins: RS, R/W, E
Pins: RS, R/W, E
Pins: DB0 - DB7
Data hold time tHD2 5.0 - - ns Pin DB0 - DB7

SPLC780D
7.4. DC Characteristics (VDD = 4.5V to 5.5V, TA = 25)
Limit
Min. Typ. Max.
Operating Current IDD - 0.55 0.8 mA External clock (Note)
Input High Voltage VIH1 2.5 - VDD V Pins:(E, RS, R/W, DB0 - DB7)
Input Low Voltage VIL1 -0.3 - 0.6 V VDD=5V
Input High Voltage VIH2 VDD-1 - VDD V Pin OSC1

Input Low Voltage VIL2 -0.2 - 1.0 V Pin OSC1
Input High Current IIH -2.0 - 2.0 A
A l
Pins: (RS, R/W, DB0 - DB7)
a
VDD = 5.0V
l y
ti
Input Low Current IIL -20 -125 -250
n
Output High IOH = - 0.1mA
VOH1 2.4 - VDD V
Voltage (TTL)
Output Low
VOL1 - - 0.4
e
V n Pins: DB0 - DB7
IOL = 0.1mA
O
if d se
Voltage (TTL) Pins: DB0 - DB7
Output High IOH = - 40A,
VOH2 0.9VDD - VDD V
Voltage (CMOS) Pins: CL1, CL2, M, D
Output Low
Voltage (CMOS)
o n VOL2
U - - 0.1VDD V
IOL = 40A, Pins:
CL1, CL2, M, D
(COM)
C ERRCOM - - 20 K
IO = 50A, VLCD = 4.0V
Pins: COM1 - COM16
s
u IN
RSEG - - 30 K
IO = 50A, VLCD = 4.0V
l
(SEG) Pins: SEG1 - SEG40
LCD Voltage VLCD 3.0 - 11 V VDD-V5, 1/4 bias or 1/5 bias
n p
Note: FOSC = 250KHz, VDD = 5.0V, pin E = L, RS, R/W, DB0 - DB7 are open, all outputs are no loads.
M
u
S AR
7.5.1. Internal clock operation T
7.5. AC Characteristics (VDD = 4.5V to 5.5V, TA = 25)
Limit
Min. Typ. Max.
OSC Frequency
r P FOSC1 190 270 350 KHz VDD = 5.0V, Rf = 91K2%
F
Characteristics
o
7.5.2. External clock operation
Symbol
Min.
Limit
Typ. Max.
Unit Test Condition
External Frequency FOSC2 125 250 350 KHz

Duty Cycle 45 50 55 %
Rise/Fall Time t r, t f - - 0.2 s

SPLC780D
7.5.3. Write mode (Writing Data from MPU to SPLC780D)
Limit
Min. Typ. Max.
E Cycle Time tC 500 - - ns Pin E

E Pulse Width tPW 230 - - ns Pin E
E Rise/Fall Time tR , t F - - 20 ns Pin E
Address Setup Time tSP1 40 - - ns Pins: RS, R/W, E
Address Hold Time tHD1 10 - - ns Pins: RS, R/W, E
Data Setup Time tSP2 80 - - ns
l
Pins: DB0 - DB7
a l y
ti
Data Hold Time tHD2 10 - - ns Pins: DB0 - DB7
7.5.4. Read mode (Reading Data from SPLC780D to MPU)
n n
Limit
e
Unit
O
Test Condition
if d se
Min. Typ. Max.
E Cycle Time tC 500 - - ns Pin E

E Pulse Width
E Rise/Fall Time
Address Setup Time
tW
o n
tR , t F
tSP1 U
230
-
40
-
-
-
-
20
-
ns
ns
ns
Pin E
Pin E
Pins: RS, R/W, E
Address Hold Time
C ER
tHD1 10 - - ns Pins: RS, R/W, E
Data Output Delay Time
Data hold time
s
u IN
tD
tHD2
-
5.0
-
-
120
-
ns
ns
Pins: DB0 - DB7
Pin DB0 - DB7
p l
7.5.5. Interface mode with LCD Driver (SPLC100A1)
Characteristics
u n T M
Symbol
Min.
Limit
Typ. Max.
Unit Test Condition
Clock setup time

S AR
Clock pulse width high
Clock pulse width low
tPWH
tPWL
tCSP
800
800
500
-
-
-
-
-
-
ns
ns
ns
Pins: CL1, CL2
Pins: CL1, CL2
Pins: CL1, CL2
Data setup time
Data hold time
r P tDSP
tHD
300
300
-
-
-
-
ns
ns
Pins: D
Pins: D
M delay time
F o tD -1000 - 1000 ns Pins: M

SPLC780D
7.5.6. Write mode timing diagram (Writing Data from MPU to SPLC780D)
V IH1 V IH1
RS
V IL1 V IL1
tSP1
tHD1
R/W
V IL1 V IL1
tPW
tF tHD1
V IH1 V IH1
E
V IL1 V IL1
tSP2
a l
V IL1
l y
ti
tR tHD2
DB7 - 0
V IH1
V IL1
Valid Data
V IH1
V IL1
n n
tC
e O
if d se
7.5.7. Read mode timing diagram (Reading Data from SPLC780D to MPU)
RS
o nV IH1
U V IH1
C ER
V IL1 V IL1
tSP1
tHD1
R/W
s
u IN
V IH1 V IH1
p l V IH1
tPW
V IH1
tF tHD1
E
u n T M tR
V IL1
tD
V IH1
V IL1
tHD2
V IH1
V IL1
S AR
DB0 - DB7 Valid Data
V IL1 V IL1
tC
r P
7.5.8. Interface mode with SPLC100A1 timing diagram
F o
CL1
0.9VDD
tPWH
0.9VDD
tPWH
tCSP 0.9VDD
CL2
0.1VDD 0.1VDD
tCSP tPWL
0.9VDD 0.9VDD
D 0.1VDD 0.1VDD
tDSP tHD
M
0.1VDD
tD

SPLC780D
8. APPLICATION CIRCUITS
8.1. R-Oscillator
The oscillation resistor Rf is used only for the internal oscillator operation mode.
OSC1 Rf : 75.0K2% ( when VDD = 3.0V)

Rf : 91K 2% ( when VDD = 5.0V)
Since the oscillation frequency varies depending on the OSC1 and OSC2
OSC2
l
pin capacitance, the wiring length to these pins should be minimized.
400 600
ti a l y
n n
Fosc ( KHz )
270
Fosc ( KHz )
400
200 270
e O
if d se
200
0
75 0
n
0 100 200 300 400 91
0 100 200 300 400
U
Rosc ( Kohms )
o
Rosc ( Kohms )
VDD = 3.0V VDD = 5.0V
C ER
8.2. Interface to MPU
s
u IN
l
8.2.1. Interface to 8-bit MPU (6805)
p
u n T M PA0
|
PA7
8
DB0
|
DB7
COM1
|
COM16
16 LCD PANEL
16 COMMONS
S AR 6805
PB0
PB1
E
RS
SPLC780D
SEG1
| 40
X
40 SEGMENTS
P PB2 R/W SEG40
o r
F
8.2.2. Interface to 8-bit MPU (Z80)
D0
| 8
DB0
|
COM1
16 LCD PANEL
|
D7 DB7 COM16
Z80 16 COMMONS
A1 7
| SPLC780D
E
A7 X
SEG1
A0 RS | 40
40 SEGMENTS
SEG40
IORQ
R/W
WR

SPLC780D
8.3. SPLC780D Application Circuit
DOT MATRIX LCD

PANEL
16
(8) 40 40 40 SPLC100A1 40
SPLC100A1 SPLC100A1
Y1-Y40 Y1-Y40 Y1-Y40
SEG40
COM16 (COM8)
SEG1
COM1
DL1 DR2 DL1 DR2 DL1 DR2

|
VDD DL2 VDD DL2 VDD DL2
l
FCS DR1 FCS DR1 FCS DR1
SHL1 SHL1 SHL1
SHL2
GND
VEE
CL1
CL2
M
SHL2
GND
VEE
CL1
CL2
M
SHL2
GND
VEE
ti a
CL1
CL2
M
l y
V1V2V3V4V5V6 V1V2V3V4V5V6
n
V1V2V3V4V5V6
n
VDD
e O
if d se
GND
CL1
CL2
n
M
U
V1
o
V2
V3
C ER
V4
V5
s
SPLC780D
l u IN R R R R R VR
n p VDD ( +5V )
M
C C C C C -V or Gnd
u
S AR T
r P
F o

SPLC780D
8.4. Applications for LCD
SPLC780D
COM1
LCD Panel
COM8 8 characters x 1 line
SEG1
SEG40
a
( Example 1 ) : 5 x 8 dots , 8 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ] l l y
n ti n
SPLC780D
e O
COM1
if d se LCD Panel
COM11
o n U
8 characters x 1 line
SEG1
C ER
s
u IN
SEG40
l
( Example 2 ) : 5 x 10 dots , 8 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
p
SPLC780D
u n T M
S AR
COM1
LCD Panel
COM8
COM9
r P 8 characters x 2 lines
COM16
F
SEG1o
SEG40
( Example 3 ) : 5 x 8 dots , 8 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]

SPLC780D
SPLC780D
COM1
COM8
SEG1
SEG40
COM9
a l l y
COM16
n ti n
e
( Example 4 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 5 Bias , 1 / 16 Duty ]
O
if d se
SPLC780D
o n U
SEG1 C ER
s
u IN
SEG20
COM1
p l
COM8
u n T M LCD Panel
4 characters x 2 lines
S AR
SEG21
r P
F o
SEG40
( Example 5 ) : 5 x 8 dots , 4 characters x 2 lines [ 1 / 4 Bias , 1 / 8 Duty ]

SPLC780D
9. CHARACTER GENERATOR ROM

9.1. SPLC780D - 01
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.2. SPLC780D - 02
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.3. SPLC780D - 03
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.4. SPLC780D - 08
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.5. SPLC780D - 11
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.6. SPLC780D - 12
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.7. SPLC780D - 13
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.8. SPLC780D - 14
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.9. SPLC780D - 15
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.10. SPLC780D - 17
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.11. SPLC780D - 18
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.12. SPLC780D - 19
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
9.13. SPLC780D - 54
a l l y
nti n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
10. PACKAGE/PAD LOCATIONS

10.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
10.2. Package Configuration

QFP 80L Top View
80 SEG23
79 SEG24
78 SEG25
77 SEG26
76 SEG27
75 SEG28
74 SEG29
73 SEG30
72 SEG31
71 SEG32
70 SEG33
69 SEG34
68 SEG35
67 SEG36
66 SEG37
65 SEG38
a l l y
n ti n
SEG22 1
e O
64 SEG39
if d se
SEG21 2 63 SEG40
SEG20 3 62 COM16
SEG19
SEG18
4
o n U
61 COM15
60 COM14
C ER
SEG17 6 59 COM13
SEG16 7 58 COM12
SEG15 8
u s N
57 COM11
56 COM10
l
SEG14 9
SEG13 10
pSPLC780D-I 55
54
COM9
COM8
M
SEG12 11
SEG11
SEG10
12
13
u n T XXX
53
52
COM7
COM6
SEG09
SEG08
SEG07
14
15
16
S AR 51
50
49
COM5
COM4
COM3
SEG06
SEG05
17
18
r P 48
47
COM2
COM1
SEG04
SEG03
SEG02
19
20
21
F o 46
45
44
DB7
DB6
DB5
SEG01 22 43 DB4
VSS 23 42 DB3
OSC1 24 41 DB2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
OSC2
R/W
VDD
DB0
DB1
CL1
CL2
RS
V1
V2
V3
V4
V5

SPLC780D
10.3. Package Information

QFP 80L Outline Dimensions Unit: Millimeter
D
D1
a l l y
E E1
SUNPLUS
SPLC780D
n ti n
YYWW
e O
if d se e
o n U b
C ER
s
u IN
p
c
l L1
A2 A
u n T M A1
Symbol
D
D1
S AR Min. Nom.
23.20 REF
20.00 REF
Max. Unit
Millimeter
Millimeter
E
E1
r P 17.20 REF
14.00 REF
Millimeter
Millimeter
e
b
A
F o 0.30
-
0.80 REF
0.35
-
0.45
3.40
Millimeter
Millimeter
Millimeter
A1 0.25 - - Millimeter
A2 2.50 2.72 2.90 Millimeter
c 0.11 0.15 0.23 Millimeter
L1 1.60 REF Millimeter
10.4. Ordering Information
Product Number Package Type
SPLC780D-NnnV-C Chip form

SPLC780D-NnnV-PQ05 Package form - QFP 80L
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).

SPLC780D
11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
a l
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
l y
ti
illustrated in this document are for reference purposes only.
n n
e O
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o

SPLC780D
12. REVISION HISTORY
Date Revision # Description Page
NOV. 04, 2004 1.2 1. VIH=2.5V@5V

2. Add COMPARISON OF SPLC780D AND SPLC780C
3. Modify IIL Min/Max
JUN. 16, 2004 1.1 Add ROM code 32 - 44
APR. 23, 2004 1.0 1. Remove Preliminary

2. Modify description: Execution time to Execution time (Temp = 25)
a l l y
7
ti
3. Add Note2 7
APR. 01, 2004 0.2 1. Add min. and max. value in Instruction Table
2. Add 8-bit/4-bit data transfer timing sequence example
n n 7
17 - 18
AUG. 06, 2003 0.1 Original

e O 33
if d se
o n U
C ER
s
u IN
p l
u n T M
S AR
r P
F o


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S P L C 780D

NOV. 04, 2004

1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4

3. BLOCK DIAGRAM ...................................................................................................................................................................................... 4

8. APPLICATION CIRCUITS ......................................................................................................................................................................... 27

Sunplus Technology Co., Ltd. 2 NOV. 04, 2004

9.6. SPLC780D - 12 .................................................................................................................................................................................. 27

Sunplus Technology Co., Ltd. 3 NOV. 04, 2004

1. GENERAL DESCRIPTION 2. FEATURES

o U Support external clock operation

C ER Package form: 80 QFP or bare chip available

u n T M Timing Generation Circuit

Sunplus Technology Co., Ltd. 4 NOV. 04, 2004

Passivation Opening Window

Sunplus Technology Co., Ltd. 5 NOV. 04, 2004

6.2. Control and Display Instructions

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Cursor 11th line

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 0 1 S/C R/L X X

Blink display alternately

S/C R/L Description Address Counter

Sunplus Technology Co., Ltd. 6 NOV. 04, 2004

6.2.6. Function set

C ER 5 x 10 dots 1 / 11 6.2.10. Write data to character generator RAM or

6.2.11. Read data from character generator RAM or

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

It reads data (dddddddd)2 from character generator RAM or

Code 0 0 1 a a a a a a a To read data correctly, do the following:

Sunplus Technology Co., Ltd. 7 NOV. 04, 2004

6.3. Instruction Table

font type (F:5x10

Read Busy Flag

known by reading BF.

Sunplus Technology Co., Ltd. 8 NOV. 04, 2004

No. Instruction Display Operation

3 Display on / off control Display on.

5 Write data to CG RAM / DD RAM

Write data to CG RAM / DD RAM

Write " E ".

9 Entry mode set

Write data to CG RAM / DD RAM

Write " C ".

Cursor or display shift

Shift the display and the cursor's position to the right.

19 Write data to CG RAM / DD RAM Write " " (space).

Sunplus Technology Co., Ltd. 9 NOV. 04, 2004

No. Instruction Display Operation

No. Instruction Display Operation

Entry mode set

Increase address by one.

Write data to CG RAM / DD RAM

Write " E ".

1 0 0 1 0 0 0 1 0 1 The cursor is incremented by one and shifted to the right.

8 Set DD RAM address WELCOME It sets DD RAM's address.

9 Write data to CG RAM / DD RAM WELCOME Write " T ".

Sunplus Technology Co., Ltd. 10 NOV. 04, 2004

No. Instruction Display Operation

13 Write data to CG RAM / DD RAM ELCOME Write " Y ".

S ARW ait time > 100 us

F o BF can be checked after the following

Initialization Ends Entry mode set