Chapter #8: Finite State Machine Design

Contemporary Logic Design

8-1

Example: Odd Parity Checker

Assert output whenever input bit stream has odd # of 1's

Present State Input Next State Output

Reset
Even 0 Even 0
Even 1 Odd 0
Odd 0 Odd 1
Even 0 Odd 1 Even 1
[0]

1 Symbolic State Transition Table

1

Odd
[1]
0

Present State Input Next State Output

0 0 0 0
State 0 1 1 0
Diagram 1 0 1 1
1 1 0 1

Encoded State Transition Table

8-2
 Next State/Output Functions : NS = PS xor PI; OUT = PS

NS Input Output
Input T Q
D Q CLK
CLK PS/Output
Q Q
R R
\Reset \Reset

D FF Implementation T FF Implementation

Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output 1 1 1 0 1 1 0 0 1 0 1 1

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

8-3

Basic Design Approach: Six Step Process

1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state mininimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3, 4, 5 covered later;

4, 5 generalized from the counter design procedure

8-4
 Example: Vending Machine FSM

General Machine Concept:

- deliver package of gum after 15 cents deposited
- single coin slot for dimes, nickels
- no change

Step 1. Understand the problem:

Draw a picture!
Block Diagram

N
Coin
Vending Open Gum
Sensor D
Machine Release
Reset FSM Mechanism

Clk

8-5

Step 2. Map into more suitable abstract representation

Tabulate typical input sequences:

- three nickels
- nickel, dime
- dime, nickel Reset
S0
- two dimes
- two nickels, dime
N D

S1 S2

Draw state diagram:

N D
D N
Inputs: N, D, reset
S3 S4 S5 S6
Output: open [open] [open] [open]
N D

S7 S8
[open] [open]

8-6
Step 3: State Minimization

Reset
0 Present Inputs Next Output
State D N State Open
N
0 0 0 0 0
5 0 1 5 0
D
1 0 10 0
N 1 1 X X
10
5 0 0 5 0
D 0 1 10 0
1 0 15 0
N, D
1 1 X X
15 10 0 0 10 0
[open] 0 1 15 0
1 0 15 0
1 1 X X
15 X X 15 1

reuse states
whenever Symbolic State Table
possible

8-7

Step 4: State Encoding

Present State Inputs Next State Output

Q1 Q0 D N D1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X

8-8
 Step 5. Choose FFs for implementation
Q1 Q1 Q1
Q1 Q0 Q1 Q0 Q1 Q0
DN DN DN

N N N
D D D

Q0 Q0 Q0
K-map for D1 K-map for D0 K-map for Open

Q1
D D1 Q1
D Q
Q0
N
CLK
R
Q
\ Q1
D1 = Q1 + D + Q0 N
\reset
N
\ Q0 OPEN D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q0
\N
D0
D Q
Q0
OPEN = Q1 Q0
Q1 CLK \ Q0
N RQ
Q1 \reset
D
8 Gates
8-9

Step 5. Choosing FF for Implementation

J-K FF

Present State Inputs Next State J1 K1 J0 K 0

Q1 Q0 D N D1 D0
0 0 0 0 0 0 0 X 0 X
0 1 0 1 0 X 1 X
1 0 1 0 1 X 0 X
1 1 X X X X X X
0 1 0 0 0 1 0 X X 0
0 1 1 0 1 X X 1
1 0 1 1 1 X X 0
1 1 X X X X X X
1 0 0 0 1 0 X 0 0 X
0 1 1 1 X 0 1 X
1 0 1 1 X 0 1 X
1 1 X X X X X X
1 1 0 0 1 1 X 0 X 0
0 1 1 1 X 0 X 0
1 0 1 1 X 0 X 0
1 1 X X X X X X

Remapped encoded state transition table

8-10
 J1 = D + Q0 N
Q1 Q1
Q1 Q0 Q1 Q0
DN DN K1 = 0

N N
D D J0 = Q0 N + Q1 D
Q0 Q0 K0 = Q1 N
K-map for J1 K-map for K1
Q1 Q0 Q1 Q1 Q0 Q1
DN DN

N
N N Q0 J Q Q1
D D D \ Q1
CLK KRQ
\ Q0

Q0 Q0 N
K-map for J0 K-map for K0 OPEN
Q1

D Q0
CLK J Q
\ Q1
Q \ Q0
K
N R

\reset 7 Gates

8-11

Moore Machine
Xi Zk
Inputs Combinational Outputs Outputs are function
Logic for
Outputs and solely of the current
Next State state
State Outputs change
State Register Clock Feedback
synchronously with
state changes

State
Register Mealy Machine
Xi Comb.
Inputs
Combinational
Logic for
Logic for Outputs depend on
Next State
Outputs state AND inputs
(Flip-flop Zk
Inputs) Outputs
Input change causes
Clock an immediate output
change
state
feedback Asynchronous signals

8-12
 State Diagram Equivalents

Mealy (N D + Reset)/0 N D + Reset Moore

Machine Reset/0 Reset Machine
0 0

[0]
Reset/0 Reset
N/0 N

5 5
N D/0 D/0 ND D
[0]

N/0 N

10 10
D/1 D
N D/0 [0] ND
N+D/1 N+D

15 15

[1] Reset
Reset/1

Outputs are associated Outputs are associated

with Transitions with State

8-13

States vs. Transitions

Mealy Machine typically has fewer states than Moore Machine
for same output sequence

0
0 0/0
0
Same I/O behavior [0]
0 0/0 1/0
1
Different # of states 1
0 1

1/1
[0]
1
2

[1] 1

Equivalent
ASM Charts

8-14
Timing Behavior of Moore Machines
Reverse engineer the following:

X J Q A
C Input X
X Output Z
KR Q \A
\B
FFa State A, B = Z
\Reset

Clk

X J Q Z
X C
KR Q \B
\A
FFb
\Reset

Two Techniques for Reverse Engineering:

Ad Hoc: Try input combinations to derive transition table

Formal: Derive transition by analyzing the circuit

8-15

Behavior in response to input sequence 1 0 1 0 1 0:

100

X
Clk
A
Z
\Reset
Reset X =1 X =0 X =1 X=0 X =1 X=0 X=0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00

A B X A+ B+ Z
0 0 0 ? ? 0
1 1 1 0
0 1 0 0 0 1
Partially Derived 1 ? ? 1
State Transition 1 0 0 1 0 0
Table 1 0 1 0
1 1 0 1 1 1
1 1 0 1

8-16
Synchronous Mealy Machine

Clock

Xi Zk
Inputs Combinational
Outputs
Logic for
Outputs and
Next State

State Register Clock state

feedback

latched state AND outputs

avoids glitchy outputs!

8-17

Finite State Machine Word Problems

Mapping English Language Description to Formal Specifications

Four Case Studies:

Finite String Pattern Recognizer

Complex Counter with Decision Making

Traffic Light Controller

Digital Combination Lock

We will use state diagrams and ASM Charts

8-18
 Finite String Pattern Recognizer

A finite string recognizer has one input (X) and one

output (Z). The output is asserted whenever the input
sequence 010 has been observed, as long as the
sequence 100 has never been seen.

Step 1. Understanding the problem statement

Sample input/output behavior:

X: 00101010010
Z: 00010101000

X: 11011010010
Z: 00000001000

8-19

Step 2. Draw State Diagrams/ASM Charts for

the strings that must be recognized ( 010 , 100).

Reset
S0
[0] Moore State Diagram
Reset signal places
S1 S4 FSM in S0
[0] [0]

S2 S5
[0] [0]

S3 S6
Outputs 1 Loops in State
[1] [0]

8-20
 Exit conditions from state S3: have recognized 010
if next input is 0 then have 0100!
if next input is 1 then have 0101 = 01 (state S2)

Reset
S0
[0]

S1 S4
[0] [0]

S2 S5
[0] [0]

S3 S6
[1] [0]

8-21

Exit conditions from S1: recognizes strings of form 0 (no 1 seen)

loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form 1 (no 0 seen)

loop back to S4 if input is 1

Reset
S0
[0]

S1 S4
[0] [0]

S2 S5
[0] [0]

S3 S6
[1] [0]

8-22
S2, S5 with incomplete transitions

S2 = 01; If next input is 1, then string could be prefix of (01)1(00)

S4 handles just this case!

S5 = 10; If next input is 1, then string could be prefix of (10)1(0)

S2 handles just this case!

Reset
S0
[0]

S1 S4
[0] [0]
Final State Diagram

S2 S5
[0] [0]

S3 S6
[1] [0]

8-23

Review of Process:

Write down sample inputs and outputs to

understand specification

Write down sequences of states and

transitions for the sequences to be
recognized

Add missing transitions; reuse states as

much as possible

Verify I/O behavior of your state diagram

to insure it functions like the specification

8-24
Complex Counter
A sync. 3 bit counter has a mode control M.
if M = 0, the counter counts up in the binary sequence.
if M = 1, the counter advances through the Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111

Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior:

Mode Input M Current State Next State (Z2 Z1 Z0)
0 000 001
0 001 010
1 010 110
1 110 111
1 111 101
0 101 110
0 110 111

8-25

One state for each output combination

Add appropriate arcs for the mode control
Reset
S0
[000]

S1
[001]

S2
[010]

S3
[011]

S4
[100]

S5
[101]

S6
[110]

S7
[111]

8-26
Digital Combination Lock
"3 bit serial lock controls entry to locked room.

Inputs are RESET, ENTER, 2 position switch for bit

of key data.

Locks generates an UNLOCK signal when key

matches internal combination. ERROR light
illuminated if key does not match combination.

Sequence is:
(1) Press RESET
(2) enter key bit
(3) Press ENTER
(4) repeat (2) & (3) two more times.

8-27

Problem specification is incomplete:

how do you set the internalcombination?
exactly when is the ERROR light asserted?

Make reasonable assumptions:

hardwired into next state logic vs. stored in internal
register
assert as soon as error is detected vs. wait until full
combination has been entered

Our design: registered combination plus error after full

combination

8-28
Understanding the problem: draw a block diagram

RESET
Operator Data ENTER UNLOCK
KEY-IN
Combination
Lock FSM ERROR
L0
Internal
Combination L1
L2

Inputs: Outputs:
Reset Unlock
Enter Error
Key-In
L0, L1, L2

8-29

Reset + Enter

Equivalent State Diagram Reset

Start

Reset Enter

Comp0
KI = L0 KI L0

Enter Enter
Idle0 Idle0'

Enter Enter

Comp1 Error1
KI L1
KI = L1
Enter
Enter
Idle1 Idle1'

Enter Enter

Comp2 Error2

KI = L2 KI L2

Reset Reset
Done Error3
[Unlock] [Error]

Reset Reset

Start Start

8-30