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6SHFLI\LQJ 3$/V ZLWK $%(/ 6SHFLI\LQJ 3$/V ZLWK $%(/
3+ 3$/ module bcd2excess3
title 'BCD to Excess 3 Code Converter State Machine'
u1 device 'p10h8'; 3+ 3$/ module bcd2excess3
title 'BCD to Excess 3 Code Converter State Machine'
u1 device 'p12h6';
"Input Pins
X,Q2,Q1,Q0,D11i,D12i pin 1,2,3,4,5,6; "Input Pins
X, Q2, Q1, Q0 pin 1, 2, 3, 4;
"Output Pins
D2,D11o,D12o,D1,D0,Z pin 19,18,17,16,15,14; "Output Pins
D2, D1, D0, Z pin 17, 18, 16, 15;
INSTATE = [Q2, Q1, Q0];
S0 = [0, 0, 0]; INSTATE = [Q2, Q1, Q0]; OUTSTATE = [D2, D1, D0];
S1 = [0, 0, 1]; S0in = [0, 0, 0]; S0out = [0, 0, 0];
S2 = [0, 1, 1]; S1in = [0, 0, 1]; S1out = [0, 0, 1];
S3 = [1, 1, 0]; S2in = [0, 1, 1]; S2out = [0, 1, 1];
S4 = [1, 0, 0]; S3in = [1, 1, 0]; S3out = [1, 1, 0];
S5 = [1, 1, 1]; S4in = [1, 0, 0]; S4out = [1, 0, 0];
S6 = [1, 0, 1]; S5in = [1, 1, 1]; S5out = [1, 1, 1];
S6in = [1, 0, 1]; S6out = [1, 0, 1];
equations
D2 = (!Q2 & Q0) # (Q2 & !Q0); equations
([SOLFLW HTXDWLRQV D1 = D11i # D12i; D2 = (!Q2 & Q0) # (Q2 & !Q0);
D11o = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0); D1 = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0) #
IRU SDUWLWLRQHG D12o = (!X & Q2 & !Q0) # (Q1 & !Q0); (!X & Q2 & !Q0) # (Q1 & !Q0);
RXWSXW IXQFWLRQV D0 = !Q0; 6LPSOHU HTXDWLRQV D0 = !Q0;
Z = (X & Q1) # (!X & !Q1); Z = (X & Q1) # (!X & !Q1);

end bcd2excess3; end bcd2excess3;

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module bcd2excess3 state_diagram SREG

title 'BCD to Excess 3 Code Converter' state S0: if Reset then S0
u1 device 'p16r4'; else if X then S2 with Z = 0 0
else S1 with Z = 1 )RXU NLQGV RI WUDQVLWLRQV IRU HDFK VWDWH
"Input Pins state S1: if Reset then S0
Clk, Reset, X, !OE pin 1, 2, 3, 11; else if X then S4 with Z = 0 no
 WR 6WDWH  &/5
else S3 with Z = 1 CLR signals
"Output Pins state S2: if Reset then S0 n
D2, D1, D0, Z pin 14, 15, 16, 13; else if X then S4 with Z = 1  WR QH[W VWDWH LQ VHTXHQFH &17 asserted
else S4 with Z = 0
SREG = [D2, D1, D0]; CNT LD
state S3: if Reset then S0  WR DUELWUDU\ QH[W VWDWH /'
S0 = [0, 0, 0]; else if X then S5 with Z = 1
S1 = [0, 0, 1]; else S5 with Z = 0
S2 = [0, 1, 1];  ORRS LQ FXUUHQW VWDWH
S3 = [1, 1, 0];
state S4: if Reset then S0 n+1 m
else if X then S6 with Z = 0
S4 = [1, 0, 0]; else S5 with Z = 1
S5 = [1, 1, 1]; state S5: if Reset then S0
S6 = [1, 0, 1]; else if X then S0 with Z = 1
else S0 with Z = 0
state S6: if Reset then S0
else if !X then S0 with Z = 1 &DUHIXO
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end bcd2excess3;
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1 1 0 1 1 1 0 1 1 1 1 X X X
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