Chng 3

NG DNG FPGA TRONG

THIT K CC MODULE
IU KHIN

1
 I. MT S LU KHI THIT K
1.1. Cc bin ch c gn trong 1 khi always, khng c gn trong
nhiu khi always khc

reg [7:0] a, b; reg [7:0] a, b;

initial a = 4; initial a = 4;

always @(posedge clk) begin always @(posedge clk or posedge reset)

a = b + 2; begin
end if (reset == 1)
a = 0;
always @(posedge reset) begin
else
a = 0;
a = b + 2;
end
end

2
Trng H Bch Khoa TP.HCM
 I. MT S LU KHI THIT K
1.2. pht hin xung cnh ln ca cc tn hiu, dng xung clk tn s cao
chn vo

module demxung_encoder (clk, enc, D); module demxung_encoder (clk, enc, D);
input clk, enc; input clk, enc;
output [7:0] D; output [7:0] D;
reg [7:0] D = 8h00; reg [7:0] D = 8h00;
reg pre_enc = 0; reg pre_enc = 0;

always @(posedge clk) begin always @(posedge clk) begin

pre_enc <= enc; pre_enc <= enc;
if ({pre_enc, enc} == 2b01) end
D <= D + 1;
always @(posedge clk) begin
end
if ({pre_enc, enc} == 2b01)
D = D + 1;
end

3
Trng H Bch Khoa TP.HCM
 I. MT S LU KHI THIT K
1.3. Dng bin tm cp nht gi tr cc b m

module do_dorongxung (clk, enc, D); module do_dorongxung (clk, enc, D);
input clk, enc; input clk, enc;
output [7:0] D; output [7:0] D;
reg [7:0] D = 8h00; reg [7:0] D = 8h00, temp = 8h00;
reg pre_enc = 0; reg pre_enc = 0;
always @(posedge clk) begin always @(posedge clk) begin
pre_enc <= enc; pre_enc <= enc;
if ({pre_enc, enc} == 2b01) if ({pre_enc, enc} == 2b0x)
D <= 0; temp <= 0;
else if ({pre_enc, enc} == 2b11) else if ({pre_enc, enc} == 2b11)
D <= D+1; temp <= temp+1;
end else if ({pre_enc, enc} == 2b10)
D <= temp;
end

4
Trng H Bch Khoa TP.HCM
 I. MT S LU KHI THIT K
1.4. V du 1: Vit chng trnh verilog o tn s

- Gi tr D c cp nht sau mi module do_tanso (clk, enc, D);

input clk, enc;
cnh ln ca xung enc.
output [7:0] D;
- Tn s xung clk chn rt ln so reg [7:0] D = 8h00, temp = 8h00;
vi tn s ca xung enc reg pre_enc = 0;
- Nu b m D vt qu gi tr always @(posedge clk) begin
0xFF th s lun bng 0xFF
end

5
Trng H Bch Khoa TP.HCM
 I. MT S LU KHI THIT K
1.4. V du 2: Vit chng trnh verilog o lch pha 2 tn hiu

- Gi tr D c cp nht sau mi module do_dolechpha (clk, encA, encB, D);

cnh ln ca xung encB. input clk, encA, encB;
- Nu b m D vt qu gi tr output [7:0] D;
reg [7:0] D = 8h00, temp = 8h00;
0xFF th s lun bng 0xFF
reg pre_enc = 0;
- Gi s encA lun lun nhanh

pha hn encB

6
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
S kt ni phn cng cc module iu khin

7
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
1. Module c xung encoder

8
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
1. Module c xung encoder
u vo clk, encA, encB, rst, x4
u ra 8 bit D[15:0]
Khi rst = 1: D[15:0] = 16h8000
Khi rst = 0: D[15:0] m ln,
xung theo xung encA, encB
m x1, x2, x4

module encoder (clk,encA,encB,x4,rst,D);

input clk, encA, encB, rst;
input [1:0] x4;
output [15:0] D;
reg [15:0] D = 16h8000;

9
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
2. Module c cm bin siu m

> 50 ms

Distance (cm) = Time (us) / 58

10
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
2. Module c cm bin siu m
u vo clk (1us), EchoPulse module sfr04 (clk, EchoPusle, Trigger, D);
u ra 16 bit D[15:0], Trigger input clk, EchoPuse;
Chn Trigger c rng xung output Trigger;
output [15:0] D;
10us, lp li vi chu k T = 50ms
reg [15:0] D = 16h0000;
(Chnh T = 1ms khi m phng)

Ng ra D[15:0] cp nht khi
c cnh xung ca EchoPulse.
(n v o us).
Nu D = 0xFFFF th khng
c tng D.

11
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
3. Module ni suy cho my CNC, robot

12
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
3. Module ni suy cho my CNC, robot

13
Trng H Bch Khoa TP.HCM
II. THIT K CC MODULE IU KHIN
3. Module ni suy cho my CNC, robot

(Max Pulse input 200kHz )

14
Trng H Bch Khoa TP.HCM
 II. THIT K CC MODULE IU KHIN
3. Module ni suy cho my CNC, robot
- Thut ton ni suy ng thng theo phng php xung chun

- dT1: tng trc X

- dT2: tng trc Y
- T: thi gian lp li
15
Trng H Bch Khoa TP.HCM
 II. THIT K CC MODULE IU KHIN
3. Module ni suy cho my CNC, robot
u vo clk (1us), WR, LS module servo (clk,WR,LS, dT,T, Pulse,Dir);
u vo T[7:0], dT[7:0] input clk, WR, LS;
input [7:0] T, dT;
u ra Pulse, Dir
output Pulse, Dir;
Khi c xung cnh ln ca WR,
dT s np gi tr mi. always @(posedge clk) begin
Khi LS = 1, ng ra Pulse = 0, acc = acc + dT;
LS = 0, Pulse xut ra theo ni suy. if (acc > T) begin
dT[7] qui nh bit du cho Dir, acc = acc - T; pinout = 1;
dT[7] = 1, Dir = 1. end
else pinout = 0;
dT [7] = 0, Dir = 0.
end

assign Pulse = ~clk & pinout;

16
Trng H Bch Khoa TP.HCM