PART I: SOLUTIONS CHAPTER L (Components of a computer: ALU and Control Unit (CPU), Memory, Input, and Output. Functions of various components: CPU: It processes and stores binary data, wansfers data from and to memory and VO devices, and provides timing to all the operations. It includes ALU, register arrays, and control unit. ‘The ALU perfonns the arithmetic and logic operations, and the control unit provides timing. ‘Input - provides binary data as an input to the CPU. Output - accepts binary data from the CPU. A microprocessor functions as the CPU of a microcomputer, and includes the ALU, register arrays, and the control unit on one chip; itis manufactured using the LSL technology. On the other hand, the CPU is designed with various discret boards, Functionally, beth are similay however, technology and processes used for designing is different A microprocessor is one component of a microcomputer, and the microcomputer is ‘complete computer consists of a microprocessor, memory, input, and output ‘See Summary: Scale oF Totagration Four bytes. ‘The machine language of the 8085 are the comamands to the microprocessor given in binary. ‘These are the binary instructions the processor can understand and execute. ‘The assembly language comprise of mnemonics (group of letiers to represent commands) assigned by the ‘manufacturer for the convenience of the users, 9, 10, 11, See Summary: Computer Languages 2. ‘The assembly language mnemonics represent instructions to the microprocessor: therefore. when they are wanslated into machine language, there is one-to-one correspondences between the mnemonics and the machine code. The assembly language programs are compact, require less memory space, and are efficient. ‘The high level languages arc written, in English- like statements, and when these statements are translated in machine language, the ‘object code tends to be large. and requires large memory. ‘The execution of the programs ‘written in high level languages is less efficient than that of assembly language programs13, 14. See Summary: Computer Languages 15. 16, ASCII codes in Hex: A= a1, 5A, and m=6D s Summary: Computer Languages CHAPTER? 1 2 10 12, Memory Read, Memory Write, VO Read, and U0 Wate, A bus is group of ines (wires or conductors) which cary digital informasion, “The function ofthe address busi to camy’a binary address of'a memory jcation or an YO device. ‘The address bus is unidirectional, and dhe information flows from the MPU t9 ‘peripherals and memory _A microprocessor with 14addreas lines is capable of addressing 16K (2) memory locations 21 adress tines. ‘Data bytes are transferred in both dizetions between the MPU and memory/perpheral. TOR (VO Read), 1OW (VO Write), MEMR (Memory Read), end MEMW (Memory Writ). In memory write operation, the control siznal required is MEMW, and the dirotion of the data flow is fom the MPU to memory. ‘The accumulators an 8-bitregister and itiea partof the ALU. All8-bt arithmetic and logic ‘operations are performed in relation to the accumulator content, and theresult i storedin the steurnulator (with a few exceptions) A fing i the output of a given Mip-flop to indieate certain data conditions. ‘The program counter and the stack pointer store memory sddresses of 16 bits. ‘The program counter always points to the next memory Tocation; therefore, the content of the program counter will be 2055H. 128 registers and 128 X4 = 512 memory cells. 1024 bits are can be stored by this chip; however, it can not be specified as 2 128-byte _memary chip because the byte indicates § bit memory registers; this chip has 4-bit registers.15, 16. v7. 18. 18. 21 2, 2 2, 2s. 26 21, 28, 29, 30, 3 32. 33. 34 .bit wort size, 8 chips. 4 chips 32 chips ‘The WR signal enables the input buffer of a memory chip co that information can be stored (orien) in the selected memory register 1 address tines, ‘The staring address is FBOOH, and the memory map is FSO0H to FBFFH. “The staring adress ie: BOOOH. ‘The address ranges fom FFOOH to FFFFH. “The address ofthe selected register: 1000 0000 0100 0111 = $0474 ‘The memory map ranges fora 2000H to 23FFH. “The address of the selected register: 0010 0000 1111 1000 = 20F8H4 8 address lines are required for a peripheral UO port, aad 16 address lines are required fr a memory-mapped VO por ‘Tri-state devices ae logie devices with tee states; the third state is high impedance, In a ‘bus-orlented system, devices are connected in parallel, and the buses are capable of diving fone TTL logic device. The MPU communicates with one peripheral at a time, snd other peripherals are placed in high impedance to avoid bus loading High impedance state. From B10 A. None. The decoder is not enabled: all output lines will be hi “The line 6 (00, 001 (Complement of 1 10)35, ‘A transparent latch ga flip-flop; its ouput changes according to input when the lock signal is high, and it latches the input when the elock goes low. The latch is necessary for output devices to rotain the result, otherwise, the resule will disappear. 36. The high-order address lines: A12-A1S, the low-order address lines: AO-A10, and the don't care line: ALL 37. ‘This answer assumes the memory chips are 2048 X 4: AIS AI4AI3 AZ ALL ALO AS AS A7 AG AS A4.A3 AZ. AL AG 1 1 1 1 0 000000000 0 o=F00oH 1 | borot ab aad ad abd tad PRE 38. The memory occupics the memory space ftom FOOOH to FFFFEL The don't care line ALL ‘gencrates additional address range. This is a 2K memory chip that oceupies 4K of memory Space in the map, thus wasting 2K of memory space. IF A1 is assured to be at logic O as in @. 27, the address range is: FOOOH to F7FEH and if tis assumed to be at logic 1, the [adress range (also called foldback memory space) is: F800H to FFFFH. CHAPTER 3 “The ALE signal goes high at the boginning of each machine cycle indicating the availability ‘of an address on the address bus, and the signal is used to latch the low-order address bus. ‘The 1O/M signal ie a satus signal indicating whether the machine cycle is VO or memory ‘operation. ‘The TO/M signal is combined with the RD and WR control signals to generate TOR, 1OW, MEMR and MEMW control signals. ‘The low-order bus AD7-ADO is used for two purposes. In the carlcr part of a machine ceyele, the bus is used forthe low order address of a memory location the 808S is accessing. fad in the latter part of the cycle the bus ie used for data. By demultiplexing the bus, he ‘Madress and the data are kept separate. 1n Fig. 3.2, the input signal RD ané WR cannot be low atthe same time. Therefore, the ‘valid combinations ofthe input signals ae:u 2. 13. M4. JOM RD WR Output Signat © 9 0 Oy nvalid. «RD sn WR cannot be active simultaneously © 9 1G) MEM Mond RD ctive © 1 0) MEMW Mand WR active © 1 1G, relevant Both RD and WR are inactive 10 6 Invalid RD and WR cannot be active imultancously 1 0 Lt oO TOR IO and RD active 1 1 0 & TOW 10 and WR active 2 1 1G) eelevant Both RD and WR are inactive See the answer of 03. {In Fig, 323, the 7415139 is enabled when 1O/M is low, Therefore, the following memory ‘contol signale cat be generate. RD WR Decoder Output © 0 Oy-tnvaid © 1 0) MEM 10 O.-MEMW 11 O,-No operation ‘The cutput of the latch will be OSH; however, it will be mot be latched until the ALE goet low. ‘The output of the latch is OSH. At T2, the ALE i low; therefore, the latch will ot be enabled, and it will continue te hold the previously latched byte (OSE). ‘The crystal frequency should be ~ 2.2 MHz because the oscillator logic divides the input requency by tw. See the steps on page 66/67, Exsenple 3.1 ‘The sum of 87H + 79H = 10GH. Therefore, the accumulszor will have OOH. and the as willbeS=0,C¥=1.2=1 2060H. The program counter always points to the next machine code tobe fetched. IST X 2 micro-tec = 2.6 miero-see (ALS.A8)= 20H, (AD?-ADO)= 47H, (PC) = 2076 RD and JOM are asserted low. as19. 20. 2 23, 25, 26. 28. ‘The second machine eycle is Memory Read; the processor reads the contents of memory in register B, and the control signal is RD, “The fourch machine eyele is Memory Read; the processor reads the contents of memory in the accuanlator. (A15-A0) = 2050, (AD7-ADO) as data bus = Contents of location 205014 (Refer to Instruction Sot on pages 696-659) SUB BOF (Opeode Fetch) ADI 47H = OF, MR (Memory Read) ‘STA 20501 ~ OF, MR, MR, MW (Memory Write) PUSHB = OF, MW, MW. ‘Memory map: 6000H to 6FFFH. ‘Memory map: S000H to 8FFFH OR gate Connect RD to OF of the memory chip and IO/M to F2 of the decoder. AISAISAISAIZ Al A109 ABA7 AGAS ASA A2 AL AO 0 0 1 6 1 6 60 6 00 00000 =2800% 1 H Bobb aaa aaa aren ‘Total range 16K. Map = S000H to BFFFEL A data byte entered at location 2100H will be accepted and stored at location 2000H. The ‘adavees lines 410, AO, and AS aronotbeing used for memory addressing: therefore, they can ‘assume 0 of 1 (dont care) logie state wich results into multiple addresses forthe same ‘memory locations ‘Memory address: 0800H-OSFFH, and the foldback memory ranges from 0900 to OF FFE. ‘Memory map: 3800H - 3FFFEL {In Figure 3.19, tree lines are dant care which can have (2) eight combinations. This the ‘memory chip Will occupy the memory space equal to oight times is size ROMI: 0000H - LFFFH, ROM2: E0001 - FFFFH, R/WMI: 8000# - S3FFH30. 31. 32. 33 24 3s. 36. 3. -Meinory map: 8000H to 83FFH (Asnume all don't care Lines st 0) Foldback Memory: 8400H1 to 9FFFH ‘The adress range: 0000H to 3FFFH ‘The address range: 4000H to 7FFFH ‘The primary address range: OO00H to 1FFFH (Aseuines A13 ~0) ‘The foldback or the mirror address range: 200041 to 3FFFHL ‘The mirtor address range: S000H to 9FFFIL ‘The adress range when ¥1 is asserted: 4000 to 7FFFH ‘The total address range is : 4000H to BEFFFEL Fora 16K memory chip. when A141, the address ranges from 4000H to 7FFFH as in Q. 35. When Al4 =O, the address ranges fe 8000H to BFFFH. Fora 32K memory chip, itis accessed either by YI or Y2; therefore, the address ranges from 40008 to BEFFH. ‘The opcode fetch cycle begins immediately after MEMW signal Ist MEMR —> opcode fetch of the JMP insisuction, ‘ih MEM ——> opcode fh of the STA instruction. ‘The last MEME ie the third byte of the STA instruction. It veads FFH. CHAPTER 4 ‘The number of omput ports in the pripheral /O is restricted o 256 ports because the operand of the OUT instruction is § bit; itean have enly 256 combinations. Yes, ‘The 8085 differentiate between the ipput end the output ports of the same address by the ‘control signal. The input port requires the RD and she ouput ports requires the WR control signals “WR (low) and 10M (high) Pulse going from high to low. ‘Taaling edge.10. 12, 14 15. 16. vy. 1. 20. a 22, Each LED roquires 1010 19 mA current for proper illumination. The latch cannot supply the ‘necessary current when the output is logic high, bur it ean sink the necessary current when the logic level is low. RD (low) and JOM (high). ‘A latch is necessary to hold the ousput dats for display however, the input data byte is Chiained by enabling a tr-state buffer and placed in the accuraulator. RD, WR, and 10M (low). No \No. An output byte wil he displayed temporarily until dhe WR signal is active, and then, it will disappear ‘Memory-mapped VO. LE is enabled when 1O/M is low. ‘80000. “Assuming A3 ~ 0, port address = FUH. 1€A7 = 0, port address = 75H, and IAT = 1, address = FST, IIO/Mis connected to /E1 (sctive ow), it will bea memory-mapped VO. The port address oorsHL [Replace OUT FSH hy STA OOFSH MYIA, COH ;Code for'o" OUT FE BLT tn O19, replace the code COH by the cole for letter T (Code for = 89H 1F-A7 is replaced by 1O/M signa}, the circuit will have three don't care adress lines: A7, Ad fand AS resulting in eight different addresses, IEA7 =O, the addresses are: 04H, OCH, 14H and 17 IA? = 1, the addresses are: 84H, SCH, 93H, and 9CH (as shown in Section 4.34), “The port will be a memory-mapped UO with an address = 0OFBH.22. 29, Port A = Memory-mapped Output Port ort B = Memory-mapped Input Port Both are memory-mapped VO ports. Assuming the addres lines A15-A8 are atlogic 0, Por, Aan Port B will be 0085 In Figure 4.10, theeutput OS is enabled by the address which is active for three states. On the other hand, the 1OW signal requires WR signal which is active forapproninately one and half Tostates, a Machine Cycles: MI M2_M3 INSAH OF MR IoRD IMP START OF MR MR b.20T X05 = 10 micro-ee, ©. Six times, 4.10 micro-see (from beginning to th next beginning) ‘©. Thereisno WR pulse in theroutine. JOM high orIORD can be used to aye the scope, & Machine Cycles: M1 M2 M3. Ma LDA FFFOH OF MR MR MR STA FFFSH OF MR MR MW MOV B.A oF IMP START OF MR MR bo FFFOH RD =11 times and WR = I time, 4. 401 X 0.5 mioro-tee = 20 micro-see. In Figure 4.18, the address line Ad is dont care. ‘Assuming AS ~ 0: Input Port = 2FH and Output Port = SEH ‘Assuming A@~ 1: Input Port ~ 3FH and Ourput Pert = 9FH. START; IN 2FH Read input port ANI 00000011 Masi all bits exeept D1 and DO JNZ START i's switch is open, read ain MVE A.00 {This striction te unnecessary {Used here forelanty30. 2 our sFH BLT START: IN o2FH OR 111111008 MOV B.A cr orFH JZ START Mov A.B our sc HLT START) IN 2FH ANI 000000118 iz staRT cua OUT SFE BLT Tum on all LEDs ‘Read input port |Setall bits rom D2 to D7 Save reading in B ‘Check whether both switches are open Lchoth ewitches are open, read again sGet initial reading sTum on corresponding LED Read input port {Mack all bits except DO and D1 {If both switches ate open, read azain [Make all voadings 1 except which is open ‘Tum on corresponding LED ‘The address of the atch enabled by Y3 = FSH and the address ofthe laich enabled by Yoo rat MYIA, 98H Common anode code for"? Our Fst ‘MVIA, FSH ;Common anode code for?" our ran BLTPART Il: SOLUTIONS CHAPTERS 1. The four categories of instructions that manipulate data are: data transfer (copy), arithmetic, logic, and branch. ‘Tae tsk to be performed is called the opcode (operation cod), and the data to be operated fon is called the operand Which may be specified ar data, register of addrest. Opcode: MOV and Operands FLL 3. ‘Themachine code: 01 100 111 = 6781 4. (@)2647H OPCODE ~MVI_ OPERANDS = 8, 4711 (©) COFSH OPCODE = ADI_ OPERANDS ~ A GMPLIED), FSH (©) 91H OPCODE = SUB OPERANDS = A (IMPLIED), C 5. (@) HEX ~325020H1 OPCODE=STA OPERANDS = 20501 () HEX =C270208 OPCODE=INZ OPERANDS = 2070H, 6. The SUB A instruction clears the accumulator. Z=1, CY =0 7. INSTRUCTION ADDRESS HEX MVI BAFH 2000 o64r MVI C78 2002 O78 MOV A.C 2004 79 ADD B 2005 50 ‘our o7a 2006 D307 HLT 2008 76 & INSTRUCTION ADDRESS HEX MVI ASEH 2020 38F MVI B.s8H 2022 0608 SUB B 3024 90 ANI OFH 302s Rear STA 207015 2027 327020 BLT 2A T6 9, INSTRUCTION ADDRESS HEXn 12, START: IN. FaH 2000 DRE? CMA, 2002 2F ORAA 2003 BT 32 START 2004 CAo020 Logical steps to add two Hex numbers: Load A2H! in one register. [Load 18H in second register. Copy A2H in the accumulator ‘Add the contents of the second register to the contents of End of the program. MVIB, AH MVIC, 188 MOV A.B ADDC HLT Register contents: Initial: B=28H, A~OTHL ‘After the execution : A~28H, B-28H, C=28H InQ. 6, ifthe code O7H (port address) is omitted, the processor assumes the opcode ofthe rent instruction T6H (HILT) as the address of the outpst por, ouput the contents of the Sccumulator to the address 76H, and continues to the next code. After the ext code, results Er indeterminate 4s Q. &, if the byte OFH is omitted, the processor asoumes the opcode 32H of the next inswuction (STA) as the socond byte of the ANI instruction. The processor isa soquettal ‘machine, it assumes the aext code 20H (the low-order address of 2070H) os the opcode of ‘the next insuction and continues. CHAPTER 6 ‘Section 6.1: Data Transfer (Copy) Operations 1 ApecDs z cy MvIA.00 00 NA NA NA MVIBFS 00 FS MOVGA 00 FS 00 the accumulator.MOV DB 00 FB 00 FE HLT MYIC, 5514 MVLA, 9211 OUT PORT! ;Display 92H MOV'A,C. QUT PORTO :Display 65H HLT 4 INO OUT OOH Display data trom input port O7EL IN ost MOV B, A ;Store data ftom port 081i HLT ssn 6 som 7. Both wit be 80H ‘Section. 6.2: Arithmetic Operations 8 ABS zc oo FF Oo 1 oO MVIAF2H F2 FF NA NA NA MVIB.7AH FZ 7A NA NA NA ADDB 6C 7A.0. 0 1 OUT PORTO 6C 7A NA NA NA BUT 9. The instruction ADD A will add the content ofthe sccumslator to Steet this is equivalent to multiplying by 2 30. Theinstruction SUB A will clear the accumulator. The flag. status will be: CY -0,2~1. n. Ac szce xx xx 000 0 MVIASEH SE XX NANA NA ADIAZH 00 XX OL13, 14 16 18, MOVC.A 00 09 NANANA HLT MYT A.3AH. ADI Asi ‘OUT PORTE HLT MYIA, 00H (A)=00000000 per «’ ee ooooan01 OUT PoRT# BLT x iii 1~FFH ‘The instruction DCR does not set the CY flag A=95H S=1 CY=0 ‘The flag has no significance when subtracting unsigned numbers. Ifthe the CY fag is ei, it indicates a negative result, AB Ss zc SUBA 00 MOVBA 00 00 DCRB 00 FF INRB 00 00 SUIOIH FF 00 wonge enoze -% Eg SUB A Clear acumutator our PORTO Display reeult(47H-926) Borrow flag (CY) is set ‘tw indicate negative results. 1 0001 1001 =19H Borrow flag is deleted by the CY of the esult (PORTO) = BSH and (PORTI)= 19H19. If anumber is added before clearing the accumulator, the result will include the residual ‘contents of the accumulator. ‘Section 63: Logic Operations 20, The instruction XRA A clears the accumulator, and the Mag status is: CY ~ 0, 2 = 21, The instruction ADD B sets the CY Mag, bet the instruction ORA A resets the CY fag, A=00 S=0 Z=1 cY=0 23, Theinstruction ORA A will set the flag without affecting the content of the accumulator. 24 ABS zo XRAA 00010 MVIB4AH 00 4A NA NA NA SulaeH BL aA TOD ANAB 00 4A 0 1 oT aur 26. MVIC, ABET MOV A.C, ‘ANIOFH :Masking byte to mask D7-D4 Sut pore HLT 27. MVID, SEH ANLOFH ;Mask D7-D4 MOV D, 4" :Save in MVIE, F7HL ANI OFE | ;Mask D7-Dd of second byte XRAD "Exclusive OR masked bytes ‘OUT PORTO BLT 28, MVIB, 91H MVIC, 878 MOV A.B ANIOUT —:Masi all bits of 01H exeept DO MOVB,A Save DO from frst byie MOV A.C ANLOLH ‘Masi all bits of 87H exeept DO ANAB) AND bits DO of STH and 87HOUT PORT! ;Tumn on/off light connected to DO aN o7 cma ‘Complement data from port O7H ORAA Set flag iPall switches are open 1 Continue i 1 ‘Section 6.4: Branch Operations 30. 3 2 33, 34, 35, 36, ast In the following program, explain the range of bytes that will be displayed at PORT? for various values of BYTEL MMVI A. BYTEI MOVE, A Sut sori JC DELETE, Mov A,B SUI SoH JCDSPLAY DELETE: XRAA Our Portt DSPLAY: MOV A.B out PoRT2 HLT Jn this problem, all bytes from 5GH to 7FH will be displayed st POPRT2. “The address of the output port ~ F2H, AMI positive signed umbers and zero will be Siaplayed st port FE. ry ‘This routine displays the absolute value (magnitude) of BYTE son 267», 38, START: MvI D9BE MV E-A7HL Mov AD ADD Jc_pspay ‘our oor BLT DSPLAY: MVI A.O1H Our oon BLT XRAA Clear CY MVIB, FF INRB MOV A,B INC DSPLAY MVIA, 01H DSPLAY: OUTPORT# —_ ;The output = 00H because INR docs not ‘ELT {sot CY fing ‘To clear the CY flag, the instructions such as ANA A, SUB A, ORA A can be used instead ofthe instruction XRA A. ORAA Clear CY MVIC, FH MOV A.C ‘ADI On INC DSPLAY Mvra, orn, DSPLAY: OUTPORT# The output = O11 because ADI sets CY HLT Hing, MYIB. BYTE! MVIC, BYTE? MOVAB SUBC. JNCDSPLAY Jump if result is postive cua lake one’s complement ADIOLH Find two's complement DSPLAY: OUT PORT! HLT‘Section 6.6: Debugging « Program AL, Reference: Section 6.53 2000 ORG 200011 2000 BFL START: INOFIH 2002.47 MOV B.A 2003 DBE2 INOF2H 2005 Esso ANI OH 2007 a MOV C,A 2008 78 MOV A.B 2009 E680 ANTSOH 2008 Ai ANAC 200¢ €21720 Nz SHTDWN 200F 7 Mov A,B 2010 Bair ANTIFE 2012 DIES Our Fs, 2014 €30020 IMP START 20173840 SHTDWN: MVIA, 40H. 2019 DaF3 OUT ofa 201B 76 HLT 201¢ END 42, Inthe following program, the instructions IN FI and IN F2 are replaced by loading two data ‘bytes 97H and 85H in registers D and E respectively 2000 ‘ORG 20008 2000 1697 START: MVID,BYTE! ;Simulate data from port Fi 2002 1885 MVI EBYTE? ‘Simulate data from port P2 2004 78. MOV AE 2005 E680 ANTSOH Mask 3650" 2007 SF MOVEA ";Save S7 2008 70, MOV A.D 2009 E680 ANT BOE ‘Mask $6-S0 2008 A3 ANAE, [Check S757" 200c C21720 INZSHTDWN —_HIES7.& S7-aro.on, jump to Intiate shut down procedure 200F 7A Mov AD net, get data from port FI 2010 oir ANLIFH ‘Mask bite D7-DS. 2012 DFS ‘Our PORT ‘Turn conveyer belts 2o14 c30020 IMP START 2017 3540. SHTDWN: | MV1AAOH {Secbit Dé=1 Bois bars OUT PORT ‘Tues on emergency doin 76 ELT 0097 = BYTEL EQUOTH 28oss = pyTE2 ors = PORT aoe. QU SSH OU OFSH END 43, "This program turms on the LED indicator when the switch S7 ison. 2000 2000 DBF START: 2002.47 2005 E680 2008 78 2009 E680 2008 CA1420 2008 D3F3 2010.1 2011 €21¢20 201478 TURNON: 2015 Bor 2017 DFS. 2019. C30020 201C3B40 SHETDWN: 2018 D3F3 2020 76 (CHAPTER? ORG 200081 INGFIH — ;Comments are same as illustrative MOVB.A program ~ omitted here Nora ANI SOE MOVGA Saves MOV AB ‘Getdata Gom port Fl ANT 80F 3Z TURNON If $7 =0, turn on belts OUT OF3H Tum oa LED to incicate $7 is on ANAC Check S7and 7" INZ SHTDWN, MOV AS AND 1FHL Our ors IMP START MVIAOH jLoad byte to tur off belts end turn oa emergency OUT OFS HLT END “The following programs assume the systems R/W memory begins at location 2000H. The symbols 26 in the aesignmente are assumes as memory page 20H Section 2.1 See Figures 71,72, 7.3, & 7. Section 2.2 pg. 81 5, Location 2075H will contain F7H.10. 12 13. 14, 16. MVE CFF LEXI #.2070% LXI_D2070H MOV MC LDAx D FF A=FFH (20708) = FFE 207SH and 2076H A=00H D=00H HL=209FH Clea loestions 2090H 9 2097 Lx1 820908 SUB A MVI_DOFH Loop: STAXB INX B DeR'D TNZ. LOOP HLT cp ewEL FE rE 20 70 FF 20 70 20 70 FF 20 70 20 70 FE 20 70 20 70 rE 40 Infinite loop. DCX instruction docs not affect Z flag. 7 eisnes, DCX instruction docs not affect Z flag. START: LXTH, 2055Hr XID, 208541 MVIB, Oct NEXT: MOVAM STAXD INKL Dex DCRB INZ NEXT HLT START: LXIH, 205FH index for data source lindex for data destination, starting st last location Byte counter (Got data byte Store data byte inex location. [Ufeounter is not 0, go back to transfer next byte sIndex pointing to last source byte findex for destination18, w, START: START: Loo: SKIP: START: MVIB, 10H MOV A, M STAXD DCXH DCRB INZ NEXT HLT xr, 20608, LXID, 20807 MV15, ost MOV A.M STAXD INX HL INXH DCRB NZ NEXT HLT MVI BS XI #20508 xt D’20500 MOV AM ORA A INZ SKIP STAXD INX D IN Der B INZ LOOP HLT LXID, 20608 vi G. os MVIB, oF LDAX'D ADDB MOV B, A INXD. DCR C JNZ. NEXT our PoRT BLT Byte counter iGetdata byte {Store data byce Next location sNewt count Jadex pointing to low-order reading ndex for storing low-order reading sCounter for emp. readings iGet resding {Store low-order reading sPoint to next low-order reading aNext count sBYTE COUNT :SOURCE sDESTINATION IGET BYTE STEST IT FOR ZERO :NOT ZERO, SO STORE IT :GOON TONEXT. fndex for date !Counter for data {Clear B to store partial sum sAdd data byte fave partial sum, Next count Display sumFor the given five bytes, the sum is B7H 20. START: LXTH, 2060 dlndex for data Mvi cost Counter for data Mv B, oon {Clear B to store partial sum NEXT: MOV A,M ADDB 5c CARRY Atsura > FF, digplay OL MOVs, A’ Save paral sum DCR iNew count SNZ NEXT Our PorTt sDieplay sim SLT CARRY: MVLA, or Our PoRTr aLT First set display = OH. ‘Second set dssplay = AFH. 21, Clear register D to cout the umber of bytes added and insert the instruction INR. after the instruction JC CARRY. Display the contents of register D at PORT? at the end, First set display = 3 and Second set display~ 5 Section 2.2: 22, Locations 2070H to 2074H will contain O1H, 02H, 03H, 04H, AND 05H 23 A HL SZ CY M20ssH Lx 2055 2055 NA NA NA MVI-MSAH 20 55 | | | BA MVI Aer mw 20 35 | | | 8A ADD M 00 20 55 0 1 1 BA STA 20551 00 20 55 NANA NA 00 HLT 25, $=0 Z=1 CY isnotaftected (NA), 26. START: LXID, 20501 {Set up index pointer EXT, 20408 Point to counter location in memory MVIM, 06H "Load counter with the count XRA A {Clear aceurnulator MOVC.A {Clear C to save partial sum 2228. 29. MOV B.A NEXT: LDAXD ADD INC skp INRE SmI: INXD NX DCRM INZNEXT. our port MOV A,B Our PoRT2 HLT START: LXID, 20508 (Da, 20608 MVIC, 05 NEXT: LDAXD MOV 3B, M SUBB JC SHTDWN IND INK, DER JNZ NEXT Mvr A, ont ‘OUT PORT] HLT SHTDWN: MVI A, OFFH ‘OUT PORT! ELT sClear B to save carrys sGer daze :Add previous partial sum Aine carry, do uot increment CY register nerement carry register $Point to next byte sNewt count Af all numbers are not yet added, get the next byte Display sum Display CY register Set pointer for readings of furnace 1 {Set poimter for readings of furnace 2 et Up couster fo count five readings {Place temp. reading from furnace Lin A {Place temp. reading from furnace 2 in B AE (B)> (A), jump to display emergency Point to next memory locaton Decrement reading count {Get next temp. reading Set bit DO~ 1 #Tam on bit DO ‘oad emergency indicator Display FF for emergency |Add, after the statement JC SHTDWN: INZ NOTEQ MMVI A.soH OUT PORTI NOTE: continue START: Ext 1.20701 MVI Ba Loop: = MOV AM INx ‘ADD M Dex 1 {Uf they are not same, skip Uf they are, load byte to tar on D7 Tum on bitD7, SDATA LOCATION (NUMBER OF PAIRS: SGET FIRST BYTE OF PAIR, POINT TO SECOND BYTE [ADD 2ND TO 1ST [POINT TO LOCATION TO STORE SUM SNOTE: DCX AND INX DO NOT AFFECT CARRY 3a START: oor: START: Loop: ‘Section 7.4: 52. @A=6rH, cY= 33. MOV M.A INX MVL AO ADC AA MoV M.A INX DcR B JNZ LOOP. HLT x1 H,20708 XI D2070H MVE Bs MOV AM INX SUB M STAXD INX DCR 'B INZ Loop oa 4.20708 Da D070 MVI Ba MOV AM INX SUB M ac Skip sraxD INx D INX H DCR B INZ LOOP: aur MVI ASO 80. Ona 8 RAR 80. ;STORE suM POINT TO CARRY POSITION SGET CARRY INTO A. )STORE IT TO 2ND LOCATION POINT TO NEXT PAIR INEXT COUNT, HF COUNT IS NOT ZERO, GET NEXT PAIR Data location. {Storage location number of paice [Get fret byte of pair Point wo second bye ‘Subtract 2nd from 1st {Store sum jBump sum pointer Point o next pair Decrement court Ge bask for next operation Data location {Storage location iNumber of paice \Get fst byte of pair Point to second byte {Subtract 2nd from Ist Shap if =O (negative) unsigned () A= 6EH,CY=1 s Zz oe 1 0 0 o 1 4 3435 37. 29. @ A cy @ MVI AcsH Cs Ona ‘A. cs 0 RAL sat RRC 4s 0 A cy MVIAATH AT Ora & a7 0 RAR aE 1 RAL aro ‘These instructions will move the MSD of a BCD number (7s this cass) ftom 10th to the 1's place. A=O7 (@) Muniply by? (@) Divide By 4 Mutuply by 20. START: MYID, OAH 13H, 20608 MVIC, cor MOV B,C Loop; MOV ALM ORaa JM NEXT ‘ADD C Mov ca INC NEXT INRB. NEXT: INXHL Der D INZ LOOP, MOV A.C ourrorrt MOV A.B ‘our PoRT2 HLT et up counter to count ten readings {Set pointer to data location Clear register C to save partial sam iClear register B for cary sGet current reading Set lage HED? = 1, reject the data byte {Ada the current reading: ‘Save partial sum of the readings "If no carry, do not increment (3) JAdd 1 to previous carry count $Go to next data location Next count 1Go back to gat next reading Get the final sum Display low-order byte ofthe sum iGet the earry count Display earry count For the given set of readings in assignment 38, the sum ~ 2AQH START: MVID, DAH LXLH, 20608, MVIC, OOF MOV B,C MOV E,C. Toor: = MOV ALM ORAA IMNEXT INRE ADDC {Set up counter to coumt ten readings {Set pointer to data location ‘Clear register C to save partial sum ‘Clear register B for earry ‘Clear regi. FE to count positive readings iGet curent reading Set fags HED? = 1, reject the data byte ‘Positive reading found; count it Add the curtent reading40, Moy c, A, INC NEXT INRB NEXT) INKL DCR D INZ LOOP MoV A.C OUT PORT! MOV A,B. OUT PORT2 MOV AE. OUT PORTS BLT START: LXE, 20008 LEXI, 20501, MVIC, os Loop: MOV A.M ORA A JM NEXT RRC JC NEXT Ric STAXD INXD NEXT: INXHL DER INz LOOP HLT ‘Save partial sum of the readings /U'no earry, do not increment (B) TAde | to previous cary count ‘Go to next dats location Next count $Go back to got next reading, $Get the final sum Display low-order byte of the sum SGet the carry count Display earry count iGet number for positive readings "Display number for positive reading {Set pointer to data storage location {Set painter to data location {Set counter to count eight bytes iGet the byte Set flag if D7 =1 umnp to increment data peinter Place DO in C¥ position Slump to increment data pointer Restore original byte {Save the byte at storage location Next storage location Next data location Next count ump back to get next byte Answer, The following memory locations should have the data bytes as shown, 2060 = 5241 2061 ~ 78H 2062 = 62H Section 7.8: at, szcy MYI ATFH Ona x rr aa aa > “oe 3643. as Asza LEXI H.20708 MMVI M644 MVIASFH 8F CMP MBF 6 0 oO (00, 00, 7A, 87, 00, 00 100 (641) < BYTE < 200 (C8H) 20, 64, 8F IEPORTI <32 (20M, CY flag is se. (or if PORT] ~> 160 (AGH), Minus fing ie set START: LXIH, 205011 Set index to point to data MVIC, oor ear register C to save sum MOV B,C Clear (B) to save carry MOV D.C {Sct register D to compare bytes NXTBYT: MOV A.M iGer data CMPD ‘Cheek whether this the last byte Az DsPLay FIE'Yes, go to display section ‘ADD C FAdd previous eum INC SAVE Hf there is no carry, go 10 save the sum, INRB {Update carry register SAVE: MOV.CA Save sum INK Point to next reading IMP NXTBYT Go back 10 get nen! reading DSPLAY: MOV A.C Our PORT! Display low-order byte of the sum MOV A.B sCopy the carry count to accumulator our PORT2 Display high-order byte of sur HLT START: LXIH, 20508 {Set index to point to data location MVID, 40% Byte w be found in data string Mv1; ost [Sec up counter NXTBYT: MOVA.M. iGet data byte CMPD {the byte ~ 40H? JZ DSPLAY ; —_If'yes, go to display its location INKH Point to next data byte DCR C iNext count INZNXTBYT Jump to get next byte a749, 50. s DSPLAY: START: NXTBYT: NEXT: START: START: Loop: MVIA, FFH OUT PORT HLT MOV AH our PORT MOV'A.L Our PoRT2 HLT LX1H, 20508 MIC, 08H MVIB, on MoV A.M. cur 6 INC NEXT MOVE, A. INxH DER JNZ NXTBYT MOV A.B our ort HLT LxIH, 20504 MVIC, ostt ‘MVIB, 0O# MOV AM cup & JC NEXT MOV B, A INXEL DER JNZ NXIBYT MOV A.B our oar LX1 8.205081 131 20508 MVE B10 MOV AM CPI 60. JC REJECT cer 101 JNC REJECT {The byte 40H is not im the set sLoad high-order memory address Display memory page number Load low-order memory address Display memory low-order adkiness $Set index to point to data location Set up counter ‘Clear (B) to save the highest reading $Getdata byte Bs B)> (A)? $f yes, replace (B) with (A) Save the larger number Point to next data bye INext count Hump to get next byte ‘Load the largest byte «Display the largest byte in the string Clear (B) to save the highest reading iGetdata byte sy <1)? {Af yes, replace (B) with (A) ‘Save the larger number ‘Poin to next data byte [Next coune Slump to get next byte Load the largest byte Display the largest byte in the string :SOURCE POINTER [SAVE POINTER, iBYTE COUNT. REJECTIF < 60 NOTE: IF SUBTRACT 100, WOULD REJECT 100 :RETECT IF > 10052 sa REJECT. START: Loop: REJECT. START: LooP REJECT: ENDS: START: Loop: STAxD Ixx D INX DeR'B JNZ LOOP EXT #20508 LXE D200 v1 8,10 Mv Co Mov AM CPI 66 JC REJECT cP or INC REIECT STAXD INX D INR C INX AL DCR B INZ LOOP Mov Ac our Port BLT xd 1.2070 EXa_D2090H MOV AM CPI opi JZ ENDS Cex sunt JC REFECT ‘Cer sant INC REIECT STAXD IXx D INX IMP LOOP, HLT LXI H,2070H LX D/2090H MVI Co MOV AM :0K, SO SAVEIT SLOOP FOR NEXT SOURCE POINTER (SAVE POINTER SBYTE COUNT SREIECT IF <60. SNOTE: IF SUBTRACT 100, WOULD REJECT 100 IREJECT IF = 100 10K, SO SAVE IT. :AND COUNT IT :LOOP FOR NEXT sDISPLAY COUNT sCHECK FOR END OF STRING HIF “OH, THEN END OF SRTING {REIECT IF < 30% :NOTE: IF SUBTRACT 39H, WOULD REIECT 39H IREJECT IF > 398 10K, SO SAVE IT sLOOP FOR NEXT :SOURCE POINTER [SAVE POINTER,REJECT: ENDS 55, START. Loor: SK. ENDS cpr opi JZ ENDS cPr 308 JC REJECT cpr 3A INC REJECT STAXD INX D INR C INK Ht IMP Loor: MOV AC. OUT PORTI HUT xr Bpocod mvt Co MOV A.M ona A az ENDS cer asH INZ ING INX SMP LOOP HLT .CHECK FOR END OF STRING HF =0DE, THEN END OF SRTING JRETECT IF < 30H |NOTE: IF SUBTRACT 39H, WOULD REJECT 3911 IREIECT IF > 398, JOK, SO SAVE IT ,AND COUNT IT sLOOP FOR NEXT sDISPLAY COUNT :SOURCE POINTER FOR SCANNER READINGS :COUNTER TO COUNT SETS |GET SCANNER READING ISET ZERO FLAG. HE BYTE =0, THEN END OF STRING HS IT A 19" SET SKIPuF NO, DO NOT COUNT TP ‘C\COUNT THE SET 56, Thisassignment is similar to the Mlustrative Program 7.53 except thatthe orders descending land the number of bytes = 10. ‘Thersfore, the counter register C should be set for 9 and the instruction JC NXTBYT ehould be replaced by INC NNTBYT. (©) 1)A was not initialized to 00 2) Missing INX Hin loop, ‘Section 2.6: 57 (@) 256) 20901-2001 58 seri SET2 @ Em oan (© DCR B hould be DCR C and add the instruction MOV A.B Just before (STA. 2070H) storing the answer59, SETI ser? (a) o16rrr (a) 039cH, (@) Change INZ 2008H to TN 2007 (@) ADC M should be ADD M CHAPTERS 10. 1168 usec 234.67 msec 468.584575 mSee (Count I2FFH = 1X16 + 2x16 + 15X16 = 15x16 = 863 ‘The delay in the loop: = Testes X Clock Period X Count = 64x (33x10) x 4803 ‘The sbove calculations are based on the assumption that the IMP insinietion takes 10 ‘Tostates in the last iteration, and the intial instruction LXI B is not part of the delay loop. To account for the 7 T-states in the last Weration, the delay of 0.99 misro-see (9x10 3-99 X10) should be subtracted ftom the above delay. 234.1313 mSee @4 (©) infinite (©) infinite oF just once ifthe flag is set initially. (@) infinite @) snanite (@) 1 1.405 mSee {ethe system frequency is 3.072 MHz, the clock period will be 325 ns, This will reduce the delay to 325 counT~0EH1, B= 34965, Insignificant difference when the delay is caleulated with JNZ ~7 ‘T-states in the last iteration. 12, 12799 GIFFED Note: In the following assignments, the delay calculations are based on the SDK-85 system with the frequency of 2.072 Miz (T= 225.5 ns). Mnemonics Comments ‘Testates 13, START: MVIB, oH Initialize counter DSPLAY: OUT PORTI Display count 10 LXID, COUNT Load delay count 10 Loop: = pexp 6 MOV A,E 4 ORAD sSetZ Mlag if D) & E)-0 4 JNZ LOOP "EZ = 1, repeat the loop 107 INRB sNext count 4 MOV A,B, 4 cpr2i count= 21817 3 INZDSPLAY “if net, go w display count 107 IMP START SReeet counter, tart again Caleutations for 100 me delay: Delay outside the loop: 14688 ns ‘Delay within the loop: “T= 2a T-otates x 325.5 ne x COUNT ‘Total Delay T = To+T 100 me 4648 ne + (26 x 325.5 n8 x COUNT) 100x 10- 14648 x 10 counr =———— =12,798 =31FEH 781210START: DSPLY1 Loops Loop2 DsPLY2, Loops Loops: MVEB, oO7 OUT PORTI MVIC. COUNT: XID, COUNT2 DexD MOV AE ORAB INzZ LOOP? perc NZ LOOP1 INRE. MOV A,B cProar INZ DSPLY1 Der B ut Port MVIC, CouNTI LXID, COUNT: DEXD MOV A, E. ORAD INZLOOPS bere INZ.LOOP3 MOV A,B ORAA INZ DSPLY2 IMP START start Up-Counter :COUNTI = 10 :COUNT? should provide 100 me delay Check whether 9 is displayed :COUNT: = 10 :COUNT? should provide 100 me delay Set Z flag if (a) = 0 For delay calculations, see Assignment #7. START: ROTATE, Loop: LOOP2: MVID, oor Mov A.D CMa MOV DA, ANI 808 Our Port: MVIE, COUNT! LXIB, COUNT2 DCXB MOV A.C ORAS INZL00P2 DCRE SNZLOOPL IMP ROTATE sLoad bit pattern ‘Tstates sComplement bit pattern 4 4 ‘Maske D6-DO 7 107 ‘To design S-second delay using the loop within the loop technique, it is assumed that che LOOP? will provide 100 ms delay, and It will be repeated 50 times by using the COUNT! = 32FT in the outer loop, LOOFI Delay: =24T x (225.5 ns) x50 =039me Delay Outside the loop: = 397 x (325.5.n8) = 0.0127 ms ‘Total Delay ~ LOOP! ~ LOOP2 x 50-+ Outside Delay 5 6.39 ms~ (24 x 325.5 ne x COUNT2) 50 +.0128 ms COUNT2 = 12799,78 ‘The COUNT2 can be calculated by ignoring all the delays except in the LOOP? as follows: 3s=LooP2 x50 = (24 325.5 ne x COUNT2) x 50 COUNT2 = 12800 “The difference between the two calculations is 0.22; itis insignificant. START: MVID, 008 Load bit pattem, ROTATE: MOV A.D 4 MA {Complement bit pattem * MOV D.A a ANIOL :Mask D7-D1 7 Our porT: 10 MVIB, COUNT 7 Loop: BCRB 4 JNZ LOOP, 107 JMP ROTATE 10 ‘Total Delay T =To+T 200 5 = 46x 325.5 ne + 14 x 325.5 nex COUNT COUNT =42.5 = 42 TURNON: MVIA, O11 Bit pater to tum on DO 7 OUT PoRTI 10MYTB, COUNTI :Count for 200 s pulse 7 LOOP: CRB 4 INZLOOP1 107 MVEA. OOH :Bit patie to tam off D0 7 OUT PORT! “:OfFperiod begins to MYIB, COUNT? ;Count for 400s delay 7 LooP2; DCRR 4 JNZ LOOP? tor IMP TURNON, 10 On-period Delay: 7 =To+T 200 = (24 Tx325.5 ms) + (14 T* 325.5 ns x COUNTH) 200-781) x10 couNT: = = 42 (557 10) Otf-period Delay: T -To+t 400 = (347 x 325.5 ns) + (14x 325.5 ns x COUNT2) (400 - 11.06) count; == 85 (557 x10) START: MYT [101010108 ALTERNATING LIGHT PATTERN LIGHTS: Mov AL RRC OUT PoRT MOV LA vi B50 320 50 mSee DELAY = 1 See OUTER: EX! D2559 320 mSee DELAY INNER! DCX D MOV AD ORA E INZ INNER, DCR B JNZ OUTER IMP LiGHTS