Low-Power VLSI Circuit Design Final Test, Winter 2007 Each question is worth 17 points Bus inversion coding can be used for interconnect data transmission with ong wires. ‘Assume the bus contains n bits and the data transmitted is uniformly distributed, Analysis shows that the power ratio with and without bus conversion can be represented by Equation (1) shown below. It can be observed that as the value of n increases, the power saved is almost 0. How ¢o extend the idea of bus inversion to get a reasonable power saving? You must show your idea by a simple figure plus a stnall paragraph of explanation (DO NOT WRITE THESIS). Equation (1) Multiplying a signal with constant coefficients is a very common operation in DSP. Consider the example in which a multiplication with a constant is decomposed to IN+IN>>7+IN>>8 where a>>b means the value of a shifted right b bits and IN a n-bit number. Assume the shifter is implemented by a combinational circuit, instead of a shift register, o simplify this problem. Assume you are given two adders (each adder is a n-bit adder) and two shifters (one for 7 bits while the other one for 8 bits). Show how to design this low-power multiplication by using these two adders and «wo shifters to implement IN+IN>>7+IN>>8. Just show block diagram design, i, adders and shifters are circuit blocks here, You do not need to design them, This is RT-level low-power design, Given two interconnects as shown in Fig. Fig. H(a) and Fig. (b). The capacitance and resistance of a fat segment of size LxW is 20 fF and 50 Ohm, respectively. The load capacitances are shown in the figures. (A) Use the Elmore delay model to calculate the delay for each interconnect. To simplify your analysis, we assume the driver gave does not contribute any parasitic capacitance and resistance. Also, try to use T-model to represent cach interconnect segment. (B) Calculate the dynamic energy consumption for each transition. (C) Use this example to verify the monotone property of the interconnect sizing.ee eel L —s 4h w kw fon i 2 y w FE lof F 1g lof oo” Fig. 1. oo) 4, Assume inverter G drives n other gates as shown in Fig. 2, The best sizing W of G can be represented by Equation (2) as shown below. Equation (3) is used to derive Equation (2). (A) If the channel width of alt gates driven by G is doubled, which parameter in Equation (2) will be changed? (B) If the mobility of N-type transistor is doubled, and the input of G is a falling transition, how will the optimized size W be changed? (C) If the switching frequencies of all gates are doubled, how will the optimal size W be changed? Fig. 2 Ne EG (Berg) We G a Ln )f Equation (2). Pi + (RUC P= Pi Pei)of wall Soop (by 5S +fetn) Equation (3).Fig, 3(a) shows a memory array with size 100 rows and 100 columns. Assume the power consumed to activate each word line is P(wl), while the power consumed to activate each pair of bit lines is P(bl). Assume a low-swing bit line technique is used, so we have P(wl)=100P(b1). Now, assume the entire array has been partitioned into four banks as shown in Fig. 3(b). Also, the data has been arranged in such a way that the probability of accessing each part of every bank is prob(1) to prob(4) as shown in Fig, 3(b). Assume we have prob(1)=1/2, prob(2)=1/4, prob(3)=1/8, and prob(4)=1/8, Assume the banking will not introduce any power overhead (ie., the extra decoder and all required extra interconnects consume little power and can be ignored). How [RG percentage of power can be saved due to this banking, Use equal banking) — P(with banking)] / P(without banking). POL PbO 2 HP Prch(= dp preg Sense Pret Ooptutfig. > vee “Ver z alae) Fe VIF voVY iy Cb) Fig. 4 gives the circuit of a low-leakage memory cell using data retention gated-ground cache design. (A) Based on the given memory cell state, when the cell is driven into sleep mode, which transistors will have stacking effect? (B) Add extra circuit to guarantee that stack effect can be applied to all paths from Vdd to Vgnd for each cell. Rols-deioa~ Uda_ hh i = {SE {—————}} 4 IN >>?w se we 5 oe Wi 7h Terr Thee tor as (5°) + 25 (de) + 5? (a0) + S$ () a5 = 1250 4750 4 Joo + Seo =}fw (38 lo . Ste ays ee ese oO 2@) Sie rp ws w ~ ao Te [Raper 7 ose y0($°) + 50( 4°) + AE (3) + ar(le) = afoot Qos +7 fatv = Shoo HY Ss ph & ~ Foe 7) oe : ° < : 2 <2 CiVaa = 50 Va ) dele (ata & < al Sf el He deste of E, ho Stable, tfo~ How wrath CE) Wide @).® i) Oe eee Led , a v) Wr» J2W ¢) the Same 6) Rone bank ferry den = plob) + foo PUL)= Xt x= 2K Bampect \ ee Plt) —s & pwr) fe mT) Ket onpinal bit por cpt HY 3 Lm powttoP bit Qo med W TT 2 el 2X ay + + E94 bey Hy = F4t+teteiraks tS = Es ty oe "# t= at @Berg tert ponte: “98 ve e, 42 PR Saal U b wh #3 2X- Hx bf 1 = 1p 2X fs ort ya Dh 173 = g 3 - “GP *QD ~ oR wre 06 - Me i « yi 2k ee Beg ot ey t i Xe ee) 4 buch Ce and My M4 &) Get @