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HomeELECTRONICSVLSI/VHDL/VerilogHSPICEProjectsDesignandPerformanceEvaluationofALowTransistorTernaryCNTFETSRAMCell2015

DESIGN AND PERFORMANCE EVALUATION OF A LOW TRANSISTOR TERNARY CNTFET SRAM

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CELL 2015
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HSPICEProjects,MicroWindProjects,TannerEdaProjects February4,2017

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DesignandPerformanceEvaluationofALowTransistorTernaryCNTFETSRAM
Cell2015
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Abstract:
Subject
CarbonNanotubeFieldEffectTransistor(CNTFET)hasprovedtobeapromising
alternativetoconventionalCMOSdesignowingtothebetterelectrostaticcontrol Re: Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM C
and high mobility. The paper presents a novel design of 10 Transistor ternary
Message
memory cell, with separate read and write lines. Extensive HSPICE simulations
have validated the readwrite functionality of the design. Besides a significant
reduction in transistor count, results show at least 45% reduction in delay as
comparedtoprevalentmemorycelldesigns.

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