Lap Trinh C Cho VDK

GVHD: NGUYN VN NGA 20/11/2009
[Year]
MC LC
PHN A: VIT NGN NG KEIL C CHO 89C51
I. MT VI NT CHUNG V 89C51
II. NHNG VN TRNG TM CA 89C51
III. NGN NG KEIL C CHO 89C51
IV. HNG DN S DNG KEIL C LP TRNH CHO 89C51
V. M PHNG MODUL NG DNG V CHNG TRNH MU
PHN B: VIT NGN NG CCSC CHO PIC 16F877A
I. VI NT KHI QUT V PIC 16F877A

II. TRNG TM CA PIC 16F877A
III. NGN NG CCSC CHO PIC 16F877A
IV. HNG DN S DNG PHN MM CCSC
V. CHNG TRNH MU V MODUL M PHNG CHO PIC
16F877A
PHN C: LP TRNH CHO AVR BNG CODE VISION
I. TM HIU V AVR
II. CU TRC LNH CA CODE VISION
III. HNG DN S DUNG LP TRNH AVR BNG CODE VISION
IV. MODUL NG DNG V CHNG TRNH M PHNG
SVTH:NGUYN VN BIN Page 1

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PHN A: VIT NGN NG KEIL C CHO 89C51
I. MT VI NT CHUNG V 89C51
c im v chc nng hot ng ca cc IC h MSC-51 hon ton tng t nh nhau. y

gii thiu IC8951 l mt h IC vi iu khin do hng Intel ca M sn xut. Chng c cc c
im chung nh sau:
Cc c im ca 8951 c tm tt nh sau :
8 KB EPROM bn trong.
128 Byte RAM ni.
4 Port xut /nhp I/O 8 bit.
Giao tip ni tip.
64 KB vng nh m ngoi
64 KB vng nh d liu ngoi.
X l Boolean (hot ng trn bit n).
210 v tr nh c th nh v bit.
4 s cho hot ng nhn hoc chia.

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v S khi ic 89c51

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v S chn ic 89c51

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Chc nng cc chn ca 8951:
8951 c tt c 40 chn c chc nng nh cc ng xut nhp. Trong c 24 chn c

tc dng kp (c ngha 1 chn c 2 chc nng), mi ng c th hot ng nh ng
xut nhp hoc nh ng iu khin hoc l thnh phn ca cc bus d liu v bus a
ch.
Port 0 :
Port 0 l port c 2 chc nng cc chn 32 39 ca 8951. Trong cc thit k c nh

khng dng b nh m rng n c chc nng nh cc ng IO. i vi cc thit k c
ln c b nh m rng, n c kt hp gia bus a ch v bus d liu.
Port 1 :
Port 1 l port IO trn cc chn 1-8. Cc chn c k hiu P1.0, P1.1, P1.2, c th
dng cho giao tip vi cc thit b ngoi nu cn. Port 1 khng c chc nng khc, v
vy chng ch c dng cho giao tip vi cc thit b bn ngoi.
Port 2 :
Port 2 l 1 port c tc dng kp trn cc chn 21 - 28 c dng nh cc ng xut

nhp hoc l byte cao ca bus a ch i vi cc thit b dng b nh m rng.
Port 2 :
Port 3 l port c tc dng kp trn cc chn 10 - 17. Cc chn ca port ny c nhiu

chc
nng, cc cng dng chuyn i c lin h vi cc c tnh c bit ca 8951 nh
bng sau:
Cc ng tn hiu iu khin :
Ng tn hiu PSEN (Program store enable):
- PSEN l tn hiu ng ra chn 29 c tc dng cho php c b nh chng trnh
m rng thng c ni n chn 0E\ (output enable) ca Eprom cho php c cc
byte m lnh.

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- PSEN mc thp trong thi gian Microcontroller 8951 ly lnh. Cc m lnh ca
chng trnh c c t Eprom qua bus d liu v c cht vo thanh ghi lnh bn
trong 8951 gii m lnh. Khi 8951 thi hnh chng trnh trong ROM ni PSEN s
mc logic 1.
Ng tn hiu iu khin ALE (Address Latch Enable ) :
- Khi 8951 truy xut b nh bn ngoi, port 0 c chc nng l bus a ch v bus d liu
do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30 dng lm
tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni chng vi IC
cht.
- Tn hiu ra chn ALE l mt xung trong khong thi gian port 0 ng vai tr l a
ch thp nn cht a ch hon ton t ng.
Cc xung tn hiu ALE c tc bng 1/6 ln tn s dao ng trn chip v c th c
dng lm tn hiu clock cho cc phn khc ca h thng. Chn ALE c dng lm ng
vo xung lp trnh cho Eprom trong 8951.
Ng tn hiu EA\(External Access):
- Tn hiu vo EA\ chn 31 thng c mc ln mc 1 hoc mc 0. Nu mc 1,

8951 thi hnh chng trnh t ROM ni trong khong a ch thp 8 Kbyte. Nu mc
0, 8951 s thi hnh chng trnh t b nh m rng. Chn EA\ c ly lm chn cp
ngun 21V khi lp trnh cho Eprom trong 8951.
Ng tn hiu RST (Reset) :
Ng vo RST chn 9 l ng vo Reset ca 8951. Khi ng vo tn hiu ny a ln cao

t nht l 2 chu k my, cc thanh ghi bn trong c np nhng gi tr thch hp
khi
ng h thng. Khi cp in mch t ng Reset.
Cc ng vo b dao ng X1, X2:
B dao ng c tch hp bn trong 8951, khi s dng 8951 ngi thit k ch cn kt

ni thm thch anh v cc t nh hnh v trong s . Tn s thch anh thng s dng
cho 8951 l 12Mhz
Chn 40 (Vcc) c ni ln ngun 5V.

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II. NHNG VN TRNG TM CA 89C51
1. S vng nh

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2. Thanh ghi quan trong:
Thanh ghi B:
Thanh ghi B a ch F0H c dng cng vi thanh ghi A cho cc php ton nhn
chia. Lnh MUL AB s nhn nhng gi tr khng du 8 bit trong hai thanh ghi A v
B, ri tr v kt qu 16 bit trong A (byte cao) v B(byte thp). Lnh DIV AB ly A
chia B, kt qu nguyn t vo A, s d t vo B.
- Thanh ghi B c th c dng nh mt thanh ghi m trung gian a mc ch. N l
nhng bit nh v thng qua nhng a ch t F0HF7H.
Con tr Ngn xp SP (Stack Pointer) :
- Con tr ngn xp l mt thanh ghi 8 bit a ch 81H. N cha a ch ca byte d
liu hin hnh trn nh ngn xp. Cc lnh trn ngn xp bao gm cc lnh ct d liu
vo ngn xp (PUSH) v ly d liu ra khi Ngn xp (POP). Lnh ct d liu vo ngn
xp s lm tng SP trc khi ghi d liu v lnh ly ra khi ngn xp s lm gim SP.
Ngn xp ca 8031/8051 c gi trong RAM ni v gii hn cc a ch c th truy
xut bng a ch gin tip, chng l 128 byte u ca 8951.
- khi ng SP vi ngn xp bt u ti a ch 60H, cc lnh sau y c dng:
MOV SP , #5F
- Vi lnh trn th ngn xp ca 8951 ch c 32 byte v a ch cao nht ca RAM trn
chip l 7FH. S d gi tr 5FH c np vo SP v SP tng ln 60H trc khi ct byte d
liu.
- Khi Reset 8951, SP s mang gi tr mc nh l 07H v d liu u tin s c ct
vo nh ngn xp c a ch 08H. Nu phn mm ng dng khng khi ng SP
mt gi tr mi th bank thanh ghi1 c th c 2 v 3 s khng dng c v vng
RAM ny c dng lm ngn xp. Ngn xp c truy xut trc tip bng cc
lnh PUSH v POP lu tr tm thi v ly li d liu, hoc truy xut ngm bng
lnh gi chng trnh con ( ACALL, LCALL) v cc lnh tr v (RET, RETI)
lu tr gi tr ca b m chng trnh khi bt u thc hin chng trnh con v ly
li khi kt thc chng trnh con
Con tr d liu DPTR (Data Pointer):
-Con tr d liu (DPTR) c dng truy xut b nh ngoi l mt thanh ghi 16 bit
a ch 82H (DPL: byte thp) v 83H (DPH: byte cao). Ba lnh sau s ghi 55H vo
RAM ngoi a ch 1000H:
MOV A , #55H
MOV DPTR, #1000H
MOV @DPTR, A

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- Lnh u tin dng np 55H vo thanh ghi A. Lnh th hai dng np a ch ca
nh cn lu gi tr 55H vo con tr d liu DPTR. Lnh th ba s di chuyn ni dung
thanh ghi A (l 55H) vo nh RAM bn ngoi c a ch cha trong DPTR (l
1000H).
Cc thanh ghi Port (Port Register):
- Cc Port ca 8951 bao gm Port0 a ch 80H, Port1 a ch 90H, Port2 a ch
A0H, v Port3 a ch B0H. Tt c cc Port ny u c th truy xut tng bit nn rt
thun tin trong kh nng giao tip.
Cc thanh ghi Timer (Timer Register):
- 8951 c cha hai b nh thi/ b m 16 bit c dng cho vic nh thi c m
s kin. Timer0 a ch 8AH (TLO: byte thp ) v 8CH (THO: byte cao). Timer1
a ch 8BH (TL1: byte thp) v 8DH (TH1: byte cao). Vic khi ng timer c SET
bi Timer Mode (TMOD) a ch 89H v thanh ghi iu khin Timer (TCON) a
ch 88H. Ch c TCON c a ch ha tng bit .
Cc thanh ghi Port ni tip (Serial Port Register) :
- 8951 cha mt Port ni tip cho vic trao i thng tin vi cc thit b ni tip nh
my tnh, modem hoc giao tip ni tip vi cc IC khc. Mt thanh ghi m d liu ni
tip (SBUF) a ch 99H s gi c hai d liu truyn v d liu nhp. Khi truyn d
liu ghi ln SBUF, khi nhn d liu th c SBUF. Cc mode vn khc nhau c lp
trnh qua thanh ghi iu khin Port ni tip (SCON) c a ch ha tng bit a ch
98H.
Cc thanh ghi ngt (Interrupt Register):
- 8951 c cu trc 5 ngun ngt, 2 mc u tin. Cc ngt b cm sau khi b reset
h thng v s c cho php bng vic ghi thanh ghi cho php ngt (IE) a ch A8H.
C hai c a ch ha tng bit.
Thanh ghi iu khin ngun PCON (Power Control Register): - Thanh ghi PCON
khng c bit nh v. N a ch 87H cha nhiu bit iu khin. Thanh ghi PCON
c tm tt nh sau:
_ Bit 7 (SMOD) : Bit c tc Baud mode 1, 2, 3 Port ni tip khi set.
_ Bit 6, 5, 4 : Khng c a ch.
_ Bit 3 (GF1) : Bit c a nng 1.
_ Bit 2 (GF0) : Bit c a nng 2 .
_ Bit 1 (PD) : Set khi ng mode Power Down v thot reset.
_ Bit 0 (IDL) : Set khi ng mode Idle v thot khi ngt mch hoc reset.

[Year]
Cc bit iu khin Power Down v Idle c tc dng chnh trong tt c cc IC h
MSC-51 nhng ch c thi hnh trong s bin dch ca CMOS.
Hot ng Reset:
- 8951 c ng vo reset RST tc ng mc cao trong khong thi gian 2 chu k xung
my, sau xung mc thp 8951 bt u lm vic. RST c th kch bng tay
bng mt phm nhn thng h, s mch reset nh sau:
Trng thi ca tt c cc thanh ghi trong 8951 sau khi reset h thng c tm tt nh
sau:

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-Thanh ghi quan trng nht l thanh ghi b m chng trnh PC c reset tai a ch
0000H. Khi ng vo RST xung mc thp, chng trnh lun bt u ti a ch 0000H
ca b nh chng trnh. Ni dung ca RAM trn chip khng b thay i bi tc ng
ca ng vo reset.
3. Cc ngt ca 8051.
a. Cc ngt timer.
Cc ngt timer c a ch Vector ngt l 000BH (timer 0) v 001BH (timer
1). Ngt timer xy ra khi cc thanh ghi timer (TLx ITHx) trn v set c bo trn
(TFx) ln 1. Cc c timer (TFx) khng b xa bng phn mm. Khi cho php cc
ngt, TFx t ng b xa bng phn cng khi CPU chuyn n ngt.
b. Cc ngt cng ni tip.
Ngt cng ni tip xy ra khi hoc c pht (TI) hoc c ngt thu (KI) c
t ln 1. Ngt pht xy ra khi mt k t c nhn xong v ang i trong
SBUP c c.
Cc ngt cng ni tip khc vi cc ngt timer. C gy ra ngt cng ni
tip khng b xa bng phn cng khi CPU chuyn ti ngt. Do c hai ngun
ngt cng ni tip Ti v RI. Ngun ngt phi c xc nh trong ISR v c to
ngt s c xa bng phn mm. Cc ngt timer c ngt c ngt c xa bng
phn cng khi CPU hng ti ISR.
c. Cc ngt ngoi.
- Cc ngt ngoi xy ra khi c mt mc thp hoc cnh xung trn chn INT0 hoc
INT1 ca vi iu khin. y l chc nng chuyn i ca cc bit Port 3.(Port 3.2 v
Port 3.3).
Cc c to ngt ny l cc bit IE0 v IE1 trong TCON. Khi quyn iu khin chuyn
n ISR, c to ra ngt ch c xa nu ngt c tch cc bng cnh xung. Nu ngt
c tch cc theo mc, th ngun yu cu ngt bn ngoi s iu khin mc ca c
thay cho phn cng.
S la chn ngt tch cc mc thp hay tch cc cnh xung c lp trnh qua
cc bit IT0 v IT1 trong TCON. Nu IT1 = 0, ngt ngoi 1 c tc ng bng mc
thp chn IT1. Nu IT1 = 1 ngt ngoi 1 s c tc ng bng cnh xung. trong ch
ny, nu cc mu lin tip trn chn INT1 ch mc cao trong mt chu k v ch mc
thp trong chu k k, c yu cu ngt IE1 trong TCON c t ln 1, ri bit I yu cu
ngt.
Nu ngt ngoi c tc ng bng cnh xung th ngun bn ngoi phi gi chn tc
ng mc cao ti thiu mt chu k v gi n mc thp thm mt chu k na m
bo pht hin c cnh xung. Nu ngt ngoi c tc ng theo mc th ngun bn
ngoi phi gi tn hiu yu cu tc ng cho n khi ngt c yu cu c tht s to
ra v khng tc ng yu cu ngt trc khi ISR c hon tt . Nu khng mt ngt
khc s c lp li.

[Year]
III. NGN NG KEIL C CHO 89C51

1. Gii thiu ngn ng C
Trong k thut lp trnh cho vi iu khin, ngn ng lp trnh c chia lm 2 loi:

Ngn ng cp thp v ngn ng cp cao.
Ngn ng cp thp thng i hi ngi lp trnh phi hiu r v cu trc vi iu
khin v tp lnh ca n v chng trnh thng kh di.
Ngn ng cp cao l cc ngn ng gn vi con ngi hn do vic lp trnh d dng
v n gin hn. Cc ngn ng cp cao thng gp l C, Visual Basic, Pascal trong
ngn ng C l thng dng hn c trong k thut vi iu khin. Khi s dng ngn ng ny
ngi lp trnh khng cn phi hiu su sc v cu trc ca b vi iu khin cng khng
phi nghin cu tp lnh ca n. iu ny cho php mt ngi cha quen vi mt ngn
ng cho trc s d dng xy dng c chng trnh mt cch nhanh chng m khng
phi mt nhiu thi gian tm hiu v cu trc ca vi iu khin . Chng trnh vit
bng ngn ng C s c mt phn mn gi l trnh bin dch (Compiler) chuyn sang
dng hp ng trc khi chuyn sang ngn ng my. i vi h vi iu khin 8051 ta c
chng trnh Keil C, vi iu khin AVR c Vision C, vi iu khin PIC c PIC C
2. Cu trc chng trnh C

//nh km cc file
#include <file.h>
#include <file.c>
//Khai bo bin ton c_c

unsigned char x,y;
int z;
long n=0;
//Khai bo v nh ngha cc hm
void Hm1(void)
{
//Cc cu lnh
}
void Hm2(unsigned char x)

{
//Cc cu lnh
}
//Hm chnh bt buc chng trnh no cng phi c.
void main(void)
{
//Cc cu lnh
}
Cc cu lnh trong chng trnh chnh c th l lnh gi cc hm con khai bo
trn.

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Khi c li gi hm con th chng trnh nhy n hm thc hin hm xong ri
quay li chng trnh chnh (hm main) thc hin tip cc hm hoc cc cu lnh.
Cc cu lnh trong C kt thc bng du ;.
Cc li gii thch c m u bng du /* v kt thc bng du */.
Nu cc li gii thch trn cng mt hng th c th dng du //.
Khi lp trnh chng ta nn gii thch cc cu lnh hay cc khi lnh sau ny d sa
li.
2.1.Cc kiu d liu hay dng trong Keil C
Trong C ta thng dng cc kiu d liu sau:
Dng bin S bytes S bits Min gi tr

Char 1 8 -128 n +127
Unsigned char 1 8 0 n 255
Short 2 16 -32768 n +32767
Unsigned short 2 16 0 n 65535
Int 2 16 -32768 n +32767
Unsigned int 2 16 0 n 65535
Long 4 32 -2^31 n +2^31-1
Unsigned long 4 32 0 n 2^32-1
Khai bo bin:
Cu trc : Kiu bin Tn bin

VD: unsigned char x ;
Khi khai bo ta c th gn lun gi tr ban u cho bin.
VD: Thay v dng 2 lnh: unsigned char x;
x = 0;
Ta ch cn 1 dng lnh unsigned char x= 0;
Ta cng c th khai bo nhiu bin cng kiu cng 1 lc.
VD: unsigned int x,y,z;
Ngoi ra dng tin cho vic lp trnh vi iu khin, chng trnh bin dch cn h
tr cc loi bin sau:
Dng bin S bytes S bits Min gi tr

Bit 0 1 0;1
Sbit 0 1 0;1
Sfr 1 8 0 n 255
Sfr16 2 16 0 n
65535
2.2. Cc hm trong C
Trong ngn ng C ta thng ta thng dng cc loi hm sau:
Hm c tr v gi tr
Cu trc: Kiu gi tr hm tr v Tn hm (Danh sch cc bin truyn vo hm)

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{
// Cc lnh x l
}
VD: Unsigned char phep_cong(unsigned char x,unsigned char y)
{
//Cc lnh x l
}
Hm khng c tr v gi tr
Cu trc: Void Tn hm (danh sch cc bin truyn vo hm)
{
//Cc lnh x l
}
VD: void Phep_cong(unsigned int x,y)
{
//Cc lnh x l
}
Hm khng truyn bin vo
Cu trc: Void Tn hm (void)
{
// Cc cu lnh x l
}
Hm khng truyn bin vo
Cu trc: void Tn hm (unigned char x)
{
// Cc cu lnh x l
}
S bin truyn vo hm l ty (min b nh) v c ngn cch bi du ,.
Ngoi cc hm trn th Keil C cn c mt loi hm ring cho vi iu khin na l
hm ngt.
Cu trc: Tn hm(void) interrupt ngun ngt
{
// Cc lnh x l khi c ngt xy ra
}
Hm ngt khng c php tr li gi tr hay truyn tham bin vo hm.
Tn hm ta c th t bt k nhng ta nn t tn sao cho d nh nht.
Interrupt l t kha ch hm ngt.
Ngun ngt ca vi iu khin c cho nh bng bn di:
Loi ngt C ngt Ngun ngt a ch ngt

Ngt ngoi th 0 IE0 0 0003H
Ngt Timer/Counter 0 TF0 1 000BH
Ngt ngoi th 1 IE1 2 0013H
Ngt Timer/Counter 1 TF1 3 001BH
Ngt port ni tip RI hoc TI 4 0023H
Ngt Timer/Counter 2 TF2 hoc EXF2 5 002BH
2.3. Cc ton t c bn trong C

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Php gn : =
VD: x=y; // x phi l bin y c th l bin hoc gi tr nhng phi ph hp
kiu.
Php cng: +
Php tr: -
Php nhn: *
Php chia: /
Cc ton ton logic:
Bng : ==
And: &&
Or: ||
Not: !
Dch tri: <<
Dch phi: >>
2.4. Cc lnh thng dng

Lnh r nhnh If:
Lnh If c cc cu trc sau:
If (iu kin)
{
// Cc cu lnh x l khi iu kin ng
}
If (iu kin)
{
// Cc cu lnh x l khi iu kin ng
}
Else
{
// Cc cu lnh x l khi iu kin khng ng
}
If (iu kin 1)
{
// Cc cu lnh x l khi iu kin 1 ng
}
Else if (iu kin 2)
{
// Cc cu lnh x l khi iu kin 2 ng
}
.
Else
{
//Cc cu lnh x l khi tt c cc iu kin trn u khng ng
}
Lnh la chn Switch ():
Cu trc: Switch (bin)

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{
Case giatri 1: {//Cc cu lnh Break;}

Case giatri n: {//Cc cu lnh Break;}
}
Vng lp While:
Cu trc: While (expresstion)
{
Statements
}
Cu trc: While(1) {}; to vng lp v tn rt hay dng trong lp trnh vi iu
khin, chng trnh chnh s c vit trong du {}.
Vng lp Do While:
Cu trc: Do statements While (condition);
Vng lp ny s thc hin cc cu lnh trc ri mi kim tra iu kin sau. V vy
cc cu lnh s c thc hin t nht l mt ln ngay c khi iu kin khng bao gi
c tha mn.
Vng lp for:
Cu trc: For (initialization; condition; increase)
{
statements;
}
Chc nng chnh ca vng lp for l lp li statements khi condition vn cn ng nh
trong vng lp while nhng trong lnh for c gi tr khi to (initialization) v c lnh tng
(increase) nn vng lp for s lp li cc cu lnh vi mt s ln xc nh trc.
Phn khi to v phn lnh tng c th b qua nhng phi c du chm phy (;) ngn
cch gia chng. V d chng ta c th vit for(;n<10;) hoc for(;n<10;n++).

[Year]
IV. HNG DN S DNG KEIL C LP TRNH CHO 89C52

1. Khi to 1 Project mi
Khi dng chng trinh Keil C ta s c giao din nh sau:(giao din c th khc nu bn
m ln u. y do mnh lm nhiu ln nn chng trnh s t load Project m mnh
m trc .)
to 1 project mi chn Project / New Project

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Hp thoi create new project hin ra:

[Year]
Nhp tn project mi v chn ng dn lu ri chn save. Hp thoi Select Device for
Taget Taget 1 hin ra:
Trong hp thoi ny hin th 1 lot cc hng sn xut 8951. Bn lp trnh cho con no th
chn hng , sau kch chut vo du + chn loi IC ca hng . y ta lp trnh
cho AT89C51 ca hng ATMEL nn ta chn nh bn di. Khi chon loi chip no th 1
bng bn phi s hin th cc tnh nng ca chip. Sau nhp OK. Khi c hi Copy
standard 8951 startup code to project and addfile to project th bn nn chn NO v nu
chon YES th cng chng c li g ngoi vic lm cho chng trnh ca bn nng thm m
thi.

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to 1 file code mi bn chn File / New hoc nhn Ctrl + N.

[Year]
Sau mt ca s text hin ra ta lu li file ny dng file.c mc d file ny cha c g.
Sau khi save file xong ta tin hnh add file.c vo Project. Trong ca s Project window click
vo du + ca th mc Taget 1 ri nhp phi vo Source group 1 chn Add file to Group
Source Group 1.

[Year]
Sau bn chn file.c m bn cn add vo project. Sau khi add xong bn Project
window s xut hin tn file.c m bn add. Cng vic lc ny ca bn l tip tc vit code
cho Project ca mnh. Sau khi vit code xong ta s c giao din nh hnh bn di.
2. Bin dch chng trnh v m phng:
Sau khi vit code xong bn lu li nhng g thc hin. Sau bn tin hnh bin dch
chng trnh bng cch nhn phm F7 hay chn Project / Build Taget.

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Nu chng trnh ca bn c li th bn phi tin hnh sa cc li cho n khi khng

cn li na. Sau to file.hex bn vo Project / Option for Taget Taget 1

[Year]
Ca s Option for Target Target 1 hin ra. Trong tab Target bn chn tn s dao ng
cho loi Vi iu khin ca bn ti Xtal (MHz). Trong tab Output bn nh du P vo
Create HEX file ri nhn OK.
Sau bn tip tc bin dch li chng trnh ln na th file.hex s c to ra.

m phng chng trnh bn vo Debug / Start/Stop Debug Session hoc nhn phm
tt l Ctr + F5 hoc bn cng c th nhp vo biu tng trn thanh cng c.

[Year]
hin th cc Port cc thanh ghi bn chn trong Peripherals

[Year]
Cc thanh ghi v cc port c chn s hin th trong trong cc ca s nh nh bn
di
no c du tick (P) th ang mc cao (5V) cn cc khng c du tick th

ang mc thp (0V).
tin hnh chy m phng bn nhn F11. Mi ln nhn th chng trnh s chy 1
lnh. Nu bn ang chy chng trnh delay m qua lu th bn c th nhn Ctrl + F11 bo
qua hm .
V. M PHNG MODUL NG DNG V CHNG TRNH MU
Modul 1: iu khin Led n hnh tri tim:

1. S kt ni phn cng mch m phng:

[Year]

[Year]
2. Chng trnh:
#include <at89x51.h>/*trnh bin dch s gi file th vin ca 89 ra*/
#include <stdio.h>
//hm delay
void wait( unsigned int x)
{
unsigned int i;
for (i=0;i<x;i++);
}
//Chng trnh con 1 led chy
void ledchay(void)
{
unsigned int led = 1;
do
{
P0 = ~led; // ~ NOT o ngc bit
P2 = ~led;
wait(12000); //i cho nhn thy trang thi trc
led =led << 1; //dch tri bit 1
}while(led < 128); //trang thi 0111 1111
if (led == 128)
{
P0 = ~led;
P2 = ~led;
wait(12000);
P0 = 255;
P2 = 255;
led = 1;
do
{
P1 = ~led;
P3 = ~led;
wait(12000);
led = led <<1;
}while(led < 128);
if (led == 128)
{
P1 = ~led;
P3 = ~led;
wait(12000);
led = 128;
}
do //Chay nguoc lai
{
led = led >> 1;
P1 = ~led;

[Year]
P3 = ~led;
wait(12000);
}while (led > 1);
if (led == 1)
{
P1 = 255;
P3 = 255;
led =128;
}
do
{
P0 = ~led;
P2 = ~led;
led = led >> 1;
wait(12000);
}while (led >1);
}
}
// Chng trnh con led sng dn ri tt dn
void sangdan(void)
{
unsigned int led =1;
do
{
P0 = ~led;
P2 = ~led;
wait(12000);
led = led|(led << 1);//trang thi led 0000 0001
}while (led < 255); //or vi trng thi dch ln 1 l 0000 0010
if (led == 255) //kt qu 0000 0011
{
P0 = 0;
P2 = 0;
led = 1;
}
do
{
P1 = ~led;
P3 = ~led;
wait(12000);
led = led|(led <<1);
}while (led < 255);
if (led == 255)
{
P1 = ~led;
P3 = ~led;

[Year]
wait(12000);
led = 128; //tat dan
}
do
{
P1 = led;
P3 = led;
wait(12000);
led = led|(led >>1);
}while(led <255);
if (led == 255)
{
P1 = 255;
P3 = 255;
wait(12000);
led = 128;
}
do
{
P0 = led;
P2 = led;
wait(12000);
led = led|(led >>1);
}while(led <255);
if (led == 255)
{
P0 = 255;
P2 = 255;
wait(12000);
led = 1;
}
}
//Chng trnh con led sng dn ri tt dn
void sangdon(void)
{
unsigned char sck,slx,led,ledtam1,ledtam2;
sck = 16;
ledtam1 = 0;
ledtam2 = 0;
P0 = 255; //tt led
P1 = 255;
P2 = 255;
P3 = 255;
//Cac led bat dau sang don
do
{

[Year]
slx = 0;
led = 1;
do
{
wait(8000);
P0 = ~(ledtam1|led); //~(0000 0001 | 0000 0010)
P2 = ~(ledtam1|led);
led = led <<1;
slx++;
if (slx == sck) break;
}while (slx<9);
if (slx ==9) led=1;
do
{
wait(8000);
led = led <<1;
slx++;
}while(slx<=sck);
ledtam1 = ~P0;
ledtam2 = ~P1;
sck--;
}while (sck >0);
// Cac led bat dau tat don
sck = 16;
ledtam1 = 0;
ledtam2 = 0;
P0 = 0; //sang het
P1 = 0;
P2 = 0;
P3 = 0;
do
{
slx = 0;
led = 128; //tat 1 led
do
{
wait(8000);
P1 = (ledtam1|led);
P3 = (ledtam1|led);
led = led >>1;
slx++;
if (slx == sck) break;
}while (slx<9);

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if (slx ==9) led=128;
do
{
P0 = (ledtam2|led);
P2 = (ledtam2|led);
wait(8000);
led = led >>1;
slx++;
}while(slx<=sck);
ledtam1 = P1;
ledtam2 = P0;
sck--;
}while (sck >0);
}
//Chng trnh chnh
void main(void)
{
for(;;)
{
ledchay();
sangdan();
sangdon();
}
}

[Year]
Modul 2: Mch ng h s c nt chnh hin th kt qu trn led 7 on:

1. S kt ni phn cng mch m phng:

[Year]
2. Chng trnh:
#include <at89x51.h>
sbit SCK = P2^0;
sbit SERI_IN = P2^1;
sbit RCK = P2^2;
sbit MR = P2^3;
sbit OE = P2^4;
sbit SELECT = P3^2;
sbit UP = P3^3;
unsigned int DEM,MODE;
unsigned int GIO,PHUT,GIAY;
unsigned int DV_GIO,CH_GIO,DV_PHUT,CH_PHUT,DV_GIAY,CH_GIAY;
unsigned int MA[] = {0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90,0xBF};
unsigned int HT[8];
//Hm delay
void delay(unsigned long x)
{
unsigned int i;
for(i=0;i<x;i++);
}
//Chng trnh ngt khi Timer0 trn

void timer0_int(void) interrupt 1
{
DEM++;
TH0 = 0x3C; //50 000 uS
TL0 = 0xB0;
TF0 = 0;
}
//Chng trnh ngt ngoi INT0

void ngat0(void) interrupt 0
{
MODE++;
if (MODE == 4)
MODE = 0;
}
//Chng trnh ngt ngoi INT1

void ngat1(void) interrupt 2
{
switch (MODE)
{
case 0:
break;

[Year]
case 1:
GIO++;
if (GIO == 24) GIO = 0;
break;
case 2:
PHUT++;
if (PHUT == 60) PHUT = 0;
break;
case 3:
GIAY++;
if (GIAY == 60) GIAY = 0;
break;
}
}
//Chng trnh con gii m HEX sang BCD

void hex_bcd(void)
{
CH_GIO = GIO/10; //chia lay phan nguyen
DV_GIO = GIO%10; //chia lay phan du
CH_PHUT = PHUT/10;
DV_PHUT = PHUT%10;
CH_GIAY = GIAY/10;
DV_GIAY = GIAY%10;
}
//Chng trnh con chuyn t m BCD sang m 7 on

void bcd_7doan(void)
{
HT[0] = MA[CH_GIO];
if (MODE == 1)
HT[1] = MA[DV_GIO]&0x7F; //Hin th thm du chm bit ang iu chnh
hng no
else
HT[1] = MA[DV_GIO];
HT[2] = 0xBF; //ma dau gach ngang phan cach
HT[3] = MA[CH_PHUT];
if (MODE == 2)
HT[4] = MA[DV_PHUT]&0x7F;
else
HT[4] = MA[DV_PHUT];
HT[5] = 0xBF;
HT[6] = MA[CH_GIAY];

[Year]
if (MODE == 3)
HT[7] = MA[DV_GIAY]&0x7F;
else
HT[7] = MA[DV_GIAY];
}
//Chng trnh con hin th kt qu ra led 7 on

void display(void)
{
unsigned int i;
OE = 0; //Cho phep hoat dong
MR = 0; //Reset he thong
MR = 1;
SCK = 0;
RCK = 0;
SERI_IN = 1; //ngo vao noi tiep dich muc 1
for (i = 0;i<8;i++)
{
SCK = 1;
SCK = 0;
RCK = 1;
RCK = 0;
P1 = HT[i];
delay(50);
P1 = 0xFF;
SERI_IN = 0;
}
}
//Chng trnh chnh

void main(void)
{
IT1 = 1; //Cc ngt ngoi tc ng bng cnh
IT0 = 1;
MODE = 0;
TH0 = 0x3C;
TL0 = 0xB0;
TMOD = 0x01; //Chn Timer0 lm vic ch 16 bit
IE = 0x87;
TR0 = 1;
for(;;)
{
GIO = 0;
do

[Year]
{
PHUT = 0;
do
{
GIAY = 0;
do
{
DEM = 0;
do
{
hex_bcd();
bcd_7doan();
display();
}while (DEM <20); //lap lai 50 lan cho dat 1s
GIAY++;
}while (GIAY<60);
GIAY = 0;
PHUT++;
}while (PHUT < 60);
PHUT = 0;
GIO++;
}while (GIO <24);
}
}

[Year]
Modul 3: Led ma trn chy ch qung co:
1. S nguyn l mch m phng:

[Year]
2. Chng trnh:
sbit SCK = P2^0;
sbit RCK = P2^1;
sbit D_IN = P2^2;
sbit MR = P2^3;
sbit OE = P2^4;
//Bng m cc k t cn hin th
unsigned char code MA[1000] = {
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
0xFF,0xFD,0xFD,0x01,0xFD,0xFD, //T
0xFF,0x01,0xED,0xCD,0xAD,0x73, //R
0xFF,0X81,0x7F,0x7F,0x7F,0X81, //U
0xFF,0x83,0x7D,0x7D,0x7D,0x83, //O
0xFF,0x01,0xF7,0xEF,0XDF,0x01, //N
0xFF,0x83,0x7D,0x6D,0x6D,0x8D, //G
0xFF,0xFF,0xFF,0xFF,
0xEF,0x01,0x6D,0x7D,0x7D,0x83, //D
0xFF,0x07,0xDB,0xDD,0xDB,0x07, //A
0xFF,0x7D,0x01,0x7D, //I
0xFF,0X01,0xEF,0xEF,0xEF,0x01, //H
0xFF,0x83,0x7D,0x7D,0x7D,0x83, //O
0xFF,0x83,0x7D,0x7D,0x7D,0xBB, //C
0xFF,0xB3,0x6D,0x6D,0x6D,0x9B, //S
0xFF,0x81,0x7F,0x7F,0x7F,0x81, //U
0xFF,0x01,0xED,0xED,0xED,0xF3, //P
0xFF,0x01,0xFB,0xF7,0xFB,0x01, //M
0xFF,0x01,0xEF,0xD7,0xBB,0x7D, //K
0xFF,0xFD,0xFB,0x07,0xFB,0xFD, //Y
0xFF,0x81,0x7F,0x7F,0x7F,0x81, //U

[Year]
0xFF,0x83,0x7D,0x7D,0x7D,0x83, //O
0xFF,0x83,0x7D,0x7D,0x7D,0x83, //O
0xFF,0x7D,0x01,0x7D, //I
0xFF,0x01,0xFB,0xF7,0xFB,0x01, //M
0xFF,0x7D,0x01,0x7D, //I
0xFF,0x01,0xEF,0xD7,0xBB,0x7D, //K
0xFF,0x83,0x7D,0x7D,0x7D,0x83, //O
0xEF,0x01,0x6D,0x7D,0x7D,0x83, //D
0xFF,0x7D,0x01,0x7D, //I
0xFF,0x01,0x6D,0x6D,0x6D,0x7D, //E
0xFF,0xFF,0xEF,0xEF,0xEF,0xEF,0xFF,0xFF,
0xEF,0x01,0x6D,0x7D,0x7D,0x83, //D
0xFF,0x7D,0x01,0x7D, //I
0xFF,0x01,0x6D,0x6D,0x6D,0x7D, //E
0xFF,0x81,0x7F,0x7F,0x7F,0x81, //U

[Year]
0xFF,0x81,0x7F,0x7F,0x7F,0x81, //U
0xFF,0xC1,0xBF,0x7F,0xBF,0xC1, //V
0xFF,0x7D,0x01,0x7D, //I
0xFF,0x39,0xD7,0xEF,0xD7,0x39, //X
0xFF,0x81,0x7F,0x7F,0x7F,0x81, //U
0xFF,0x01,0x7F,0x7F,0x7F,0x7F, //L
0xFD,0xFB,0x07,0xFB,0xFD, //Y
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
};
//Ham delay
void delay(unsigned long time)
{
unsigned int i;
for(i=0;i<time;i++);
}
//Ham chinh
void main(void)
{
unsigned int count0,count1,count2,i,j,k;
for(;;)
{
OE = 0; //Cho phep cac IC 74HC595 hoat dong
MR = 0; //Reset he thong
MR = 1;
SCK = 0;
RCK = 0;
//RCK = 1;
count0 = 765;

[Year]
for(i = 0;i < count0; i++)
{
count1 = 2; //Toc do chay chu
for (j = 0;j<count1;j++)
{
count2 = 48;
D_IN = 1;
for (k = i;k < i+count2; k++)
{
SCK = 1;
SCK = 0;
RCK = 1;
RCK = 0;
P1 = MA[k];
delay(25);
P1 = 0xFF;
D_IN = 0;
}
}
}
}
}
Modul 4: Chy ch qung co trn LCD:

Yu cu: Hin th 2 dng ch trn LCD ri cho dng ch dch sang tri.
1. Mch nguyn l m phng:

[Year]

[Year]
2. Chng trnh:
#include <string.h>
sfr LCDdata = 0xA0;
sbit BF = 0xA7;
sbit RS = P1^0;
sbit RW = P1^1;
sbit E = P1^2;
//Ham kiem tra xem LCD co san sang hay khong!
void kiemtra(void)
{
RS = 0; //Chon thanh ghi lenh
RW = 1; //Chon che do doc tu LCD
LCDdata = 0xFF;
while (BF)
{
E = 0;
E = 1;
}
}
//Ham delay
void delay(long time)
{
unsigned int i;
for (i=0;i<time;i++);
}
//Ham ghi lenh len LCD
void control(unsigned char x)
{
RS = 0;
RW = 0; //Chon che do ghi len LCD
LCDdata = x; //Ghi len LCD lenh co ma la x
E = 1;
E = 0; //Tao xung tren chan E de LCD chot du lieu lai
kiemtra(); //Kiem tra LCD co san sang khong
}
//Ham ghi 1 ki tu len LCD
void write(unsigned char a)
{
RS = 1; //Chon thanh ghi du lieu
RW = 0;
LCDdata = a;
E = 1;
E = 0;
kiemtra();

[Year]
}
//Ham ghi 1 chuoi ki tu len LCD
void writes(unsigned char *s)
{
unsigned char lens,i;
lens = strlen(s);
for(i = 0;i<lens;i++)
{
write(*(s+i));
delay(4000);
}
}
// Ham khoi tao LCD
void khoitaoLCD(void)
{
control(0x38); //Khoi tao LCD o che do 2 dong va ma tran 5x7
control(0x0E); //Bat man hinh hien thi va cho con tro nhap nhay
control(0x01); //Xoa man hinh hien thi LCD
}
void main(void)
{
unsigned int lens,i;
for(;;)
{
khoitaoLCD();
control(0x81); //Dua con tro LCD ve ki tu thu 2 dong thu nhat
writes("DAI HOC SU PHAM KY THUAT TP HCM");
control(0xC6); //Dua con tro LCD ve ki tu thu 7 dong thu 2
writes("KHOA DIEN - DIEN TU");
control(0x0C); //Tat con tro
delay(50000);
lens = strlen("DAI HOC SU PHAM KY THUAT TP HCM");
control(0x81);
i = 0;
do
{
control(0x1C); //Dich tat ca cac ki tu sang ben trai
delay(5000);
i++;
}while(i<lens);
delay(10000);
}
}

[Year]
Modul 5: Giao tip vi iu khin vi ADC o nhit hin th kt qu trn

LCD:
Yu cu: Kt ni ADC vi 2 cm bin nhit LM35 o nhit a kt qu v VK x
l ri hin th kt qu trn LCD.
1. Mch nguyn l m phng:

[Year]
2. Chng trnh:
#include <string.h>
#include <math.h>
//sfr adc = 0x90;
sfr LCDdata= 0xA0;
sbit BF = P2^7;
sbit RS = P3^0;
sbit RW = P3^1;
sbit E = P3^2;
sbit A = P3^3;
sbit ALE = P3^4;
sbit START = P3^5;
signed int adc0,adc1;
unsigned int dvi,chuc,tram,tam;
const unsigned char ma[] ="0123456789- ";
void kiemtra(void)
{
RS = 0; //Chn thanh ghi lnh
RW = 1; //Chn ch c t LCD
while (BF)
{
E = 1;
E = 0;
}
}
//Ham delay
void delay(long time)
{
unsigned int i;
for (i=0;i<time;i++);
}
//Ham ghi lenh len LCD
void control(unsigned char x)
{
RS = 0;
RW = 0; //Chn ch ghi ln LCD
LCDdata = x; //Ghi ln LCD lnh c m l x
E = 1;
E = 0; //To xung cht d liu trn LCD li
delay(70);
}
//Ham ghi 1 ki tu len LCD
void write(unsigned char a)
{

[Year]
RS = 1; //Chn thanh ghi d liu
RW = 0;
LCDdata = a;
E = 1;
E = 0;
delay(70);
}
//Hm ghi mt chui k t ln LCD
void writes(unsigned char *s)
{
unsigned char lens,i;
lens = strlen(s);
for(i = 0; i<lens;i++)
{
write(*(s+i));
delay(70);
}
}
// Hm khi to LCD
void khoitaoLCD(void)
{
control(0x38); //Khoi tao LCD o che do 2 dong va ma tran 5x7
control(0x0E); //Bat man hinh hien thi va cho con tro nhap nhay
control(0x01); //Xoa man hinh hien thi LCD
}
//Hm c nhit chuyn i t ADC v VK v x l
void read_convert(signed int adc)
{
ALE = 1;
START = 1;
ALE = 0;
delay(50);
START = 0;
adc = P1;
adc = adc - 55;
if(adc >= 0)
{
dvi = adc%10;
tam = adc/10;
chuc = tam%10;
tram = tam/10;
if(tram == 0)
{
tram = 11;
if (chuc == 0) chuc = 11;

[Year]
}
}
else
{
adc = abs(adc);
tram =10; //v tr du "-"
chuc = adc/10;
dvi = adc%10;
if (chuc == 0) chuc = 11;
}
}
//Chng trnh chnh
void main(void)
{
khoitaoLCD();
control(0x80);
writes("KENH 0: DO C");
control(0xC0);
writes("KENH 1: D0 C");
for(;;)
{
A = 1; //Chn knh 0
read_convert(adc0);
control(0x88); a con tr n k t th 8 ca dng 1
write(ma[tram]);
write(ma[chuc]);
write(ma[dvi]);
A = 0; //Chn knh 1
read_convert(adc1);
control(0xC8);
write(ma[tram]);
write(ma[chuc]);
write(ma[dvi]);
control(0x0C); //Tt du nhy ca con tr
}
}

[Year]
PHN B: VIT NGN NG CCSC CHO PIC 16F877A
I. VI NT KHI QUT V PIC 16F877A
1. Gii Thiu PIC 16F877A
PIC l mt h vi iu khin RISC c sn xut bi cng ty Microchip Technogy.
Pic l vit tt ca Programmable Intelligent Computer
Th h Pic u tin l Pic 1650 c pht trin bi Microelectronis Division thuc General-
Intrument
2. Mt s c tnh ca vi iu khin PIC
L CPU 8/16 bit

C b nh Flash v ROM
C cc cng xut nhp I/O ports
C timer 8/16 bit
C cc b chuyn i ADC 10/12 bit

C h tr giao tip LCD
C b nh ni EEPROM-c th ghi/xa ln ti 1 triu ln
C khi iu khin ng c,c encoder.
3. S Chn v c im
a- S chn:

[Year]
b- c im:
C timer 8/16 bit

C 5 port xut nhp: A, B, C, D, E.
8 knh chuyn i A/D: AN0, AN1, AN2, AN3, AN4, AN5, AN6, AN7.
C b so snh tng t
B nh d liu EEPROM (byte).
Chn cc port ngoi cc chc nng xut nhp cn c mt s chc nng khc.
4. Cc Port v Chc Nng
PortA, B, C, D, E cha trong bank 0
Cc thanh ghi nh hng d liu tng ng vi cc port l:
TRISA, TRISB, TRISC, TRISD, TRISE cha trong Bank1
PORT A
Port A l Port hai chiu ch c 6 bit

Khi TRISA = 1 th port A tr thnh port nhp.
Khi TRISA = 0 th port A tr thnh xut.
Tt c cc chn ca port chun TTL khi c

[Year]
nhiu ng v tr chn RA4
PORT B
Port B l port hai chiu 8 bit.

Khi PortB = 1 th mt port nhp
Khi PortB = 0 th mt port xut.
Mi chn ca Port B c in tr ko ln. Bit 7 ca thanh ghi OPTION_REG = 0 th c
th m tt c cc in tr ko ln.
Khi Port B c thit lp l ng ra th s t ng tt chc nng in tr ko ln.
PORT C
Port C l Port hai chiu 8 bit.

TRISC = 1 th mt Port nhp
TRISC = 0 th mt Port xut.
PORT D
Port D c 8 bit vi ng vo c mch schmitt trigger.

Khi TRISD = 1 th Port nhp
Khi TRISD = 0 th port xut
PORT E
v Port E c 3 chn c cu hnh c lp thit lp ng vo hay ra. C mch in schmitt

trigger ng vo.
v Port E tr thnh ng vo vi iu khin I/O khi bit th 4 PSPMODE ca TRIS = 1. V
cng chc chn rng TRISE <0:2>=11 v ADCON1 c cu hnh nh nhng ng xut
nhp s.
v Hai bit RP1, RP0 nm trong thanh ghi STATUS dng chn Bank.
5. Cc Khi Trong PIC 16F877A

[Year]
Khi ALU
Khi b nh chng trnh
Khi b nh d liu
Khi b nh file thanh ghi Ram
Khi thanh ghi t bit
Khi ngoi vi timer
Khi giao tip
Khi chuyn i ADC
Khi cc Port xut nhp
II. TRNG TM CA PIC 16F877A

1. B Nh PIC 16F877A
B nh chng trnh:
PIC16F877A c b m chng trnh 13 bit,qun l b nh chng trnh c dung

lng 8Kword x14 bit
Khi PIC b reset thanh ghi PC c gi tr 0000h, vector ngt c a ch 0004h
B nh d liu:
B nh d liu c chia thnh nhiu bank v cc thanh ghi c chc nng t bit.
Mi Bank c th m rng ln n a ch 7Fh
Thanh ghi c chc nng t bit nm nh c a ch thp ca mi Bank
Hai bit RP1RP0 chn Bnk
2. B inh Thi Timer 0

[Year]
B timer/ counter c nhng c im sau:
L timercounter 8 bit.
C th c ghi.
C b chia trc 8bit c th lp trnh bng phn mm.
Cho php la chn ngun xung clock bn trong hoc bn ngoi.
Pht sinh ngt khi trn t FFFh n 00h.
Cho php la chn tc ng cnh xung clock bn ngoi.
Bit TOCS(OPTION_REG<5>) bng 1 th chn ch m counter. Trong ch counter

th timer0 s tng gi tr m sau mi khi c xung tc ng cnh ln hay xung chn RA4
/TOCKI. Cnh tc ng ca xung c la chn bi bit TOSE(OPTION_REG<4>): tose=0 th
chn cnh ln,ngc li th chn cnh xung.
a- Ngt ca timer 0:
Ngt ca timer0 c kch hot khi thanh ghi TMR0 trn t FFh n 00h. Khi trn xy ra th
bit TMR0IF(INTCON<2>) ln mc 1.
b- Timer vi ngun xung clock bn ngoi:
Khi khng x dng b chia trc th ng vo xung clock bn ngoi ging nh ng ra b chia
trc. S ng b ha TOCKI vi cc xung clock bn trong c thc hin bng cch ly mu
ng ra b chia nhng chu k Q2 v Q4 bn trong. Do , n rt cn thit cho tocki trng
thi cao t nht 2 tosc v trng thi mc thp t nht 2 tosc.
c- B chia trc:
Ch c mt b chia c tc dng m n c quan h vi TIMER0 v WDT. Khi gn b chia trc
cho TIMER0 th s khng c b chia cho Watchdog Timer v ngc li. B chia trc th
khng th c ghi. Cc bit PSA v PS2:PS0(OPTION_REG<3:0>) xc nh b chia v t l
chia.
3. Cc thanh ghi:
Thanh ghi chc nng c bit:
L thanh ghi c th c ghi, thanh ghi ny c nhng bit iu khin thit lp ch

chia trc cho Timer0/WDT,ngt INT bn ngoi, Timer0 v treo PORTB.
OPTION_REG REGISTER(ADDRESS 81h,181h)
RBPU INTEDG TOSC TOSE PSA PS2 PS1 PS0
Bit 7 Bit 0
Bit 7 RBPU: PORTB Pull-Up Enable(bit cho php treo PORTB)
1=khng cho php treo PORTB

[Year]
0=cho php treo PORTB
Bit6 INTEDR: Interup Edge Select(bit la chn cnh ngt)
1=chn cho php RB0/INT tch cc cnh ln.
0=chn cho php RB0/INT tch cc cnh xung.
Bit5 TOCS: TMR0 Clock Source Select bit(bit la chn ngun xung clock TMR0)
1=cho php nhn xung ng vo RA4/TOCKI.

0=cho php nhn xung ni bn trong.
Bit4 TOSE: TMR0 Clock Source Select bit(bit la chn kiu tc ng cho TMR0)
1=cho php xung vo chn RA4/TOCKI tch cc cnh xung.

0=cho php xung vo chn RA4/TOCKI tch cc cnh ln.
Bit3 PSA:Prescaler Asignment bit(bit gn b chia)
1=b chia c gn cho WDT

0=b chia gn cho TIMER0
Bit2-0 PS2:PS0: Presccaler Rate Select bits(bit la chn h s cho trc)
Gi tr bit T l T l
TMR0 WDT
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64

[Year]
111 1:256 1:128

Thanh Ghi Trng Thi _STATUS
STATUS REGISTER (ADDRESS 03h,83h,103h,183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP IRP 1 IRP 0 TO PD Z DC C
bit 7 bit 0
Bit7 IRP : bit la chn thanh ghi (dng a ch gin tip)
1 = bank 2,3 (100h 1FFh)
0 = bank 0,1 (00h FFh)
Bit6-5 RP0-RP1 : cc bit cha chn thanh ghi (dng da ch gin tip)
11 = bank 3(180h 1FFh)
10 = bank 2 (100h 17Fh)
10 = bank 1(80h FFh)
11 = bank 0 (00h 7Fh)
Mi bank l 128 byte
Bit4 TO : Time Out bit ( bit thi gian ch)
1 = sau khi m ngun , lnh CLRWDT hoc SLEEP
0 = thi gian ch ca WDT c thc hin.
Bit3 PD: Power-down bit(bit ngt ngun)
1=sau khi m ngun hoc bng lnh CLRWDT
0=thc thi lnh SLEEP
Bit 2 Z : zero bit (bit 0)
1 = khi kt qu bng 0

[Year]
0 = khi kt qu khc 0
Bit 1 DC : Digit carry / borrow bit ( bit trn / mn)
1 = khi cng 4 bit thp b trn
0 = khi cng 4 bit thp khng b trn
Bit 0 C : Carry/ borrow bit
1 = khi kt qu php ton c trn
0 = khi kt qu php ton khng b trn
S File thanh ghi:

[Year]
III. NGN NG CCSC CHO PIC 16F877A

1. Cu trc mt chng trinh CCSC:
Khai bo, hnng, bin, mng:

n -int X : khai bo kiu s nguyn (X=8 ,16 ,32 bit)
n -char : k t 8 bit
n -float : s thc 32bit
n -Thm signed hoc unsiged c s c du /ko du; mc nh l khng du
Vd :signed int8 a:bien a kiu int8
n khai bo mt mng hng s:
v d: const unsigned char:
dig[]={0XC0,0XF9,0XA4,0XB0,0X99,0X92,0X82,0XF8,0X80,0X90};
n Mng c kch thc ti a ph thuc VK

[Year]
Phm vi ca bin:
n C php: #include <filename>

hocc #include "filename
n -Filename : khai bo tn file *.h hoc *.c
Nu ch nh file ni khc th
th thm ng dn vo
Lun t uu chng tr
trnh
V d:
#include <16f877a.H> ; //khai bo tn file *.h hoc *.c
INCLUDES\COMLIB\MYRS232.C> ; //khai bo ng dn
#include<C:\INCLUDES
n C php: #use delay ((clock=speed)

hoc #use delay(clock
clock=speed, restart_wdt)
dng khai bo hm delay cho vk
Clock =tn s dao ng
ng th
thch anh s dng
mi s dng cc cc hm #use delay _ms();#use
Ch khi khai bo hm ny m
delay _us();
V d:: #use delay _us(500); delay 500ms

[Year]
Cc hm khai bo I/O trong CCSC:
n Output_low()
n Output_high()
n Output_bit ()
n input()
n output_X()
n input_X()
n port_b_pullups()
n set_tris_X()
n Hm output_low(pin),output_high(pin)
Hm ny t Pin l ng ra
Thit lp mc logic low(0v) hoc high(5v)
V d: Output_high(pin_D0) ;//pin D0=5v
n hm output_bit(pin,value)
xut gi tr 0/1 trn Pin
Value thng l gi tr ca mt bin no
n Hm input_X()
X: l port A-E
Tr v gi tr ang c ti 8bit trn port
n hm output_x(value)
Xut gi tr ra port
X: l port A-E
n Value 8 bit
n hm input_bit(pin)
Tr v trng thi l 0 hay1 ti chn IC
Gi tr ny l 1 bit
n port_b_pullups(value)
Ch portB c chc nng ny
Value =1 cho php treo port B ln ngun
Value=0 khng treo portB

[Year]
n set_tris_x(value )
nh ngha chn I/O cho port l ng ra hay vo
Ch c dng vi #use fast _io.
S dng #byte to bin ch n port v thao tc trn bin ny chnh l thao
tc trn port
Value c gi tr 8 bit ,mi bit l 1 chn :
=0 s set chn l ng ra
=0 set chn l ng vo
Khai bo ngt v thit lp ngt:
n ENABLE_INTERRUPTS( )
C php : enable_interrupts (level)
level l tn cc ngt c nh ngha trong file devices .h
n V d:
enable_interrupts(GLOBAL); cho php ngt ton cc
enable_interrupts(INT_TIMER0); cho php ngt Timer0
VI. HNG DN S DNG PHN MM CCSC
Khi khi ng phn mn CCSC ta c mn hnh sau:

[Year]
To project mi: c rt nhiu cch to sau y l mt cch v hnh minh ha
Project / project wizard / lu tn file cn to
Sau chon SAVE v mt ca s mi hin ra

[Year]
Sau nhp OK , vy l ta to c mt project va mn hnh lm vic hin
ra nh sau:
Khi mun dich t file .C sang file .HEX ta nhp vo COMPILE / chn
COMPILE Hoc nhn F9. Trinh bin dch hin ca s sau l bin dich thnh
cng:

[Year]
Ch : nu chng trnh vit c li th con tr s tr ngay v tr li.Chng ta xem
li v sa li l xong.
VII. CHNG TRNH MU V MODUL M PHNG CHO PIC
16F877A
Modul 1: 8 led n chp tt
S d m phng:
Chng trnh:
#include<16F877A.h>
#fuses NOWDT,PUT,NOPROTECT,NOLVP
#use delay(clock = 20000000)
#byte portb = 0x6//khai bao dia chi thanh ghi portb
#byte trisb = 0x86
void main()
{
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_psp(PSP_DISABLED);

[Year]
setup_spi(FALSE);
setup_timer_0(RTCC_INTERNAL|RTCC_DIV_1);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
trisb = 0;
while(true)
{
portb=0xff;
delay_ms(500);
portb=0;
delay_ms(500);
}
}
Modul 2: hin th trn LCD
S m phng:

[Year]
Chng trinh:
#INCLUDE <16F877A.H>
#include <KhaiBaoTGhi_16F877A.h>
#USE DELAY(CLOCK=20000000)
#BYTE PORTB = 0X06 //khai bao dia chi port
#BYTE TRISB = 0X86 //khai bao dia chi thanh ghi tris
#BYTE PORTD = 0X08
#BYTE TRISD = 0X88
#DEFINE RS RD0
#DEFINE RW RD1
#DEFINE E RD2
#DEFINE LCD PORTB
//CHUONG TRINH CON GHI MA DIEU KHIEN

VOID WRITE_CONTROL()
{
RS = 0; //cho phep gui lenh RW = 0;//cho phep ghi
E = 1; //cho phep(xung canh xuong 1 xuong 0)
E = 0;
DELAY_MS(1);
}
//CHUONG TRINH GHI DATA
VOID WRITE_DATA()
{
RS = 1; // RS=1 gui data
RW = 0;
E = 1;
E = 0;
DELAY_MS(1);
}
void hienthi()

[Year]
{
LCD = 0X01; //xoa LCD
WRITE_CONTROL();
LCD = 0X01;
WRITE_CONTROL();
LCD = 0X38; //khoi tao LCD 2 dong voi ma tran 5x7
WRITE_CONTROL();
LCD = 0X0C; //bat hien thi, tat con tro
WRITE_CONTROL();
LCD = 0X81; //dua con tro ve dong 1 tai o thu 1
WRITE_CONTROL();
LCD = 'T';
WRITE_DATA();
LCD = 'R';
WRITE_DATA();
LCD = 'U';
WRITE_DATA();
LCD = 'O';
WRITE_DATA();
LCD = 'N';
WRITE_DATA();
LCD = 'G';
WRITE_DATA();
LCD = ' ';
WRITE_DATA();
LCD = 'D';
WRITE_DATA();
LCD = 'H';
WRITE_DATA();
LCD = ' ';

[Year]
WRITE_DATA();
LCD = 'S';
WRITE_DATA();
LCD = 'P';
WRITE_DATA();
LCD = 'K';
WRITE_DATA();
LCD = 'T';
WRITE_DATA();
LCD = 0XC2; //ep con ttro ve dong 2 tai o thu2
WRITE_CONTROL();
LCD = 'T';
WRITE_DATA();
LCD = 'P';
WRITE_DATA();
LCD = ' ';
WRITE_DATA();
LCD = 'H';
WRITE_DATA();
LCD = 'O';
WRITE_DATA();
LCD = 'C';
WRITE_DATA();
LCD = 'H';
WRITE_DATA();
LCD = 'I';
WRITE_DATA();
LCD = 'M';
WRITE_DATA();
LCD = 'I';
WRITE_DATA();

[Year]
LCD = 'N';
WRITE_DATA();
LCD = 'H';
WRITE_DATA();
}
//CHUONG TRINH CHINH
void main()
{
TRISB = 0;
TRISD = 0;
DELAY_MS(100);
hienthi();
}
Modul 3: giao tip ADC
S m phng:
Chng trnh:
#include <16F877A.H>
#include <KhaiBaoTGhi_16F877A.h>
#fuses NOWDT,NOPROTECT
#DEVICE 16F877*=16 ADC=8
#BYTE PORTA = 0x05
#BYTE TRISA = 0x85
#BYTE PORTB = 0x06
#BYTE TRISB = 0x86
#BYTE PORTC = 0x07
#BYTE TRISC = 0x87
SIGNED INT8 adc0,adc1;

#USE DELAY(CLOCK = 20000000)

[Year]
void main()
{
setup_psp(PSP_DISABLED);
setup_spi(SPI_SS_DISABLED);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
setup_comparator(NC_NC_NC_NC);
setup_vref(FALSE);
set_tris_b(0);
set_tris_c(0);
setup_adc_ports(AN0_AN1_VREF_VREF);
setup_adc(ADC_CLOCK_INTERNAL);
// set_adc_channel(0);
// delay_ms(10);
while(1)
{
set_adc_channel(0);
delay_ms(10);
adc0 = read_adc();
output_B(adc0);
set_adc_channel(1);
delay_ms(10);
adc1 = read_adc();
output_C(adc1);

[Year]
}
Modul 4: ng h s hin thi trn led 7 oan:
M phng:
Chng trinh:
#include <16F877A.h>
#include<khaibaotghi_16f877a.h>
#fuses NOWDT,PUT,XT,NOPROTECT,HS,NOLVP
#use delay(clock=1000000)
#use fast_io(b)
#use fast_io(d)
#use fast_io(a)
#bit start=portb.1
#bit tphuc=portb.2
#bit gphuc=portb.3
#bit tgio=portb.4
#bit ggio=portb.5
int16 count;
int8 giay,phuc,gio,dvgiay,chgiay,dvphuc,chphuc,dvgio,chgio,i;
const unsigned char dig[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
//ma 7 doan

[Year]
void nhex_bcd()
{
chgiay=giay/10;
dvgiay=giay%10;
chphuc=phuc/10;
dvphuc=phuc%10;
chgio=gio/10;
dvgio=gio%10;
}
void nhienthi()
{
i=0;
while(i<5)
{
output_high(pin_d0);
portc=dig[dvgiay]; //xuat ma ra port
delay_ms(1);
output_low(pin_d0);
portc=dig[chgiay];
delay_ms(1);
output_low(pin_d1);
portc=dig[dvphuc];
delay_ms(1);
output_low(pin_d2);

[Year]
portc=dig[chphuc];
delay_ms(1);
output_low(pin_d3);
portc=dig[dvgio];
delay_ms(1);
output_low(pin_d4);
portc=dig[chgio];
delay_ms(1);
output_low(pin_d5);
i=i+1;
}
}
#int_ext //ngat ngoai

void ngat_ngoai()
{
while (true)
{
if (tphuc==0) //kiem tra nhan phim
{
phuc=phuc+1;
goto loop;
}
if (gphuc==0)
{

[Year]
phuc=phuc-1;
goto loop;
}
if (tgio==0)
{
gio=gio+1;
goto loop;
}
if (ggio==0)
{
gio=gio-1;
goto loop;
}
goto lap1;
loop:
if (phuc==60)
{
phuc=0;
}
if (phuc==-1)
{
phuc=59;
}
if (gio==24)
{
gio=0;
}
if (gio==-1)
{
gio=23;
}

[Year]
lap: nhienthi();
if (tphuc==0||gphuc==0||tgio==0||ggio==0)
{
goto lap;
}
lap1:
if (start==0)
{
break;
}
nhex_bcd();
nhienthi();
}
}
//Chuong trinh ngat TMR0

#int_timer0
void interrupt_timer0()
{
set_timer0(6);
++count;
if(count ==500)//qua chia 4, (250 ngat),chia 2
{
count=0;
giay=giay+1;
}
}
void hex_bcd()
{

[Year]
chgiay=giay/10;
dvgiay=giay%10;
chphuc=phuc/10;
dvphuc=phuc%10;
chgio=gio/10;
dvgio=gio%10;
}
void hienthi()
{
i=0;
while(i<5)
{
portc=dig[dvgiay];
delay_ms(1);
output_low(pin_d0);
portc=dig[chgiay];
delay_ms(1);
output_low(pin_d1);
portc=dig[dvphuc];
delay_ms(1);
output_low(pin_d2);
portc=dig[chphuc];
delay_ms(1);

[Year]
output_low(pin_d3);
portc=dig[dvgio];
delay_ms(1);
output_low(pin_d4);
portc=dig[chgio];
delay_ms(1);
output_low(pin_d5);
i=i+1;
}
}
//Chuong trinh chinh

void main(void)
{
trisb=1;
trisd=0;
trisc=0;
intcon=0xb0;
enable_interrupts(int_timer0);
enable_interrupts(global);
giay =0;
phuc=0;
gio=0;

[Year]
while(true)
{
if(giay==60)
{
giay=0;
phuc=phuc+1;
}
if (phuc==60)
{
phuc=0;
gio=gio+1;
}
if (gio==24)
{
gio=0;
}
hex_bcd();
hienthi();
}
}
PHN C: LP TRNH AVR BNG PHN MN CODE VISION
I. TM HIU V AVR
AVR l tn ca ca 1 h vi iu khin do AtmeL sn xut (Atmel cng l nh
sn xut cc vi iu khin h 89C51 m bn c th tng nghe n).
Thanh ghi bn trong chip l thanh ghi c cu trc 8 bit.
RISC (Reduced Instruction Set Computer) l 1 kiu cu trc ph bin ca cc b
x l.
AVR c nhiu c tnh hn hn:c trong tnh ng dng (d s dng) v c bit l v
chc nng
Gn nh chng ta khng cn mc thm bt k linh kin ph no khi s dng AVR,

thm ch khng cn ngun to xung clock cho chip (thng l cc khi thch anh).
Thit b lp trnh (mch np) cho AVR rt n gin, c loi mch np ch cn vi

[Year]
in tr l c th lm c. mt s AVR cn h tr lp trnh on chip bng
bootloader khng cn mch np
Bn cnh lp trnh bng ASM, cu trc AVR c thit k tng thch C
Ngun ti nguyn v source code, ti liu, application notert ln trn internet.
Hu ht cc chip AVR c nhng tnh nng (features) sau:
C th s dng xung clock ln n 16MHz, hoc s dng xung clock ni ln n

8 MHz (sai s 3%)
B nh chng trnh Flash c th lp trnh li rt nhiu ln v dung lng ln, c

SRAM (Ram tnh) ln, v c bit c b nh lu tr lp trnh c EEPROM.
Nhiu ng vo ra (I/O PORT) 2 hng (bi-directional) 8bits,16 bits timer/counter

tch hp PWM
Cc b chuyn i Analog Digital phn gii 10 bits, nhiu knh.

Chc nng Analog comparator.
Giao din ni tip USART (tng thch chun ni tip RS-232)
Giao din ni tip Two Wire Serial (tng thch chun I2C) Master v Slaver.
Giao din ni tip Serial Peripheral Interface (SPI)

[Year]
ALU
ALU lm vic trc tip vi cc thanh ghi chc nng chung. Cc php ton c thc
hin trong mt chu k xung clock. Hot ng ca ALU c chia lm 3 loi: i s,
logic v theo bit.
Thanh ghi trng thi

y l thanh ghi trng thi c 8 bit lu tr trng thi ca ALU sau cc php tnh
s hc v logic.
Hnh 2.2. Thanh ghi trng thi SREG
C: Carry Flag ;c nh (Nu php ton c nh c s c thit lp)

Z: Zero Flag ;C zero (Nu kt qu php ton bng 0)
N: Negative Flag (Nu kt qu ca php ton l m)
V: Twos complement overflow indicator (C ny c thit lp khi trn s b 2)
V, For signed tests (S=N XOR V) S: N
H: Half Carry Flag (c s dng trong mt s ton hng s c ch r sau)
T: Transfer bit used by BLD and BST instructions(c s dng lm ni chung gian
trong cc lnh BLD,BST).
I: Global Interrupt Enable/Disable Flag (y l bit cho php ton cc ngt. Nu bit ny
trng thi logic 0 th khng c mt ngt no c phc v.)
Cc thanh ghi chc nng chung
Hnh 2.3. Thanh ghi chc nng chung

[Year]
Con tr ngn xp (SP)

L mt thanh ghi 16 bit nhng cng c th c xem nh hai thanh ghi chc
nng c bit 8 bit. C a ch trong cc thanh ghi chc nng c bit l $3E (Trong
b nh RAM l $5E). C nhim v tr ti vng nh trong RAM cha ngn xp.
Hnh 2.4. Thanh ghi con tr ngn xp
Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo
ngn xp trong khi con tr ngn xp gim hai v tr. V con tr ngn xp s gim 1
khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s
tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy
con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi
mt chng trnh con c gi hoc cc ngt c cho php phc v. V gi tr
ngn xp t nht cng phi ln hn hoc bng 60H (0x60) v 5FH tr li l vng cc
thanh ghi.
Qun l ngt
Ngt l mt c ch cho php thit b ngoi vi bo cho CPU bit v tnh trng sn
xng cho i d liu ca mnh.V d:Khi b truyn nhn UART nhn c mt byte
n s bo cho CPU bit thng qua c RXC,hc khi n truyn c mt byte th
c TX c thit lp
Khi c tn hiu bo ngt CPU s tm dng cng vic ng thc hin li v lu v

tr ang thc hin chng trnh (con tr PC) vo ngn xp sau tr ti vector phuc
v ngt v thc hin chng trnh phc v ngt ch ti khi gp lnh RETI (return
from interrup) th CPU li ly PC t ngn xp ra v tip tc thc hin chng trnh
m trc khi c ngt n ang thc hin. Trong trng hp m c nhiu ngt yu cu
cng mt lc th CPU s lu cc c bo ngt li v thc hin ln lt cc ngt
theo mc u tin .Trong khi ang thc hin ngt m xut hin ngt mi th s xy ra
hai trng hp. Trng hp ngt ny c mc u tin cao hn th n s c phc
v. Cn n m c mc u tin thp hn th n s b b qua.

[Year]
B nh ngn xp l vng bt k trong SRAM t a ch 0x60 tr ln. truy
nhp vo SRAM thng thng th ta dng con tr X,Y,Z v truy nhp vo SRAM
theo kiu ngn xp th ta dng con tr SP. Con tr ny l mt thanh ghi 16 bit v
c truy nhp nh hai thanh ghi 8 bit chung c a ch :SPL
:0x3D/0x5D(IO/SRAM) v SPH:0x3E/0x5E.
Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu
vo ngn xp trong khi con tr ngn xp gim hai v tr.V con tr ngn xp s gim
1 khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s
tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy
con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi
mt chng trnh con c gi hoc cc ngt c cho php phc v. V gi tr
ngn xp t nht cng phi ln hn 60H (0x60) v 5FH tr li l vng cc thanh ghi.
V d:
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
B nh chng trnh (B nh Flash)
B nh Flash 16KB ca ATmega16 dng lu tr chng trnh. Do cc lnh

ca AVR c di 16 hoc 32 bit nn b nh Flash c sp xp theo kiu 8KX16.
B nh Flash c chia lm 2 phn, phn dnh cho chng trnh boot v phn dnh
cho chng trnh ng dng.

[Year]
Hnh 3.1. Bn b nh chng trnh
3.2. B nh d liu SRAM
1120 nh ca b nh d liu nh a ch cho file thanh ghi, b nh I/O v b

nh d liu SRAM ni. Trong 96 nh u tin nh a ch cho file thanh ghi v
b nh I/O, v 1024 nh tip theo nh a ch cho b nh SRAM ni.

[Year]
Hnh 3.2. Bn b nh d liu SRAM
B nh d liu EEPROM
ATmega16 cha b nh d liu EEPROM dung lng 512 byte, v c sp xp

theo tng byte, cho php cc thao tc c/ghi tng byte mt.
Cc cng vo ra (I/O)
Vi iu khinATmega16c 32 ng vo ra chia lm bn nhm 8 bit mt. Cc

ng vo ra ny c rt nhiu tnh nng v c th lp trnh c. y ta s
xt chng l cc cng vo ra s. Nu xt trn mt ny th cc cng vo ra ny
l cng vo ra hai chiu c th nh hng theo tng bit. V cha c in tr
pull-up (c th lp trnh c). Mc d mi port c cc c im ring nhng
khi xt chng l cc cng vo ra s th dng nh iu khin vo ra d liu
th hon ton nh nhau. Chng ta c thanh ghi v mt a ch cng i vi

[Year]
mi cng, l : thanh ghi d liu cng (PORTA, PORTB, PORTC,
PORTD), thanh ghi d liu iu khin cng (DDRA, DDRB, DDRC, DDRD)
v cui cng l a ch chn vo ca cng (PINA, PINB, PINC, PIND).
Thanh ghi DDRx
y l thanh ghi 8 bit (ta c th c v ghi cc bit thanh ghi ny) v c tc

dng iu khin hng cng PORTx (tc l cng ra hay cng vo). Nu nh mt bit
trong thanh ghi ny c set th bit tng ng trn PORTx c nh ngha nh
mt cng ra. Ngc li nu nh bit khng c set th bit tng ng trn PORTx
c nh ngha l cng vo.
Thanh ghi PORTx
y cng l thanh ghi 8 bit (cc bit c th c v ghi c) n l thanh ghi d

liu ca cng Px v trong trng hp nu cng c nh ngha l cng ra th khi ta
ghi mt bit ln thanh ghi ny th chn tng ng trn port cng c cng mc
logic. Trong trng hp m cng c nh ngha l cng vo th thanh ghi ny li
mang d liu iu khin cng. C th nu bit no ca thanh ghi ny c set (a
ln mc 1) th in tr ko ln (pull-up) ca chn tng ng ca port s c
kch hot. Ngc li n s trng thi hi-Z. Thanh ghi ny sau khi khi ng Vi
iu khins c gi tr l 0x00.
Thanh ghi PINx
y l thanh ghi 8 bit cha d liu vo ca PORTx (trong trng hp PORTx

c thit lp l cng vo) v n ch c th c m khng th ghi vo c.
Tm li:
1. c d liu t ngoi th ta phi thc hin cc bc sau:
a d liu ra thanh ghi iu khin DDRxn t cho PORTx (hoc bit n trong
port) l u vo (xa thanh ghi DDRx hoc bit).
Sau kch hot in tr pull-up bng cch set thanh ghi PORTx ( bit).
Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit).
2. a d liu t vi iu khin ra cc cng cng c cc bc hon ton tng t.

Ban u ta cng phi nh ngha l cng ra bng cch set bit tng ng ca
cng .v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx.

[Year]
B nh thi
B nh thi (timer/counter0) l mt module nh thi/m 8 bit, c cc c

im sau:
B m mt knh
Xa b nh thi khi trong mode so snh (t ng np)
PWM
To tn s
B m s kin ngoi
B chia tn 10 bit
Ngun ngt trn b m v so snh
S cu trc ca b nh thi:
Hnh 5.1. S cu trc b nh thi
Cc thanh ghi
TCNT0 v OCR0 l cc thanh ghi 8 bit. Cc tn hiu yu cu ngt u nm trong thanh

ghi TIFR. Cc ngt c th c che bi thanh ghi TIMSK.
B nh thi c th s dng xung clock ni thng qua b chia hoc xung clock ngoi
trn chn T0. Khi chn xung clock iu khin vic b nh thi/b m s dng
ngun xung no tng gi tr ca n. Ng ra ca khi chn xung clock c xem
l xung clock ca b nh thi (clkT0).

[Year]
Thanh ghi OCR0 lun c so snh vi gi tr ca b nh thi/b m. Kt qu so snh
c th c s dng to ra PWM hoc bin i tn s ng ra ti chn OC0.
n v m
Phn chnh ca b nh thi 8 bit l mt n v m song hng c th lp trnh c.

Cu trc ca n nh hnh di y:
Hnh 5.2. n v m
count: tng hay gim TCNT0 1

direction: la chn gia m ln v m xung
clear: xa thanh ghi TCNT0
clkT0: xung clock ca b nh thi
TOP: bo hiu b nh thi tng n gi tr ln nht
BOTTOM: bo hiu b nh thi gim n gi tr nh nht (0)
n v so snh ng ra
Hnh 5.3. S n v so snh ng ra

[Year]
B so snh 8 bit lin tc so snh gi tr TCNT0 vi gi tr trong thanh ghi so snh ng ra

(OCR0). Khi gi tr TCNT0 bng vi OCR0, b so snh s to mt bo hiu. Bo
hiu ny s t gi tr c so snh ng ra (OCF0) ln 1 vo chu k xung clock tip
theo. Nu c kch hot (OCIE0=1), c OCF0 s to ra mt ngt so snh ng ra v
s t ng c xa khi ngt c thc thi. C OCF0 cng c th c xa bng
phn mm.
M t cc thanh ghi
Thanh ghi iu khin b nh thi/b m TCCR0
Hnh 5.4. Thanh ghi iu khin b nh thi
Bit 7-FOC0: So snh ng ra bt buc

Bit ny ch tch cc khi bit WGM00 ch nh ch lm vic khng c PWM.
Khi t bit ny ln 1, mt bo hiu so snh bt buc xut hin ti n v to dng
sng.
Bit 6, 3-WGM01:0: Ch to dng sng
Cc bit ny iu khin m th t ca b m, ngun cho gi tr ln nht ca b
m (TOP) v kiu to dng sng s c s dng.
Bit 5:4-COM01:0: Ch bo hiu so snh ng ra
Cc bit ny iu khin hot ng ca chn OC0. Nu mt hoc c hai bit
COM01:0 c t ln 1, ng ra OC0 s hot ng.
Bit 2:0: CS02:0: Chn xung ng h
Ba bit ny dng la chn ngun xung cho b nh thi/b m.

[Year]
Thanh ghi b nh thi/b m
Hnh 5.5. Thanh ghi b nh thi

Thanh ghi b nh thi/b m cho php truy cp trc tip (c c v ghi) vo b
m 8 bit.
Thanh ghi so snh ng ra-OCR0
Hnh 5.6. Thanh ghi so snh ng ra
Thanh ghi ny cha mt gi tr 8 bit v lin tc c so snh vi gi tr ca b

m.
Thanh ghi mt n ngt
Hnh 5.7. Thanh ghi mt n ngt TIMSK
Bit 1-OCIE0: Cho php ngt bo hiu so snh

Bit 0-TOIE0: Cho php ngt trn b m
Thanh ghi c ngt b nh thi
Bit 1-OCF0: C so snh ng ra 0

Bit 0-TOV0: C trn b m
Bit TOV0 c t ln 1 khi b m b trn v c xa bi phn cng khi

vector ngt tng ng c thc hin. Bit ny cng c th c xa bng phn
mm.

[Year]
V. CU TRC LNH CA CODE VISION
CC TON T:
+ php cng - Php tr

* php nhn / php chia ly kt qu
% php chia ly s d ++ php cng rt gn
-- php tr rt gn = bng
== so snh bng ~ o
! != khc
< so snh nh hn > so snh ln hn
<= so snh nh hn hoc bng >= so snh ln hn hoc bng
& and && and theo bit
| or || or theo bit
^ lu tha ?:
<< dch tri(1) >> dch phi(1)
-= gim += tng
/= chia %= ly d
&= and v lu kt qu *= nhn v lu kt qu
^= lu tha v lu kt qu |= or v lu kt qu
>>= dch tri v lu kt qu <<= dch phi v lu kt qu
KIU D LIU:
Type Size (Bits) Range

Bit 1 0,1
bool, _Bool 8 0,1
char 8 -128 to 127
unsigned char 8 0 to 255
signed char 8 -128 to 127
int 16 -32768 to 32767
short int 16 -32768 to 32767
unsigned int 16 0 to 65535
signed int 16 -32768 to 32767
long int 32 -2147483648 to 2147483647
unsigned long int 32 0 to 4294967295
signed long int 32 -2147483648 to 2147483647
float 32 1.175e-38 to 3.402e38
double 32 1.175e-38 to 3.402e38

[Year]
Cc cu trc lnh c bn:
-Lnh iu kin:
-If( ) {
Cc cu lnh;
};
-If( ) {
Cc cu lnh;
}
Else {
Cc cu lnh;
}
-Vng lp c iu kin:
-do {
Cc cu lnh;
}
while( );
-while( ){
Cc cu lnh;
};
-for( ; ; ;){
Cc cu lnh;
};
-La chn:
-switch( ){
case:
Cc cu lnh;

};

[Year]
I. HNG DN S DUNG LP TRNH AVR BNG CODE VISION
Cch to ra mt project mi trong Codevision lp trnh v np cho AVR:
>> Vo File/New/project/ok/yes mt bng hin ra nh sau:
>> Chip: chn loi chip mnh nh lp trnh, gi tr thch anh ngoi (mc trn mch)
>> Port: t y bn c th chn vo ra gi tr cho tng chn ca chip.
Bn to mt Project xong, vo mc Project/configude:
Chn Add , chn file lp trnh ca bn
Mc ny bn c th thay i gi tr thch anh , loi AVR, s bit bn cn lp trnh
Chn nh trn khi n shiflt F9 bn s bin dch v np trc tip t Codevision.
IV. MODUL NG DNG V CHNG TRNH M PHNG

MODUL 1: LED DN
S m phng

[Year]
Chng trnh:
#include <mega16.h>
#include <delay.h>
void main()
{
int i;
DDRA=0xff;
DDRB=0xff;
DDRC=0xff;
DDRD=0xff;
while(1)
{
PORTA=0X01; //sang dan portA
PORTB=0X00;
PORTC=0X00;
PORTD=0X00;
delay_ms(20);
for(i=0;i<7;i++)
{
PORTA=PORTA<<=1; //dich phai va luu ket qua

[Year]
delay_ms(20);
}
PORTA=0x00;
PORTB=0x01; //sang dan portB
delay_ms(20);
for(i=0;i<7;i++)
{
PORTB=PORTB<<=1;
delay_ms(20);
}
PORTB=0x00;
PORTC=0x01;
delay_ms(20);
for(i=0;i<7;i++)
{
PORTC=PORTC<<=1; //sang dan portC
delay_ms(20);
}
PORTC=0x00;
PORTD=0x01;
delay_ms(20);
for(i=0;i<9;i++)
{
PORTD=PORTD<<=1; //sang dan portD
delay_ms(20);
}
PORTD=0X80;
delay_ms(20);
for(i=0;i<7;i++)

[Year]
{
PORTD=PORTD>>=1;//dich trai va luu ket qua
delay_ms(20);
}
PORTD=0x00;
PORTC=0x80;
delay_ms(20);
for(i=0;i<7;i++)
{
PORTC=PORTC>>=1;
delay_ms(20);
}
PORTC=0x00;
PORTB=0x80;
delay_ms(20);
for(i=0;i<7;i++)
{
PORTB=PORTB>>=1;
delay_ms(20);
}
PORTB=0x00;
PORTA=0x80;
delay_ms(20);
for(i=0;i<9;i++)
{
PORTA=PORTA>>=1;
delay_ms(20);
}

[Year]
}
}
MODUL 2: LED 7ON

S m phng:
Chng trnh:
#include <mega8515.h>
int gio=0,phut=0,giay=0,dem=0;
void hienthi();
// Timer 1 overflow interrupt service routine
interrupt [TIM1_OVF] void timer1_ovf_isr(void)
{
// dat truoc gia tri cho timer1
TCNT1H=0x3CEF >> 8;
TCNT1L=0x3CEF & 0xff;
dem++;
if(dem==20)

[Year]
{
dem=0;
giay++;
if(giay==60)
{
giay=0;
phut++;
if(phut==60)
{
phut=0;
gio++;
if(gio==24)
{
gio=0;
};
};
};
};
}
void main(void)
{
PORTA=0x00;
DDRA=0xFF;
PORTC=0x00;
DDRC=0xFF;
// gia tri xung clock 1000.000 kHz
// Che do dem binh thuong, gia tri lon nhat la FFFFh
// Ngat timer 1
TCCR1A=0x00;

[Year]
TCCR1B=0x02;
TCNT1H=0x3C;
TCNT1L=0xEF;
TIMSK=0x80;
#asm("sei") // Cho phep ngat toan cuc
while (1)
{
hienthi();
};
}
void hienthi()
{
int
i,j,ma7doan[11]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90,0xb
f};
int tam[8];
tam[0]=giay%10;
//tam[1]=giay/10;
tam[1]=0;
tam[2]= 10;
tam[3]=phut%10;
tam[4]=phut/10;
tam[5]= 10;
tam[6]=gio%10;
tam[7]=gio/10;
PORTC=0x80;
for(i=0;i<8;i++)
{

[Year]
PORTA=ma7doan[tam[i]];
for(j=0;j<=2000;j++)
{
#asm
nop
#endasm
}
PORTA=0xff;
PORTC>>=1;
}
MODUL 3: LCD
S m phng
Chng trnh:
#include <mega16.h>
#include <delay.h>
#define RS PORTA.0
#define RW PORTA.1
#define E PORTA.2
#define LCD PORTC

[Year]
void ktao_LCD();
void ghi_data();
void ghi_lenh();
const unsigned char ndung1[]="Truong Su pham ky thuat tp Ho Chi Minh";
const unsigned char ndung2[]="Khoa dien-dien tu";
const unsigned char ndung3[]=" **Mon hoc vi xu ly**
";
void main()
{ int i,j;
DDRA=0xff;
DDRC=0xff;
ktao_LCD();
LCD=0x81; //Hien thi ndung1 len dong 1 va 2
ghi_lenh();
for(i=0;i<18;i++)
{
LCD=ndung1[i];
ghi_data();
};
LCD=0xC0;
ghi_lenh();
for(i=18;i<38;i++)
{
LCD=ndung1[i];
ghi_data();
};
LCD=0x95; //Hien thi ndung2 len dong 3
ghi_lenh();
for(i=0;i<17;i++)

[Year]
{
LCD=ndung2[i];
ghi_data();
};
for(i=0;i<41;i++)
{ LCD=0xD5; //Chay ndung3 tu phai sang trai tren dong 4
ghi_lenh();
for(j=i;j<i+20;j++)
{
LCD=ndung3[j];
ghi_data();
};
delay_ms(5);
};
for(i=41;i>=0;i--)
{ LCD=0xD5; //Chay ndung3 tu trai sang phai tren dong 4
ghi_lenh();
for(j=i;j<i+20;j++)
{
LCD=ndung3[j];
ghi_data();
};
delay_ms(5);
};
for(i=0;i<=5;i++)
{ LCD=0xD3; //Nhap nhay ndung3 5lan
ghi_lenh();
for(j=0;j<20;j++)

[Year]
{
LCD=ndung3[j];
ghi_data();
}
delay_ms(10);
LCD=0xD3;
ghi_lenh();
for(j=19;j<40;j++)
{
LCD=ndung3[j];
ghi_data();
}
}
}
void ktao_LCD()
{
LCD=0x38; //Khoi tao ma tran 5x7
ghi_lenh();
LCD=0x0C; //Bat hient thi
ghi_lenh();
LCD=0x1; //Xoa man hinh
ghi_lenh();
}
void ghi_lenh()
{
RS=0;
RW=0;
E=1;
E=0;

[Year]
delay_ms(1);
}
void ghi_data()
{
RS=1;
RW=0;
E=1;
E=0;
delay_ms(1);
}

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GVHD: NGUYN VN NGA 20/11/2009

PHN A: VIT NGN NG KEIL C CHO 89C51

PHN B: VIT NGN NG CCSC CHO PIC 16F877A

I. VI NT KHI QUT V PIC 16F877A

PHN C: LP TRNH CHO AVR BNG CODE VISION

SVTH:NGUYN VN BIN Page 1

c im v chc nng hot ng ca cc IC h MSC-51 hon ton tng t nh nhau. y

SVTH:NGUYN VN BIN Page 2

SVTH:NGUYN VN BIN Page 3

SVTH:NGUYN VN BIN Page 4

8951 c tt c 40 chn c chc nng nh cc ng xut nhp. Trong c 24 chn c

Port 0 l port c 2 chc nng cc chn 32 39 ca 8951. Trong cc thit k c nh

Port 2 l 1 port c tc dng kp trn cc chn 21 - 28 c dng nh cc ng xut

Port 3 l port c tc dng kp trn cc chn 10 - 17. Cc chn ca port ny c nhiu

SVTH:NGUYN VN BIN Page 5

- Tn hiu vo EA\ chn 31 thng c mc ln mc 1 hoc mc 0. Nu mc 1,

Ng vo RST chn 9 l ng vo Reset ca 8951. Khi ng vo tn hiu ny a ln cao

B dao ng c tch hp bn trong 8951, khi s dng 8951 ngi thit k ch cn kt

SVTH:NGUYN VN BIN Page 6

SVTH:NGUYN VN BIN Page 7

SVTH:NGUYN VN BIN Page 8

SVTH:NGUYN VN BIN Page 9

SVTH:NGUYN VN BIN Page 10

SVTH:NGUYN VN BIN Page 11

III. NGN NG KEIL C CHO 89C51

Trong k thut lp trnh cho vi iu khin, ngn ng lp trnh c chia lm 2 loi:

2. Cu trc chng trnh C

//Khai bo bin ton c_c

void Hm2(unsigned char x)

SVTH:NGUYN VN BIN Page 12

2.1.Cc kiu d liu hay dng trong Keil C

Trong C ta thng dng cc kiu d liu sau:

Dng bin S bytes S bits Min gi tr

Cu trc : Kiu bin Tn bin

Dng bin S bytes S bits Min gi tr

SVTH:NGUYN VN BIN Page 13

Loi ngt C ngt Ngun ngt a ch ngt

SVTH:NGUYN VN BIN Page 14

2.4. Cc lnh thng dng

SVTH:NGUYN VN BIN Page 15

SVTH:NGUYN VN BIN Page 16

IV. HNG DN S DNG KEIL C LP TRNH CHO 89C52

to 1 project mi chn Project / New Project

SVTH:NGUYN VN BIN Page 17

Hp thoi create new project hin ra:

SVTH:NGUYN VN BIN Page 18

SVTH:NGUYN VN BIN Page 19

to 1 file code mi bn chn File / New hoc nhn Ctrl + N.

SVTH:NGUYN VN BIN Page 20

SVTH:NGUYN VN BIN Page 21

2. Bin dch chng trnh v m phng:

SVTH:NGUYN VN BIN Page 22

Nu chng trnh ca bn c li th bn phi tin hnh sa cc li cho n khi khng

SVTH:NGUYN VN BIN Page 23

Sau bn tip tc bin dch li chng trnh ln na th file.hex s c to ra.

SVTH:NGUYN VN BIN Page 24

hin th cc Port cc thanh ghi bn chn trong Peripherals

SVTH:NGUYN VN BIN Page 25

no c du tick (P) th ang mc cao (5V) cn cc khng c du tick th

V. M PHNG MODUL NG DNG V CHNG TRNH MU

Modul 1: iu khin Led n hnh tri tim:

SVTH:NGUYN VN BIN Page 26

SVTH:NGUYN VN BIN Page 27