TL NO. oes sae cre see ee snes 2303 BE/B.Tech. 6th Sem. (ECE) Examination — May, 2014 Mosic's and Techielogy Paper : EE-306-E ne : Three hours ] [ Maximum Marks ; 100 ore answering the questions, candidates should ensuve that they e been supplied the correct and complete question paper. No iplaint in this regard, will be entertained after examination, te: Attempt any five questions, Ali questions carry equal marks. _ (a) What is channel length modulation in MOSFET ? How it can be avoided ? Explain. 10 (b) What is latch up problem in BICMOS and how it can be avoided ? 10 (a) Explain the structure and operation of enhancement mode type N-MOS device. 10 (b) Describe the various steps of a C-MOS fabrication process using twin tub technology. 10{b) Compare BJT's with FET's. 5 (c) In CMOS combinational circuit design why NAND gates are preferred over NOR gates & Explain with suitable example. 19 . What do you mean by term diffusion ? What is the difference between diffusion & Ion implantation ? Discuss Ion implantation in detail. 20 . Realize two input NAND gate using CMOS logic. Explain why NAND gate are preferred over OR gato. 20 . Explain in detail the operation of MOS transistor in enhancement and deptetion mode. 20 . Using CMOS combinational logic design, draw stick diagram and layout of 20 (a) (A+B+C).D (b) AND gate (c) NOT gate (d) OR gate . Write short note on the following : 20 {a) NMOS fabrication. (b) Resistance, . capacitance and inductance estimation. (c) MOS transistor Parameter.