LIBRARY ieee;

USE ieee.std_logic_1164.all;
ENTITY funcion_a IS
PORT(A,B,C,D :IN STD_LOGIC;
F :OUT STD_LOGIC);
END funcion_a;
ARCHITECTURE tabla OF funcion_a IS
BEGIN
F<=(((B and D)or(A and not D))and(C or not B)) or
((Not C or (B and D)) and not (A or not D));
END tabla;