Scribd Logo
Upload

Welcome to Scribd!

  • 0485004f6b6c207e69d6c1b3bd928c3a_4ed6de48cf7dd9de07b73d4d7e054e1b

    Uploaded by

    Ishan Jindal
    13 views42 pages
    Computer NSEES Exam Sample Paperz..

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    Computer NSEES Exam Sample Paperz..

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    13 views42 pages

    0485004f6b6c207e69d6c1b3bd928c3a_4ed6de48cf7dd9de07b73d4d7e054e1b

    Uploaded by

    Ishan Jindal
    Computer NSEES Exam Sample Paperz..

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 42
    501. A floating-point number is stored in the following format: ¢ af ByteO Byte 1 7T6[sT4[3T2Tilol7[éTs[4 [3 [21170 Sign Bacess-64 exponent __ Normalized Mantissa Fraction ‘The numerical valu sven by the following expression: Cyr? 2-68 9 0.1 EF Assume all floating exponents are stored in excess-64 format, and each “f" in the expression represents bit in Byte 1. ‘The mantissa is represented as a 9-bitfraetion with the radix point to the far left. The mantissa is normalized so the most significant bit is 1. The leftmost bit is then suppressed and the remaining bits are placed in Byte 1 The decimal value 111.875 is stored in this format and then returned for printing, The resulting printout is: (A) TLS (B) ILS (©) 111875 ( (D) 1120 502. A cyolic redundancy check (CRC) generator is based on what operation? A ®) © (D) Exelusive-OR Modulo-2 division Bit wise add with carry ‘Two's complement addition. 503. The CPU architecture shown in the figure below is best described as: (A) @) © @) non-pipelined architecture 1-stage pipeline architecture 2estage pipeline architecture Harvard architecture FROM MEMORY INSTRUCTION REGISTER CONTROL SELECT ‘SELECT SELECT LATCH REGISTER REGISTER: ‘OPERATION RESULT it microprocessor are shown inthe figure boloy @ unsigned binary notatioh, 504, Rotate and shift instructions available on an 8. Accumulator B of the processor has been loaded with (SA)ie. Assur ‘what will be the contents of Accumulator B after thee rotate lefts? (A) (-46)10 (By (180)10 (©) 105) (D) (2100 505, A Branch Control Logic Block (BCLB) is used within an Arithmetic Logi Unit (ALU) to generate the condition codes necessary for BRANCH ON CONDITION instruction codes. An overview of the proposed system is shown below. The inputs to the BCLB system include two 4-bit words on the A and B data bus, with corresponding output contro! signals as follows: + G[A=B](A data bus value is greater chan the B data bus value). E [A=B] (A daia bus value is equal to the B date bus value). +L [AB for previous stage] LIT - LESS‘THAN input [A % © 8 inputs, Oy) 1 I Oy) "ACTIVE LOW" Os) ‘OUTPUTS o—a, 3 or Ei os se 517. Input X is an asynchronous input to the synchronous state mac diagram below. Considering the p inc described by the state ity that input X may change st any time with respect to the state machine clock, the possible next states for State 01 are: w @) © © 01, 10 01, 10, 00 00, 01, 10, 11 10, 00 518. ‘The synchronous digital circuit below has input CLIC and output Q2, Assume positive tgif the current state ofthe synehronons circuit is QyQ3Q5= 100, the next state will bet (a) 010 @) on (©) 100 110 & a4 1, & Q] BO y ope a hy, @R ae Ss cuxe———_ 519, The microprocessor-based data acquisition system shown below samples an analog sional processes it digitally, and then converts the processed signal back to analog form. The system uses dala converter circuits with the following characteristics: AMD: bit offéct binary, unity gain, bipolar —5 V to +5 V;—5 V corresponds to (0000): ‘DIA: 4-bit offset binary, unity gain, unipolar, +10 V; 0 V corresponds to (0000)2 ANALOG__,| 4.BIT MICRO- 43Ir ANALOG INPUT AD Processon [7 pa | ouruT For ab input voltage of +2.0 V, the A/D converter output code is most nearly: (A) OLD: B) 0100). © d0lbe ©) (0D: COMPUTER ENGINEERING PM PRACTICE EXAM 520. The Bode plot for the circuit shown for 4 = ¥2/V; is most nearly: ee A) |Alan, ( ow ee ® © © Copyright 2011 by NCEES. 4 GOON TO THE NEXT PAGE, This questio vestigate the performance of he temperature measurement circuit ilstated F the figure below ‘The temperature sensor is linear, with the following open: ¥s=OmvV aO°C Fs= 100 mV at 100°C rouil voltages: ‘The operational amplifier (op amp) is ideal. At 100°C, the maximum output voltage at Yo (V) due to the tolerance in Rp is most nesrly: (A) 2.5 ® 52 (C) 104 (D) 153 522. Consider the following nested loop: For/=1 tom Forj=1 toi Foo (/); How many times will the Foo function be called? (A) nti (BR) n*(m-1)/2 (CQ) nti @) nt@tiya 523. For an output frequency of' 400 Hy, the clock frequency (Hz) is most nearly: (A) 400 (B) 800 C—_ a] ©) 1200 pq dp a a 1600 a} {| -frso) all ~ THs) Tan) 524. A synchronous counter circuit is implemented using a 3-bit linear feedback shift register (LFSR) 4s shown below. During the rising edge of each clock pulse, the LFSR shifis the register contents from the D; position to the D+: position. Assume that the LI'SR is initialized with DsD)Ds = 001, The number of states the cireuit cycles through is most nearly: (A) 2 7 ® 3 Pa | Bi | Dy © 7 PE Kd 525. COMPUTER ENGINEERING PM PRACTICE EXAM Consider the following verilog HDL module: ¢ module PEI (eid); output [3:0] d: input [1:0] i; input e; reg [3:0] wire [1:0] is always @ (ior e) if(e=1) begin case (i) 0: d=4'b 0001; 1: d=4'b 0010; 2: d=4'b 0100; 3: d=4'b 1000; default d= 4b xxxx; endcase, end else d=4'b 0000; endmodule € ‘The verilog HDL module PEI implements what can best be described as a: (A) 2+to-4 decoder (B) _ 2-to-4 decoder with enable (C) — 4-to-1 multiplexer (D) — 4+to-1 multiplexer with enable Copyright 2011 by NCEES 44 GO ON TO THE NEXT PAGE 526. A designer wishes 1o model a synchronous circuit with an active low asynchronous reset signal named "reset", When a reset occurs, the port named "out* is driven by "a", Which of the following verilog code segments is accurate? (A) always @ (posedge clk or posedge reset) if (reset =~ 1'b1) out = a5 else out (B) always @ {posedge clk or nogedge reset) if (reset = 1'B0) out =a; else out (© always @ (negedge elk or posedge reset) if(elk = V1) out= a else out = b; (D) always @ (negedge clk or negedge reset) if (elk = 'b0) out else out =b; 527. Which of the following i it a method that is used by unauthorized users to gain access to a ‘computer system? (A) Using a system password of an authorized user that was left in plain sight near a computer terminal. (B) _Snatching passwords from the first few packets of a telnet session, (© Calling on the telephone and pretending to be a system administrator fixing a system problem. During the course of the "troubleshooting session” the system password is requested from the authorized user, (D) Sending a plaintext e-mail message to a remote computer system in order to gain unauthorized access to the computer system 528, The following polynomial is used for a CRC generation ¢ Pastas Sad ‘What is an equivalent hex word for this polynomial that could be used to gencrate a double-byte cre? (A) (0215 (B) 4086 © (810)6 @) 88216 529. Which of tho following attributes best describe the goals of hard real-time operating systent? Capacity Responsiveness Overload (A) High throughput Fast average response Fairness (B) Schedulability _‘Ensured worst-case latency Stability (C) Schedulability Fast average response Stability (D) High throughput —Ensured worst-case latency Faimess 530. An important step in the software life eycle is developing detailed software specifications. Which of the following must be included for software specifications to be complete? “& ®) © ©) ‘A detailed description of the expected inputs and the expected outputs AA detailed description of the processing requirements A description of key assuraptic Alll of the above are required in detailed software specifications. 15 made in interpreting design requirements 531. The ideal software life cycle consists of many different phases, including requirements, specifications, design, code, module test, integration test, and maintenance. Of these phases, Which is generally the most expensive in terms of resourcas exponded? (A) Requirements phase (B) Coding phase (©) Iniegration phase (D) Maintenance phase 532, Which of the following is a peer review technique for verifying a software product?” (A) Proofs of correctness (B) Structural testing ©) Inspection @) Acceptance qualification 533. A set of n bags of different sizes must be arranged using the minimum possible space. What is the time complexity ofthis problem? (A) Exponential B) Linear (C) Logarithmic ) Quadratic COMPUTER ENGINEERING PM PRACTICE EXAM 534. ‘The Fibonacci series is a sequence of numbers where the next Fibonacci number is the sum the previous two. The series begins | | 23 58 13 21... A function F(n) is required to caloulat the n'* Fibonacci number, For example, (7) would cetum 13. The following three designs, pseudocode, were submitted. Sample A Line # 1 Sample B Line # 1 2 3 4 5 6 7 8 9 10 IL 12 13 SampleC Line # 1 2 3 4 5 6 7 8 9 10 i 12 13, 14 15 Copyright 2011 by NCEES in Description Function F (input:n) Check _for_illegal_input If (time to_stop recursion) Then Return (the_correct_value) Else Return (FUr-1) + F(a-2)) Description Function F (input:n) Local Variables: i, currentf, prevf ‘Check_for_illegal_input is current{= 1 prevf=0 While (

    You might also like