Question 01 50 Marks

a. Describe the different between Behavioral, Structural and Dataflow descriptions

methods in hardware description language by providing appropriate example.
[8 Marks]
b. Sketch the logic-gate equivalent circuit for the Verilog HDL module listed below,
module M1 (input x,y output z);
wire w1, w2, w3;
not nt1 (w1, x);
and n1 (w2, w1, y);
not nt2 (w3, w2);
or x1 (z, w3,w1);
endmodule

[10 Marks]
c. For the above given programme in question 1b, write the simplified Boolean equation
for output z.
[6 Marks]
d. Write the data flow description for simplified Boolean expression.
[6 Marks]
e. Consider the following combinational logic gate,

Fig Q1: M1 Module

i. Derive the F1 and F2 logic equation and simplify.
ii. Write the structural model Verilog HDL programme for above module.
iii. Write the Dataflow model Verilog HDL programme for above module.
[20 Marks]

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