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-- Company:
-- Engineer:
--
-- Create Date: 14:52:19 06/22/2017
-- Design Name:
-- Module Name: RegContador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RegContador is
PORT (
clk : IN STD_LOGIC;
areset : IN STD_LOGIC;
cnt_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end RegContador;

architecture Behavioral of RegContador is

signal cnt_tmp: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";

begin
proceso_contador: process (areset, clk)
begin
if (areset = '1' or cnt_tmp= "01100011") then
cnt_tmp <= "00000000";
end if;
if rising_edge(clk) then
cnt_tmp <= cnt_tmp + 1;
end if;
end process;

cnt_out <= cnt_tmp;

--process
end Behavioral;