module adc_module(

input fpga_clk_50,
input Rst,
input Sdi, //FPGA_ADC_Din
output reg Conv_strt,
output reg Sdo, //FPGA_ADC_Dout
output ADC_Sck,
input adc_busy,
output reg [15:0]ADC_Data,
input Adc_Read,
input [2:0]Channel
);

reg [15:0]Data1 = 16'h0011; //16'h0011; //hC400

reg [15:0]Data2 = 16'h0013;
reg [15:0]Data3 = 16'h0019;
reg [15:0]Data4 = 16'h001B;

reg Sck_En;
reg [15:0]Rece_data;
reg [4:0]counter = 0;
reg [79:0]Var = 80'h00000000000000000001;
reg Sck;

assign ADC_Sck = Sck;

//assign Adc_En = 1'b0;

always @(posedge fpga_clk_50)

begin
counter = counter + 1'b1;
end

always @(posedge counter[2] or negedge Rst)

begin
if(!Rst)
Sck=0;
else
begin
if(Adc_Read)
begin
Var = {Var[78:0],Var[79]};
if(Sck_En)
Sck=~Sck;
else
Sck=0;
end
else
Var = 80'h00000000000000000001;
end

end
always @(posedge Sck)
begin
case (Channel[2:0])
3'b000 : begin
Sdo=Data1[0];
Data1 = {Data1[0],Data1[15:1]};
end
 3'b001 : begin
Sdo=Data2[0];
Data2 = {Data2[0],Data2[15:1]};
end
3'b010 : begin
Sdo=Data3[0];
Data3 = {Data3[0],Data3[15:1]};
end
3'b011 : begin
Sdo=Data4[0];
Data4 = {Data4[0],Data4[15:1]};
end

default: begin

end
endcase

end

always @(negedge Sck)

begin

Rece_data = {Rece_data[14:0],Sdi};

end

always @(posedge Var[38] or posedge Var[41])

begin
if(Var[38])
Conv_strt=1'b1;
else
Conv_strt=1'b0;
end
always @(posedge Var[33] or posedge Var[1])
begin
if(Var[33])
begin
Sck_En = 0;
end
else
begin
Sck_En = 1;

end
end

always @(posedge adc_busy)

begin

ADC_Data[15:0] = Rece_data[15:0];

end

//always @(posedge Sck)

//begin
//count = count + 1'b1;
//end
endmodule